mirror of https://github.com/hak5/openwrt.git
generic: ar8216: add support for ar8229
ar8229 is the builtin switch in ar934x and later chips. There is also a standalone version available and their registers/functions are the same. This commit added support for the builtin ar8229. The only thing missing for standalone ar8229 should be phy modes. Since I don't have a router using that, this commit doesn't add support for other phy modes. Only add its support for mdio-device probing method because the current PHY probing can't return 1G speed when it's a FE switch. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>openwrt-19.07
Chuanhong Guo
Petr Štetiar
parent
7d504f68a6
commit
cb7d96499c
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@ -25,6 +25,7 @@
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#include <linux/netlink.h>
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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#include <linux/bitops.h>
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#include <net/genetlink.h>
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#include <linux/switch.h>
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@ -715,7 +716,8 @@ ar8216_init_globals(struct ar8xxx_priv *priv)
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}
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static void
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ar8216_init_port(struct ar8xxx_priv *priv, int port)
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__ar8216_init_port(struct ar8xxx_priv *priv, int port,
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bool cpu_ge, bool flow_en)
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{
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/* Enable port learning and tx */
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ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
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@ -727,12 +729,11 @@ ar8216_init_port(struct ar8xxx_priv *priv, int port)
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if (port == AR8216_PORT_CPU) {
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ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
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AR8216_PORT_STATUS_LINK_UP |
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(ar8xxx_has_gige(priv) ?
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AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
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(cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
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AR8216_PORT_STATUS_TXMAC |
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AR8216_PORT_STATUS_RXMAC |
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(chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
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(chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
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(flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
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(flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
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AR8216_PORT_STATUS_DUPLEX);
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} else {
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ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
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@ -740,6 +741,13 @@ ar8216_init_port(struct ar8xxx_priv *priv, int port)
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}
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}
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static void
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ar8216_init_port(struct ar8xxx_priv *priv, int port)
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{
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__ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
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chip_is_ar8316(priv));
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}
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static void
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ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
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{
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@ -807,6 +815,85 @@ static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
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}
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}
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static int
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ar8229_hw_init(struct ar8xxx_priv *priv)
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{
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int phy_if_mode;
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if (priv->initialized)
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return 0;
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ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
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ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
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phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
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if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
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ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
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AR8229_OPER_MODE0_MAC_GMII_EN);
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} else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
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ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
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AR8229_OPER_MODE0_PHY_MII_EN);
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} else {
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pr_err("ar8229: unsupported mii mode\n");
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return -EINVAL;
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}
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if (priv->port4_phy)
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ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
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AR8229_REG_OPER_MODE1_PHY4_MII_EN);
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ar8xxx_phy_init(priv);
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priv->initialized = true;
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return 0;
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}
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static void
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ar8229_init_globals(struct ar8xxx_priv *priv)
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{
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/* Enable CPU port, and disable mirror port */
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ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
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AR8216_GLOBAL_CPUPORT_EN |
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(15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
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/* Setup TAG priority mapping */
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ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
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/* Enable aging, MAC replacing */
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ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
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0x2b /* 5 min age time */ |
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AR8216_ATU_CTRL_AGE_EN |
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AR8216_ATU_CTRL_LEARN_CHANGE);
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/* Enable ARP frame acknowledge */
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ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
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AR8229_QM_CTRL_ARP_EN);
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/* Enable Broadcast/Multicast frames transmitted to the CPU */
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ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
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AR8229_FLOOD_MASK_BC_DP(0) |
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AR8229_FLOOD_MASK_MC_DP(0));
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/* setup MTU */
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ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
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/* Enable MIB counters */
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ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
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AR8236_MIB_EN);
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/* setup Service TAG */
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ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
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}
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static void
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ar8229_init_port(struct ar8xxx_priv *priv, int port)
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{
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__ar8216_init_port(priv, port, true, true);
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}
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static void
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ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
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{
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@ -1753,6 +1840,36 @@ static const struct ar8xxx_chip ar8216_chip = {
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.mib_func = AR8216_REG_MIB_FUNC
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};
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static const struct ar8xxx_chip ar8229_chip = {
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.caps = AR8XXX_CAP_MIB_COUNTERS,
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.reg_port_stats_start = 0x20000,
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.reg_port_stats_length = 0x100,
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.reg_arl_ctrl = AR8216_REG_ATU_CTRL,
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.name = "Atheros AR8229",
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.ports = AR8216_NUM_PORTS,
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.vlans = AR8216_NUM_VLANS,
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.swops = &ar8xxx_sw_ops,
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.hw_init = ar8229_hw_init,
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.init_globals = ar8229_init_globals,
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.init_port = ar8229_init_port,
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.setup_port = ar8236_setup_port,
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.read_port_status = ar8216_read_port_status,
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.atu_flush = ar8216_atu_flush,
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.atu_flush_port = ar8216_atu_flush_port,
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.vtu_flush = ar8216_vtu_flush,
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.vtu_load_vlan = ar8216_vtu_load_vlan,
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.set_mirror_regs = ar8216_set_mirror_regs,
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.get_arl_entry = ar8216_get_arl_entry,
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.sw_hw_apply = ar8xxx_sw_hw_apply,
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.num_mibs = ARRAY_SIZE(ar8236_mibs),
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.mib_decs = ar8236_mibs,
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.mib_func = AR8216_REG_MIB_FUNC
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};
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static const struct ar8xxx_chip ar8236_chip = {
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.caps = AR8XXX_CAP_MIB_COUNTERS,
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@ -2336,6 +2453,9 @@ static struct phy_driver ar8xxx_phy_driver[] = {
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static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
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{
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.compatible = "qca,ar8229",
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.data = &ar8229_chip,
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}, {
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.compatible = "qca,ar8236",
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.data = &ar8236_chip,
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}, {
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@ -52,6 +52,8 @@
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#define AR8216_REG_FLOOD_MASK 0x002C
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#define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
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#define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
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#define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
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#define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
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#define AR8236_FM_CPU_BROADCAST_EN BIT(26)
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#define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
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@ -127,6 +129,12 @@
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#define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
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#define AR8216_ATU_CTRL_AGE_TIME_S 0
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#define AR8236_ATU_CTRL_RES BIT(20)
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#define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
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#define AR8216_REG_TAG_PRIORITY 0x0070
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#define AR8216_REG_SERVICE_TAG 0x0074
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#define AR8216_SERVICE_TAG_M BITS(0, 16)
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#define AR8216_REG_MIB_FUNC 0x0080
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#define AR8216_MIB_TIMER BITS(0, 16)
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@ -142,6 +150,7 @@
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#define AR8216_REG_GLOBAL_CPUPORT 0x0078
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#define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
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#define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
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#define AR8216_GLOBAL_CPUPORT_EN BIT(8)
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#define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
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#define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
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@ -237,6 +246,16 @@
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#define AR8216_STATS_TXDEFER 0x98
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#define AR8216_STATS_TXLATECOL 0x9c
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#define AR8229_REG_OPER_MODE0 0x04
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#define AR8229_OPER_MODE0_MAC_GMII_EN BIT(6)
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#define AR8229_OPER_MODE0_PHY_MII_EN BIT(10)
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#define AR8229_REG_OPER_MODE1 0x08
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#define AR8229_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
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#define AR8229_REG_QM_CTRL 0x3c
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#define AR8229_QM_CTRL_ARP_EN BIT(15)
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#define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
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#define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
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#define AR8236_PORT_VLAN_DEFAULT_ID_S 16
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