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ralink: fix mt7620 ohci 3.10 

the ohci phy was not reset properly

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 42290
lede-17.01
John Crispin 2014-08-25 16:31:01 +00:00
parent 3d00a1109e
commit ca737049d2
1 changed files with 3 additions and 2 deletions
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5
target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
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@ -35,7 +35,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+obj-$(CONFIG_RALINK_USBPHY) += ralink-phy.o +obj-$(CONFIG_RALINK_USBPHY) += ralink-phy.o
--- /dev/null --- /dev/null
+++ b/drivers/usb/phy/ralink-phy.c +++ b/drivers/usb/phy/ralink-phy.c
@@ -0,0 +1,191 @@ @@ -0,0 +1,192 @@
+/* +/*
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org> + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ * + *
@ -66,6 +66,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10) +#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+ +
+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25) +#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20) +#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18) +#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
+ +
@ -145,7 +146,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ +
+static const struct of_device_id ralink_usbphy_dt_match[] = { +static const struct of_device_id ralink_usbphy_dt_match[] = {
+ { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) }, + { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
+ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) MT7620_CLKCFG1_UPHY0_CLK_EN }, + { .compatible = "ralink,mt7620a-usbphy", .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | MT7620_CLKCFG1_UPHY0_CLK_EN) },
+ {}, + {},
+}; +};
+MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match); +MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match);