mirror of https://github.com/hak5/openwrt.git
parent
82e244fb28
commit
c0411f877f
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@ -21,7 +21,21 @@
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static void cpmac_dump_regs(struct net_device *dev)
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{
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int i;
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@@ -1122,12 +1129,39 @@ static int __devinit cpmac_probe(struct
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@@ -1111,9 +1118,13 @@ static int __devinit cpmac_probe(struct
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struct cpmac_priv *priv;
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struct net_device *dev;
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struct plat_cpmac_data *pdata;
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+ void __iomem *mii_reg;
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+ u32 tmp;
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+ unsigned external_mii = 0;
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pdata = pdev->dev.platform_data;
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+detect_again:
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for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
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if (!(pdata->phy_mask & (1 << phy_id)))
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continue;
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@@ -1122,12 +1133,43 @@ static int __devinit cpmac_probe(struct
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strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
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break;
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}
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@ -30,22 +44,26 @@
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- dev_err(&pdev->dev, "no PHY present\n");
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- return -ENODEV;
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+
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+ if (phy_id < PHY_MAX_ADDR)
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+ if (phy_id < PHY_MAX_ADDR && !external_mii)
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+ goto dev_alloc;
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+
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+ dev_info(&pdev->dev, "trying external MII\n");
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+ /* Now disable EPHY and enable MII */
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+ dev_info(&pdev->dev, "trying external MII\n");
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+ ar7_device_disable(AR7_RESET_BIT_EPHY);
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+ *(unsigned long*) ioremap(0x08611A08, 4) |= 0x00000001;
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+
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+ for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
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+ if (!(pdata->phy_mask & (1 << phy_id)))
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+ continue;
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+ if (!cpmac_mii->phy_map[phy_id])
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+ continue;
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+ strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
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+ break;
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+ }
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+ mii_reg = ioremap(AR7_REGS_MII, 4);
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+ if (!mii_reg) {
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+ dev_err(&pdev->dev, "failed to iorenamp MII_SEL\n");
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+ return -ENOMEM;
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}
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+ tmp = readl(mii_reg);
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+ tmp |= 1;
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+ writel(tmp, mii_reg);
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+ external_mii++;
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+
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+ if (external_mii == 1)
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+ goto detect_again;
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+
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+ if (phy_id < PHY_MAX_ADDR)
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+ goto dev_alloc;
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@ -56,8 +74,8 @@
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+ if (rc && rc != -ENODEV) {
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+ dev_err(&pdev->dev, "unable to register fixed PHY\n");
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+ return rc;
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}
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+ }
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+
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+ strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
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+ phy_id = pdev->id;
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+
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@ -65,3 +83,13 @@
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dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
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if (!dev) {
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--- a/arch/mips/include/asm/mach-ar7/ar7.h
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+++ b/arch/mips/include/asm/mach-ar7/ar7.h
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@@ -41,6 +41,7 @@
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#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
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#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
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#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
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+#define AR7_REGS_MII (AR7_REGS_BASE + 0x1a08)
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#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
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#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
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#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
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