diff --git a/openwrt/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch b/openwrt/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch
index ade90a05a5..a37c5db711 100644
--- a/openwrt/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch
+++ b/openwrt/target/linux/linux-2.6/patches/brcm/001-bcm947xx.patch
@@ -2204,8 +2204,8 @@ diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm
 +
 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c	2005-12-15 20:09:46.562233250 +0100
-@@ -0,0 +1,529 @@
++++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c	2005-12-15 23:50:31.846688500 +0100
+@@ -0,0 +1,531 @@
 +/*
 + * Low-Level PCI and SB support for BCM47xx
 + *
@@ -2406,12 +2406,14 @@ diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm9
 +			n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
 +			if (off == OFFSETOF(pci_config_regs, base[0]))
 +				cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
++#if 0
 +			else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
 +				cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
 +			else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
 +				cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
 +			else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
 +				cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
++#endif
 +		}
 +		sb_setcoreidx(sbh, coreidx);
 +		return 0;
@@ -2694,9 +2696,9 @@ diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm9
 +		cfg->sub_class = subclass;
 +		cfg->base_class = class;
 +		cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
-+		cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
-+		cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
-+		cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
++		cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
++		cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
++		cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
 +		cfg->base[4] = 0;
 +		cfg->base[5] = 0;
 +		if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)