mirror of https://github.com/hak5/openwrt.git
ralink: correct handle hardware rx 2bytes offset
Signed-off-by: michael lee <igvtee@gmail.com> SVN-Revision: 44045lede-17.01
parent
03ea0cf6f1
commit
b3ca42ec8f
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@ -41,9 +41,8 @@
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#include "ralink_ethtool.h"
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#define MAX_RX_LENGTH 1536
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#define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
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#define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
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ETH_FCS_LEN)
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#define FE_RX_HLEN (NET_SKB_PAD + VLAN_ETH_HLEN + VLAN_HLEN + \
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+ NET_IP_ALIGN + ETH_FCS_LEN)
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#define DMA_DUMMY_DESC 0xffffffff
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#define FE_DEFAULT_MSG_ENABLE \
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(NETIF_MSG_DRV | \
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@ -239,7 +238,7 @@ static void fe_clean_rx(struct fe_priv *priv)
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static int fe_alloc_rx(struct fe_priv *priv)
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{
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struct net_device *netdev = priv->netdev;
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int i;
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int i, pad;
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priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
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GFP_KERNEL);
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@ -259,9 +258,13 @@ static int fe_alloc_rx(struct fe_priv *priv)
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if (!priv->rx_dma)
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goto no_rx_mem;
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if (priv->flags & FE_FLAG_RX_2B_OFFSET)
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pad = 0;
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else
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pad = NET_IP_ALIGN;
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for (i = 0; i < NUM_DMA_DESC; i++) {
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dma_addr_t dma_addr = dma_map_single(&netdev->dev,
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priv->rx_data[i] + FE_RX_OFFSET,
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priv->rx_data[i] + NET_SKB_PAD + pad,
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priv->rx_buf_size,
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DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
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@ -752,7 +755,7 @@ static int fe_poll_rx(struct napi_struct *napi, int budget,
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struct sk_buff *skb;
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u8 *data, *new_data;
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struct fe_rx_dma *rxd, trxd;
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int done = 0;
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int done = 0, pad;
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bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
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if (netdev->features & NETIF_F_RXCSUM)
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@ -760,6 +763,10 @@ static int fe_poll_rx(struct napi_struct *napi, int budget,
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else
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checksum_bit = 0;
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if (priv->flags & FE_FLAG_RX_2B_OFFSET)
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pad = 0;
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else
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pad = NET_IP_ALIGN;
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while (done < budget) {
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unsigned int pktlen;
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dma_addr_t dma_addr;
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@ -778,7 +785,7 @@ static int fe_poll_rx(struct napi_struct *napi, int budget,
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goto release_desc;
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}
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dma_addr = dma_map_single(&netdev->dev,
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new_data + FE_RX_OFFSET,
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new_data + NET_SKB_PAD + pad,
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priv->rx_buf_size,
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DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
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@ -792,7 +799,7 @@ static int fe_poll_rx(struct napi_struct *napi, int budget,
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put_page(virt_to_head_page(new_data));
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goto release_desc;
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}
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skb_reserve(skb, FE_RX_OFFSET);
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skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
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dma_unmap_single(&netdev->dev, trxd.rxd1,
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priv->rx_buf_size, DMA_FROM_DEVICE);
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@ -1115,6 +1122,8 @@ static int fe_open(struct net_device *dev)
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napi_enable(&priv->rx_napi);
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val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
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if (priv->flags & FE_FLAG_RX_2B_OFFSET)
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val |= FE_RX_2B_OFFSET;
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val |= priv->soc->pdma_glo_cfg;
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fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
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@ -289,6 +289,7 @@ enum fe_work_flag {
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#define FE_PST_DTX_IDX1 BIT(1)
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#define FE_PST_DTX_IDX0 BIT(0)
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#define FE_RX_2B_OFFSET BIT(31)
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#define FE_TX_WB_DDONE BIT(6)
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#define FE_RX_DMA_BUSY BIT(3)
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#define FE_TX_DMA_BUSY BIT(1)
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@ -401,6 +402,9 @@ struct fe_soc_data
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#define FE_FLAG_PADDING_64B BIT(0)
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#define FE_FLAG_PADDING_BUG BIT(1)
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#define FE_FLAG_JUMBO_FRAME BIT(2)
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#define FE_FLAG_RX_2B_OFFSET BIT(3)
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#define FE_FLAG_RX_SG_DMA BIT(4)
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#define FE_FLAG_RX_VLAN_CTAG BIT(5)
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#define FE_STAT_REG_DECLARE \
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_FE(tx_bytes) \
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@ -28,7 +28,6 @@
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#define MT7620A_CDMA_CSG_CFG 0x400
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#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
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#define MT7621_DMA_VID 0xa8
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#define MT7620A_DMA_2B_OFFSET BIT(31)
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#define MT7620A_RESET_FE BIT(21)
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#define MT7621_RESET_FE BIT(6)
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#define MT7620A_RESET_ESW BIT(23)
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@ -179,7 +178,7 @@ static void mt7620_init_data(struct fe_soc_data *data,
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{
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struct fe_priv *priv = netdev_priv(netdev);
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priv->flags = FE_FLAG_PADDING_64B;
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priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET;
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netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
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NETIF_F_HW_VLAN_CTAG_TX;
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@ -193,7 +192,7 @@ static void mt7621_init_data(struct fe_soc_data *data,
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{
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struct fe_priv *priv = netdev_priv(netdev);
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priv->flags = FE_FLAG_PADDING_64B;
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priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET;
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netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
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}
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@ -220,7 +219,7 @@ static struct fe_soc_data mt7620_data = {
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.switch_config = mt7620_gsw_config,
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.port_init = mt7620_port_init,
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.reg_table = mt7620_reg_table,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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.checksum_bit = MT7620_L4_VALID,
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@ -242,7 +241,7 @@ static struct fe_soc_data mt7621_data = {
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.switch_init = mt7620_gsw_probe,
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.switch_config = mt7621_gsw_config,
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.reg_table = mt7621_reg_table,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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.checksum_bit = MT7621_L4_VALID,
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