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uboot-lantiq: reorder and rework patches 

use:
  - 00nn for u-boot patches
  - 01nn for new boards

While doing the rework, the board definitions for the easy50712 and
easy80920 were moved to distinct board definitions patches.

Signed-off-by: Mathias Kresin <dev@kresin.me>
lede-17.01
Mathias Kresin 2016-05-21 12:13:36 +02:00 committed by John Crispin
parent 74b1687be3
commit b3795d0c93
26 changed files with 706 additions and 814 deletions
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662
package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch
View File

@ -5019,491 +5019,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
board_early_init_f,
timer_init,
env_init, /* initialize environment */
--- /dev/null
+++ b/board/lantiq/easy50712/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/lantiq/easy50712/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/lantiq/easy50712/ddr_settings.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x13c
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0xd00
+#define MC_DC22_VALUE 0xd0d
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x62
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- /dev/null
+++ b/board/lantiq/easy50712/easy50712.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+static void gpio_init(void)
+{
+ /* SPI/CS output (low-active) for serial flash */
+ gpio_direction_output(22, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+
+ /* enable CLK_OUT2 for external switch */
+ gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Lantiq ADM6996I switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device adm6996i_dev = {
+ .name = "adm6996i",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ /* Deactivate HRST line to release reset of ADM6996I switch */
+ ltq_reset_once(LTQ_RESET_HARD, 200000);
+
+ /* ADM6996I needs some time to come out of reset */
+ __udelay(50000);
+
+ return switch_device_register(&adm6996i_dev);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ switch (cs) {
+ case 2:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 2:
+ gpio_set_value(22, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 2:
+ gpio_set_value(22, 1);
+ break;
+ default:
+ break;
+ }
+}
--- /dev/null
+++ b/board/lantiq/easy80920/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/lantiq/easy80920/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/lantiq/easy80920/ddr_settings.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x101
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000300
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x0
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141b42
+#define MC_CCR42_VALUE 0x141b42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x0
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- /dev/null
+++ b/board/lantiq/easy80920/easy80920.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 0
+#elif defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+static void gpio_init(void)
+{
+ /* SPI CS 0.4 to serial flash */
+ gpio_direction_output(10, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* GPIO 3.0 as input for NAND Ready Busy */
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
+ /* GPIO 3.1 as output for NAND Read */
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ ltq_gphy_phy11g_a1x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ if (cs == 4)
+ return 1;
+
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 1);
+ break;
+ default:
+ break;
+ }
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -502,10 +502,17 @@ Active mips mips32 au1x0
Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
+Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -12,6 +12,7 @@ LIB := $(obj)libdma.o
@ -8782,183 +8297,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+
+ return ret;
+}
--- /dev/null
+++ b/include/configs/easy50712.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "EASY50712"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Lantiq EASY50712 Danube Reference Board"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
+
+#define CONFIG_LTQ_SPL_COMP_LZO
+#define CONFIG_LTQ_SPL_CONSOLE
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_ADM6996I
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 2
+#define CONFIG_ENV_SPI_MAX_HZ 20000000
+#define CONFIG_ENV_SPI_MODE 0
+
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (128 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Commands */
+#define CONFIG_CMD_PING
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR
+
+#endif /* __CONFIG_H */
--- /dev/null
+++ b/include/configs/easy80920.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "EASY80920"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Lantiq EASY80920 VRX200 Family Board"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 4
+#define CONFIG_SPL_SPI_MAX_HZ 25000000
+#define CONFIG_SPL_SPI_MODE 0
+
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
+
+#define CONFIG_LTQ_SPL_COMP_LZO
+#define CONFIG_LTQ_SPL_CONSOLE
+
+#define CONFIG_SYS_DRAM_PROBE
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
+
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (384 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_SFSPL)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Commands */
+#define CONFIG_CMD_PING
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+
+#define CONFIG_ENV_UPDATE_UBOOT_SF \
+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ CONFIG_ENV_UPDATE_UBOOT_SF
+
+#endif /* __CONFIG_H */
--- a/include/phy.h
+++ b/include/phy.h
@@ -214,6 +214,7 @@ int phy_atheros_init(void);

0
package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch → package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-add-default-openwrt-config.patch
View File

61
package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch
View File

@ -1,61 +0,0 @@
From 6fa1c350fa19a054371eccef84e4885cfdd6a2d7 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 19 Aug 2013 18:11:31 +0200
Subject: MIPS: lantiq: easy80920: add support for NAND SPL
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/boards.cfg
+++ b/boards.cfg
@@ -509,6 +509,7 @@ Active mips mips32 incai
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/include/configs/easy80920.h
+++ b/include/configs/easy80920.h
@@ -31,6 +31,14 @@
#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
+#define CONFIG_SYS_NAND_PAGE_COUNT 128
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
+
#define CONFIG_LTQ_SPL_COMP_LZO
#define CONFIG_LTQ_SPL_CONSOLE
@@ -57,6 +65,11 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OFFSET (192 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NANDSPL)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
@@ -84,9 +97,13 @@
#define CONFIG_ENV_UPDATE_UBOOT_SF \
"update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
+#define CONFIG_ENV_UPDATE_UBOOT_NAND \
+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_ENV_LANTIQ_DEFAULTS \
CONFIG_ENV_UPDATE_UBOOT_NOR \
- CONFIG_ENV_UPDATE_UBOOT_SF
+ CONFIG_ENV_UPDATE_UBOOT_SF \
+ CONFIG_ENV_UPDATE_UBOOT_NAND
#endif /* __CONFIG_H */

9
package/boot/uboot-lantiq/patches/0041-lzma-fixup.patch → package/boot/uboot-lantiq/patches/0023-lzma-fixup.patch
View File

@ -16,11 +16,9 @@ CC: Luka Perkov <luka@openwrt.org>
lib/lzma/LzmaTools.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/lib/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c
index 0aec2f9..90d31cd 100644
--- a/lib/lzma/LzmaTools.c
+++ b/lib/lzma/LzmaTools.c
@@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
@@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned c
return SZ_ERROR_OUTPUT_EOF;
/* Decompress */
@ -29,7 +27,7 @@ index 0aec2f9..90d31cd 100644
WATCHDOG_RESET();
@@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
@@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned c
inStream + LZMA_DATA_OFFSET, &compressedSize,
inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);
*uncompressedSize = outProcessed;
@ -39,6 +37,3 @@ index 0aec2f9..90d31cd 100644
if (res != SZ_OK) {
return res;
}
--
1.8.3.2

26
package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch
View File

@ -1,26 +0,0 @@
From ac6896098d9dd62a248340e6a090574399e1fd87 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 19 Aug 2013 18:46:47 +0200
Subject: MIPS: lantiq: easy50712: add openwrt-lantiq-common.h
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/include/configs/easy50712.h
+++ b/include/configs/easy50712.h
@@ -62,13 +62,13 @@
#define CONFIG_CONSOLE_ASC 1
#define CONFIG_CONSOLE_DEV "ttyLTQ1"
-/* Commands */
-#define CONFIG_CMD_PING
-
/* Pull in default board configs for Lantiq XWAY Danube */
#include <asm/lantiq/config.h>
#include <asm/arch/config.h>
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
#define CONFIG_ENV_UPDATE_UBOOT_NOR \
"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"

0
package/boot/uboot-lantiq/patches/0041-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch → package/boot/uboot-lantiq/patches/0024-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch
View File

26
package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch
View File

@ -1,26 +0,0 @@
From 7afbe4633773905ef94a8404510fb5a459926000 Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Date: Mon, 19 Aug 2013 18:11:57 +0200
Subject: MIPS: lantiq: easy80920: add openwrt-lantiq-common.h
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
--- a/include/configs/easy80920.h
+++ b/include/configs/easy80920.h
@@ -84,13 +84,13 @@
#define CONFIG_CONSOLE_ASC 1
#define CONFIG_CONSOLE_DEV "ttyLTQ1"
-/* Commands */
-#define CONFIG_CMD_PING
-
/* Pull in default board configs for Lantiq XWAY VRX200 */
#include <asm/lantiq/config.h>
#include <asm/arch/config.h>
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
#define CONFIG_ENV_UPDATE_UBOOT_NOR \
"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"

4
package/boot/uboot-lantiq/patches/0042-arx100-cgu-fixes.patch → package/boot/uboot-lantiq/patches/0025-arx100-cgu-fixes.patch
View File

@ -95,8 +95,8 @@ On Tue, 2015-01-20 at 00:39 +0100, Ben Mulvihill wrote:
Some of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1
out. A patch along these lines should fix it:
--- a/arch/mips/cpu/mips32/arx100/cgu.c 2015-01-20 11:57:22.000000000 +0100
+++ b/arch/mips/cpu/mips32/arx100/cgu.c 2015-01-20 12:00:15.000000000 +0100
--- a/arch/mips/cpu/mips32/arx100/cgu.c
+++ b/arch/mips/cpu/mips32/arx100/cgu.c
@@ -10,12 +10,17 @@
#include <asm/lantiq/clk.h>
#include <asm/lantiq/io.h>

20
package/boot/uboot-lantiq/patches/0045-no_extern_inline.patch → package/boot/uboot-lantiq/patches/0026-no_extern_inline.patch
View File

@ -13,11 +13,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
arch/mips/include/asm/system.h | 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 3fa37f5..a7ab087 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -117,7 +117,7 @@ static inline void set_io_port_base(unsigned long base)
@@ -118,7 +118,7 @@ static inline void set_io_port_base(unsi
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/MIPS mapping
*/
@ -26,7 +24,7 @@ index 3fa37f5..a7ab087 100644
{
#ifndef CONFIG_64BIT
return CPHYSADDR(address);
@@ -126,7 +126,7 @@ extern inline phys_addr_t virt_to_phys(volatile void * address)
@@ -127,7 +127,7 @@ extern inline phys_addr_t virt_to_phys(v
#endif
}
@ -35,7 +33,7 @@ index 3fa37f5..a7ab087 100644
{
#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
@@ -138,7 +138,7 @@ extern inline void * phys_to_virt(unsigned long address)
@@ -139,7 +139,7 @@ extern inline void * phys_to_virt(unsign
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
@ -44,7 +42,7 @@ index 3fa37f5..a7ab087 100644
{
#ifndef CONFIG_64BIT
return CPHYSADDR(address);
@@ -147,7 +147,7 @@ extern inline unsigned long virt_to_bus(volatile void * address)
@@ -148,7 +148,7 @@ extern inline unsigned long virt_to_bus(
#endif
}
@ -53,7 +51,7 @@ index 3fa37f5..a7ab087 100644
{
#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
@@ -165,12 +165,12 @@ extern unsigned long isa_slot_offset;
@@ -166,12 +166,12 @@ extern unsigned long isa_slot_offset;
extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
#if 0
@ -68,11 +66,9 @@ index 3fa37f5..a7ab087 100644
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index 7a28952..d56f73b 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -22,7 +22,7 @@
@@ -23,7 +23,7 @@
#include <linux/kernel.h>
#endif
@ -81,7 +77,7 @@ index 7a28952..d56f73b 100644
__sti(void)
{
__asm__ __volatile__(
@@ -46,7 +46,7 @@ __sti(void)
@@ -47,7 +47,7 @@ __sti(void)
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
@ -90,7 +86,7 @@ index 7a28952..d56f73b 100644
__cli(void)
{
__asm__ __volatile__(
@@ -207,7 +207,7 @@ do { \
@@ -208,7 +208,7 @@ do { \
* For 32 and 64 bit operands we can take advantage of ll and sc.
* FIXME: This doesn't work for R3000 machines.
*/

8
package/boot/uboot-lantiq/patches/0046-no_weak_alias.patch → package/boot/uboot-lantiq/patches/0027-no_weak_alias.patch
View File

@ -12,11 +12,9 @@ Acked-by: Simon Glass <sjg@chromium.org>
common/main.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/common/main.c b/common/main.c
index 32618f1..2979fbe 100644
--- a/common/main.c
+++ b/common/main.c
@@ -17,8 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
@@ -27,8 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
@ -24,5 +22,5 @@ index 32618f1..2979fbe 100644
-void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
+__weak void show_boot_progress(int val) {}
static void modem_init(void)
{
#define MAX_DELAY_STOP_STR 32

6
package/boot/uboot-lantiq/patches/0047-add-gcc5-support.patch → package/boot/uboot-lantiq/patches/0028-add-gcc5-support.patch
View File

@ -17,9 +17,6 @@ Signed-off-by: Hans de Goede <hdegoede@redhat.com>
1 file changed, 65 insertions(+)
create mode 100644 include/linux/compiler-gcc5.h
diff --git a/include/linux/compiler-gcc5.h b/include/linux/compiler-gcc5.h
new file mode 100644
index 0000000..c8c5659
--- /dev/null
+++ b/include/linux/compiler-gcc5.h
@@ -0,0 +1,65 @@
@ -88,6 +85,3 @@ index 0000000..c8c5659
+#define __HAVE_BUILTIN_BSWAP64__
+#define __HAVE_BUILTIN_BSWAP16__
+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
--
1.7.10.4

306
package/boot/uboot-lantiq/patches/0100-MIPS-add-board-support-for-Easy-50712.patch Normal file
View File

@ -0,0 +1,306 @@
--- /dev/null
+++ b/board/lantiq/easy50712/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/lantiq/easy50712/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/lantiq/easy50712/ddr_settings.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_DC00_VALUE 0x1B1B
+#define MC_DC01_VALUE 0x0
+#define MC_DC02_VALUE 0x0
+#define MC_DC03_VALUE 0x0
+#define MC_DC04_VALUE 0x0
+#define MC_DC05_VALUE 0x200
+#define MC_DC06_VALUE 0x605
+#define MC_DC07_VALUE 0x303
+#define MC_DC08_VALUE 0x102
+#define MC_DC09_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x13c
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04
+#define MC_DC21_VALUE 0xd00
+#define MC_DC22_VALUE 0xd0d
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x62
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+#define MC_DC46_VALUE 0x0
--- /dev/null
+++ b/board/lantiq/easy50712/easy50712.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <switch.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/reset.h>
+#include <asm/lantiq/chipid.h>
+
+static void gpio_init(void)
+{
+ /* SPI/CS output (low-active) for serial flash */
+ gpio_direction_output(22, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+
+ /* enable CLK_OUT2 for external switch */
+ gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* MAC0: Lantiq ADM6996I switch */
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t *bis)
+{
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+static struct switch_device adm6996i_dev = {
+ .name = "adm6996i",
+ .cpu_port = 5,
+ .port_mask = 0xF,
+};
+
+int board_switch_init(void)
+{
+ /* Deactivate HRST line to release reset of ADM6996I switch */
+ ltq_reset_once(LTQ_RESET_HARD, 200000);
+
+ /* ADM6996I needs some time to come out of reset */
+ __udelay(50000);
+
+ return switch_device_register(&adm6996i_dev);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ switch (cs) {
+ case 2:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 2:
+ gpio_set_value(22, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 2:
+ gpio_set_value(22, 1);
+ break;
+ default:
+ break;
+ }
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -502,6 +502,9 @@ Active mips mips32 au1x0
Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
+Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
--- /dev/null
+++ b/include/configs/easy50712.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "EASY50712"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Lantiq EASY50712 Danube Reference Board"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
+
+#define CONFIG_LTQ_SPL_COMP_LZO
+#define CONFIG_LTQ_SPL_CONSOLE
+
+/* Switch devices */
+#define CONFIG_SWITCH_MULTI
+#define CONFIG_SWITCH_ADM6996I
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 2
+#define CONFIG_ENV_SPI_MAX_HZ 20000000
+#define CONFIG_ENV_SPI_MODE 0
+
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (128 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY Danube */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR
+
+#endif /* __CONFIG_H */

379
package/boot/uboot-lantiq/patches/0101-MIPS-add-board-support-for-Easy-80920.patch Normal file
View File

@ -0,0 +1,379 @@
--- /dev/null
+++ b/board/lantiq/easy80920/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+++ b/board/lantiq/easy80920/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
--- /dev/null
+++ b/board/lantiq/easy80920/ddr_settings.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define MC_CCR00_VALUE 0x101
+#define MC_CCR01_VALUE 0x1000100
+#define MC_CCR02_VALUE 0x1010000
+#define MC_CCR03_VALUE 0x101
+#define MC_CCR04_VALUE 0x1000000
+#define MC_CCR05_VALUE 0x1000101
+#define MC_CCR06_VALUE 0x1000100
+#define MC_CCR07_VALUE 0x1010000
+#define MC_CCR08_VALUE 0x1000101
+#define MC_CCR09_VALUE 0x0
+#define MC_CCR10_VALUE 0x2000100
+#define MC_CCR11_VALUE 0x2000300
+#define MC_CCR12_VALUE 0x30000
+#define MC_CCR13_VALUE 0x202
+#define MC_CCR14_VALUE 0x7080A0F
+#define MC_CCR15_VALUE 0x2040F
+#define MC_CCR16_VALUE 0x40000
+#define MC_CCR17_VALUE 0x70102
+#define MC_CCR18_VALUE 0x4020002
+#define MC_CCR19_VALUE 0x30302
+#define MC_CCR20_VALUE 0x8000700
+#define MC_CCR21_VALUE 0x40F020A
+#define MC_CCR22_VALUE 0x0
+#define MC_CCR23_VALUE 0xC020000
+#define MC_CCR24_VALUE 0x4401B04
+#define MC_CCR25_VALUE 0x0
+#define MC_CCR26_VALUE 0x0
+#define MC_CCR27_VALUE 0x6420000
+#define MC_CCR28_VALUE 0x0
+#define MC_CCR29_VALUE 0x0
+#define MC_CCR30_VALUE 0x798
+#define MC_CCR31_VALUE 0x0
+#define MC_CCR32_VALUE 0x0
+#define MC_CCR33_VALUE 0x650000
+#define MC_CCR34_VALUE 0x200C8
+#define MC_CCR35_VALUE 0x1D445D
+#define MC_CCR36_VALUE 0xC8
+#define MC_CCR37_VALUE 0xC351
+#define MC_CCR38_VALUE 0x0
+#define MC_CCR39_VALUE 0x141F04
+#define MC_CCR40_VALUE 0x142704
+#define MC_CCR41_VALUE 0x141b42
+#define MC_CCR42_VALUE 0x141b42
+#define MC_CCR43_VALUE 0x566504
+#define MC_CCR44_VALUE 0x566504
+#define MC_CCR45_VALUE 0x565F17
+#define MC_CCR46_VALUE 0x565F17
+#define MC_CCR47_VALUE 0x0
+#define MC_CCR48_VALUE 0x0
+#define MC_CCR49_VALUE 0x0
+#define MC_CCR50_VALUE 0x0
+#define MC_CCR51_VALUE 0x0
+#define MC_CCR52_VALUE 0x133
+#define MC_CCR53_VALUE 0xF3014B27
+#define MC_CCR54_VALUE 0xF3014B27
+#define MC_CCR55_VALUE 0xF3014B27
+#define MC_CCR56_VALUE 0xF3014B27
+#define MC_CCR57_VALUE 0x7800301
+#define MC_CCR58_VALUE 0x7800301
+#define MC_CCR59_VALUE 0x7800301
+#define MC_CCR60_VALUE 0x7800301
+#define MC_CCR61_VALUE 0x4
--- /dev/null
+++ b/board/lantiq/easy80920/easy80920.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/lantiq/eth.h>
+#include <asm/lantiq/chipid.h>
+#include <asm/lantiq/cpu.h>
+#include <asm/arch/gphy.h>
+
+#if defined(CONFIG_SPL_BUILD)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 0
+#elif defined(CONFIG_SYS_BOOT_RAM)
+#define do_gpio_init 1
+#define do_pll_init 0
+#define do_dcdc_init 1
+#elif defined(CONFIG_SYS_BOOT_NOR)
+#define do_gpio_init 1
+#define do_pll_init 1
+#define do_dcdc_init 1
+#else
+#define do_gpio_init 0
+#define do_pll_init 0
+#define do_dcdc_init 1
+#endif
+
+static void gpio_init(void)
+{
+ /* SPI CS 0.4 to serial flash */
+ gpio_direction_output(10, 1);
+
+ /* EBU.FL_CS1 as output for NAND CE */
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A23 as output for NAND CLE */
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* EBU.FL_A24 as output for NAND ALE */
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+ /* GPIO 3.0 as input for NAND Ready Busy */
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
+ /* GPIO 3.1 as output for NAND Read */
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
+}
+
+int board_early_init_f(void)
+{
+ if (do_gpio_init)
+ gpio_init();
+
+ if (do_pll_init)
+ ltq_pll_init();
+
+ if (do_dcdc_init)
+ ltq_dcdc_init(0x7F);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_BOARD_NAME "\n");
+ ltq_chip_print_info();
+
+ return 0;
+}
+
+static const struct ltq_eth_port_config eth_port_config[] = {
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC3: unused */
+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
+};
+
+static const struct ltq_eth_board_config eth_board_config = {
+ .ports = eth_port_config,
+ .num_ports = ARRAY_SIZE(eth_port_config),
+};
+
+int board_eth_init(bd_t * bis)
+{
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
+ const ulong fw_addr = 0x80FF0000;
+
+ ltq_gphy_phy11g_a1x_load(fw_addr);
+
+ ltq_cgu_gphy_clk_src(clk);
+
+ ltq_rcu_gphy_boot(0, fw_addr);
+ ltq_rcu_gphy_boot(1, fw_addr);
+
+ return ltq_eth_initialize(&eth_board_config);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus)
+ return 0;
+
+ if (cs == 4)
+ return 1;
+
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 4:
+ gpio_set_value(10, 1);
+ break;
+ default:
+ break;
+ }
+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -509,6 +509,11 @@ Active mips mips32 incai
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
--- /dev/null
+++ b/include/configs/easy80920.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE "EASY80920"
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
+#define CONFIG_BOARD_NAME "Lantiq EASY80920 VRX200 Family Board"
+
+/* Configure SoC */
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
+
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
+
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
+
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
+
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
+
+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 4
+#define CONFIG_SPL_SPI_MAX_HZ 25000000
+#define CONFIG_SPL_SPI_MODE 0
+
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
+
+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
+#define CONFIG_SYS_NAND_PAGE_COUNT 128
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
+
+#define CONFIG_LTQ_SPL_COMP_LZO
+#define CONFIG_LTQ_SPL_CONSOLE
+
+#define CONFIG_SYS_DRAM_PROBE
+
+/* Environment */
+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
+
+#if defined(CONFIG_SYS_BOOT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (384 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_SFSPL)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (192 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#elif defined(CONFIG_SYS_BOOT_NANDSPL)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/* Console */
+#define CONFIG_LTQ_ADVANCED_CONSOLE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONSOLE_ASC 1
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
+
+/* Pull in default board configs for Lantiq XWAY VRX200 */
+#include <asm/lantiq/config.h>
+#include <asm/arch/config.h>
+
+/* Pull in default OpenWrt configs for Lantiq SoC */
+#include "openwrt-lantiq-common.h"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
+
+#define CONFIG_ENV_UPDATE_UBOOT_SF \
+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
+
+#define CONFIG_ENV_UPDATE_UBOOT_NAND \
+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_ENV_LANTIQ_DEFAULTS \
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
+ CONFIG_ENV_UPDATE_UBOOT_SF \
+ CONFIG_ENV_UPDATE_UBOOT_NAND
+
+#endif /* __CONFIG_H */

0
package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch → package/boot/uboot-lantiq/patches/0102-MIPS-add-board-support-for-Arcadyan-ARV4519PW.patch
View File

0
package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch → package/boot/uboot-lantiq/patches/0103-MIPS-add-board-support-for-Arcadyan-ARV7518PW.patch
View File

0
package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch → package/boot/uboot-lantiq/patches/0104-MIPS-add-board-support-for-AudioCodes-MP-252.patch
View File

0
package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch → package/boot/uboot-lantiq/patches/0105-MIPS-add-board-support-for-AVM-FritzBox-3370.patch
View File

0
package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch → package/boot/uboot-lantiq/patches/0106-MIPS-add-board-support-for-Gigaset-SX76X.patch
View File

0
package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch → package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch
View File

2
package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch → package/boot/uboot-lantiq/patches/0108-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch
View File

@ -160,7 +160,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -518,6 +518,9 @@ Active mips mips32 danub
@@ -508,6 +508,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>

2
package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch → package/boot/uboot-lantiq/patches/0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch
View File

@ -161,7 +161,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -521,6 +521,9 @@ Active mips mips32 danub
@@ -511,6 +511,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN -
Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR -
Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM -

2
package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch → package/boot/uboot-lantiq/patches/0110-MIPS-add-board-support-for-Arcadyan-ARV7510PW.patch
View File

@ -179,7 +179,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -515,6 +515,9 @@ Active mips mips32 au1x0
@@ -505,6 +505,9 @@ Active mips mips32 au1x0
Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>

2
package/boot/uboot-lantiq/patches/0041-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch → package/boot/uboot-lantiq/patches/0111-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch
View File

@ -156,7 +156,7 @@
+#########################################################################
--- a/boards.cfg
+++ b/boards.cfg
@@ -518,6 +518,9 @@ Active mips mips32 danub
@@ -508,6 +508,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>

0
package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch → package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch
View File

3
package/boot/uboot-lantiq/patches/0044-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch → package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch
View File

@ -156,7 +156,7 @@
+#define MC_DC46_VALUE 0x0
--- a/boards.cfg
+++ b/boards.cfg
@@ -553,6 +553,9 @@ Active mips mips32 danube arcadyan arv752dpw
@@ -520,6 +520,9 @@ Active mips mips32 danub
Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN -
Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR -
Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM -
@ -237,4 +237,3 @@
+ "kernel_addr=0xB0040000\0"
+
+#endif /* __CONFIG_H */