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Revert "ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x" 

The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some
boards. These boards depend on the preset values of u-boot which may
differ.

This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

SVN-Revision: 49071
lede-17.01
John Crispin 2016-03-23 12:52:17 +00:00
parent 26d18d4e07
commit b269a3520d
17 changed files with 19 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
View File

@ -830,9 +830,7 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
iounmap(base);
}
void __init ath79_setup_qca955x_eth_cfg(u32 mask,
unsigned int rxd, unsigned int rxdv,
unsigned int txd, unsigned int txe)
void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{
void __iomem *base;
u32 t, m;
@ -847,10 +845,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask,
QCA955X_ETH_CFG_RMII_GE0 |
QCA955X_ETH_CFG_MII_CNTL_SPEED |
QCA955X_ETH_CFG_RMII_GE0_MASTER;
m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
@ -858,10 +852,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask,
t &= ~m;
t |= mask;
t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);

3
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
View File

@ -48,7 +48,6 @@ void ath79_register_mdio(unsigned int id, u32 phy_mask);
void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
void ath79_setup_ar934x_eth_cfg(u32 mask);
void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
void ath79_setup_qca955x_eth_cfg(u32 mask, unsigned int rxd, unsigned int rxdv,
unsigned int txd, unsigned int txe);
void ath79_setup_qca955x_eth_cfg(u32 mask);
#endif /* _ATH79_DEV_ETH_H */

2
target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
View File

@ -211,7 +211,7 @@ static void __init common_setup(bool pcie_slot)
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;

2
target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
View File

@ -149,7 +149,7 @@ static void __init epg5000_setup(void)
ath79_register_usb();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c
View File

@ -148,7 +148,7 @@ static void __init esr1750_setup(void)
ath79_register_usb();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c
View File

@ -170,7 +170,7 @@ static void __init esr900_setup(void)
ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c
View File

@ -152,7 +152,7 @@ static void __init f9k1115v2_setup(void)
mdiobus_register_board_info(f9k1115v2_mdio0_info,
ARRAY_SIZE(f9k1115v2_mdio0_info));
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_init_mac(ath79_eth0_data.mac_addr,
art + F9K1115V2_WAN_MAC_OFFSET, 0);

5
target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c
View File

@ -253,8 +253,9 @@ static void __init mr18_setup(void)
res = mr18_extract_sgmii_res_cal();
if (res >= 0) {
/* Setup SoC Eth Config */
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0,
0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN |
(3 << QCA955X_ETH_CFG_RXD_DELAY_SHIFT) |
(3 << QCA955X_ETH_CFG_RDV_DELAY_SHIFT));
/* MDIO Interface */
ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c
View File

@ -287,7 +287,7 @@ static void __init nbg6716_common_setup(u32 leds_num, struct gpio_led* leds,
ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c
View File

@ -203,7 +203,7 @@ static void __init rb922gs_setup(void)
rb922gs_nand_init();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/files/arch/mips/ath79/mach-tew-823dru.c
View File

@ -155,7 +155,7 @@ static void __init tew_823dru_setup(void)
ARRAY_SIZE(tew_823dru_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;

2
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c
View File

@ -183,7 +183,7 @@ static void __init tl_wr1043nd_v2_setup(void)
ARRAY_SIZE(wr1043nd_v2_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;

2
target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c
View File

@ -152,7 +152,7 @@ static void __init wlr8100_common_setup(void)
ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c
View File

@ -156,7 +156,7 @@ static void __init wpj558_setup(void)
ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;

2
target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c
View File

@ -193,7 +193,7 @@ static void __init wzr_450hp2_setup(void)
ARRAY_SIZE(wzr_450hp2_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;

2
target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch
View File

@ -149,7 +149,7 @@
+
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+ ath79_register_mdio(0, 0x0);

2
target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch
View File

@ -149,7 +149,7 @@
+
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+ ath79_register_mdio(0, 0x0);