mirror of https://github.com/hak5/openwrt.git
detect ar7 at runtime in set_except_vector and remove useless volatile
SVN-Revision: 8824lede-17.01
parent
0d56d48d9a
commit
aa1144ff37
|
@ -26,28 +26,32 @@ diff -urN linux-2.6.22/arch/mips/Kconfig linux-2.6.22.new/arch/mips/Kconfig
|
||||||
diff -urN linux-2.6.22/arch/mips/kernel/traps.c linux-2.6.22.new/arch/mips/kernel/traps.c
|
diff -urN linux-2.6.22/arch/mips/kernel/traps.c linux-2.6.22.new/arch/mips/kernel/traps.c
|
||||||
--- linux-2.6.22/arch/mips/kernel/traps.c 2007-07-09 01:32:17.000000000 +0200
|
--- linux-2.6.22/arch/mips/kernel/traps.c 2007-07-09 01:32:17.000000000 +0200
|
||||||
+++ linux-2.6.22.new/arch/mips/kernel/traps.c 2007-07-11 02:32:39.000000000 +0200
|
+++ linux-2.6.22.new/arch/mips/kernel/traps.c 2007-07-11 02:32:39.000000000 +0200
|
||||||
@@ -1075,9 +1075,23 @@ void *set_except_vector(int n, void *addr)
|
@@ -1074,11 +1074,23 @@ void *set_except_vector(int n, void *addr)
|
||||||
|
unsigned long old_handler = exception_handlers[n];
|
||||||
|
|
||||||
exception_handlers[n] = handler;
|
exception_handlers[n] = handler;
|
||||||
if (n == 0 && cpu_has_divec) {
|
- if (n == 0 && cpu_has_divec) {
|
||||||
+#ifdef CONFIG_AR7
|
- *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
|
||||||
+ /* lui k0, 0x0000 */
|
- (0x03ffffff & (handler >> 2));
|
||||||
+ *(volatile u32 *)(ebase + 0x200) =
|
- flush_icache_range(ebase + 0x200, ebase + 0x204);
|
||||||
+ 0x3c1a0000 | (handler >> 16);
|
- }
|
||||||
+ /* ori k0, 0x0000 */
|
+ if (n == 0 && cpu_has_divec)
|
||||||
+ *(volatile u32 *)(ebase + 0x204) =
|
+ if ((handler ^ (ebase + 4)) & 0xfc000000) {
|
||||||
+ 0x375a0000 | (handler & 0xffff);
|
+ /* lui k0, 0x0000 */
|
||||||
+ /* jr k0 */
|
+ *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
|
||||||
+ *(volatile u32 *)(ebase + 0x208) = 0x03400008;
|
+ /* ori k0, 0x0000 */
|
||||||
+ /* nop */
|
+ *(u32 *)(ebase + 0x204) =
|
||||||
+ *(volatile u32 *)(ebase + 0x20C) = 0x00000000;
|
+ 0x375a0000 | (handler & 0xffff);
|
||||||
+ flush_icache_range(ebase + 0x200, ebase + 0x210);
|
+ /* jr k0 */
|
||||||
+#else
|
+ *(u32 *)(ebase + 0x208) = 0x03400008;
|
||||||
*(volatile u32 *)(ebase + 0x200) = 0x08000000 |
|
+ /* nop */
|
||||||
(0x03ffffff & (handler >> 2));
|
+ *(u32 *)(ebase + 0x20C) = 0x00000000;
|
||||||
flush_icache_range(ebase + 0x200, ebase + 0x204);
|
+ flush_icache_range(ebase + 0x200, ebase + 0x210);
|
||||||
+#endif
|
+ } else {
|
||||||
}
|
+ *(volatile u32 *)(ebase + 0x200) =
|
||||||
|
+ 0x08000000 | (0x03ffffff & (handler >> 2));
|
||||||
|
+ flush_icache_range(ebase + 0x200, ebase + 0x204);
|
||||||
|
+ }
|
||||||
return (void *)old_handler;
|
return (void *)old_handler;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue