mirror of https://github.com/hak5/openwrt.git
detect ar7 at runtime in set_except_vector and remove useless volatile
SVN-Revision: 8824lede-17.01
parent
0d56d48d9a
commit
aa1144ff37
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@ -26,28 +26,32 @@ diff -urN linux-2.6.22/arch/mips/Kconfig linux-2.6.22.new/arch/mips/Kconfig
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diff -urN linux-2.6.22/arch/mips/kernel/traps.c linux-2.6.22.new/arch/mips/kernel/traps.c
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diff -urN linux-2.6.22/arch/mips/kernel/traps.c linux-2.6.22.new/arch/mips/kernel/traps.c
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--- linux-2.6.22/arch/mips/kernel/traps.c 2007-07-09 01:32:17.000000000 +0200
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--- linux-2.6.22/arch/mips/kernel/traps.c 2007-07-09 01:32:17.000000000 +0200
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+++ linux-2.6.22.new/arch/mips/kernel/traps.c 2007-07-11 02:32:39.000000000 +0200
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+++ linux-2.6.22.new/arch/mips/kernel/traps.c 2007-07-11 02:32:39.000000000 +0200
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@@ -1075,9 +1075,23 @@ void *set_except_vector(int n, void *addr)
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@@ -1074,11 +1074,23 @@ void *set_except_vector(int n, void *addr)
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unsigned long old_handler = exception_handlers[n];
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exception_handlers[n] = handler;
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exception_handlers[n] = handler;
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if (n == 0 && cpu_has_divec) {
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- if (n == 0 && cpu_has_divec) {
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+#ifdef CONFIG_AR7
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- *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
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- (0x03ffffff & (handler >> 2));
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- flush_icache_range(ebase + 0x200, ebase + 0x204);
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- }
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+ if (n == 0 && cpu_has_divec)
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+ if ((handler ^ (ebase + 4)) & 0xfc000000) {
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+ /* lui k0, 0x0000 */
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+ /* lui k0, 0x0000 */
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+ *(volatile u32 *)(ebase + 0x200) =
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+ *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
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+ 0x3c1a0000 | (handler >> 16);
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+ /* ori k0, 0x0000 */
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+ /* ori k0, 0x0000 */
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+ *(volatile u32 *)(ebase + 0x204) =
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+ *(u32 *)(ebase + 0x204) =
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+ 0x375a0000 | (handler & 0xffff);
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+ 0x375a0000 | (handler & 0xffff);
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+ /* jr k0 */
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+ /* jr k0 */
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+ *(volatile u32 *)(ebase + 0x208) = 0x03400008;
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+ *(u32 *)(ebase + 0x208) = 0x03400008;
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+ /* nop */
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+ /* nop */
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+ *(volatile u32 *)(ebase + 0x20C) = 0x00000000;
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+ *(u32 *)(ebase + 0x20C) = 0x00000000;
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+ flush_icache_range(ebase + 0x200, ebase + 0x210);
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+ flush_icache_range(ebase + 0x200, ebase + 0x210);
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+#else
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+ } else {
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*(volatile u32 *)(ebase + 0x200) = 0x08000000 |
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+ *(volatile u32 *)(ebase + 0x200) =
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(0x03ffffff & (handler >> 2));
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+ 0x08000000 | (0x03ffffff & (handler >> 2));
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flush_icache_range(ebase + 0x200, ebase + 0x204);
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+ flush_icache_range(ebase + 0x200, ebase + 0x204);
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+#endif
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+ }
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}
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return (void *)old_handler;
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return (void *)old_handler;
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}
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}
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