mirror of https://github.com/hak5/openwrt.git
cns3xxx: drop target
This target has not been updated to 5.4 yet, and the only person trying it (Koen) decided to retreat based on the following reasons: - The target is not DT-aware at all - The huge amount of effort required - The SoC itself reached EoL at Cavium for some time now - Upstream removed some important parts as it's also slowly getting EoL over there - The commercial product that used this will fade out shortly - The amount of download for this binary suggest that the target is not that popular Since nobody has picked up the work since then, and this is the last remaining 4.19-only target, finally drop it now. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>master
Adrian Schmutzler
parent
04d3b517dc
commit
a9790dff53
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@ -8,7 +8,7 @@ include $(INCLUDE_DIR)/package.mk
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define KernelPackage/hwmon-gsc
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SUBMENU:=Hardware Monitoring Support
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DEPENDS:=@TARGET_imx6||TARGET_cns3xxx +kmod-hwmon-core +kmod-i2c-core
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DEPENDS:=@TARGET_imx6 +kmod-hwmon-core +kmod-i2c-core
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TITLE:=Driver for the Gateworks System Controller
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AUTOLOAD:=$(call AutoLoad,60,gsc)
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FILES:=$(PKG_BUILD_DIR)/gsc.ko
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@ -1,28 +0,0 @@
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#
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# Copyright (C) 2010-2012 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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ARCH:=arm
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BOARD:=cns3xxx
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BOARDNAME:=Cavium Networks Econa CNS3xxx
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FEATURES:=squashfs fpu gpio pcie usb usbgadget
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CPU_TYPE:=mpcore
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CPU_SUBTYPE:=vfp
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KERNEL_PATCHVER:=4.19
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define Target/Description
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Build images for Cavium Networks Econa CNS3xxx based boards,
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eg. the Gateworks Laguna family
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endef
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include $(INCLUDE_DIR)/target.mk
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KERNELNAME:=zImage
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DEFAULT_PACKAGES += kmod-ath9k kmod-usb2 wpad-basic-wolfssl
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$(eval $(call BuildTarget))
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@ -1,21 +0,0 @@
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#!/bin/sh /etc/rc.common
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START=99
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get_irq() {
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local name="$1"
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grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,'
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}
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set_irq_affinity() {
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local name="$1"
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local val="$2"
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local irq="$(get_irq "$name")"
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[ -n "$irq" ] || return
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echo "$val" > "/proc/irq/$irq/smp_affinity"
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}
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start() {
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set_irq_affinity gig_switch 2
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set_irq_affinity gig_stat 2
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}
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@ -1,26 +0,0 @@
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CNS3XXX_BOARD_NAME=
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CNS3XXX_MODEL=
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cns3xxx_board_detect() {
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local machine
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local name
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machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /Hardware/ {print $2}' /proc/cpuinfo)
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case "$machine" in
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"Gateworks Corporation Laguna"*)
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name="laguna"
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;;
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*)
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name="generic";
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;;
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esac
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[ -z "$CNS3XXX_BOARD_NAME" ] && CNS3XXX_BOARD_NAME="$name"
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[ -z "$CNS3XXX_MODEL" ] && CNS3XXX_MODEL="$machine"
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[ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
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echo "$CNS3XXX_BOARD_NAME" > /tmp/sysinfo/board_name
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echo "$CNS3XXX_MODEL" > /tmp/sysinfo/model
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}
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@ -1,7 +0,0 @@
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do_sysinfo_cns3xxx() {
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. /lib/cns3xxx.sh
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cns3xxx_board_detect
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}
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boot_hook_add preinit_main do_sysinfo_cns3xxx
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@ -1,19 +0,0 @@
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PART_NAME=firmware
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CI_BLKSZ=65536
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platform_check_image() {
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local magic="$(get_magic_long "$1")"
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[ "$#" -gt 1 ] && return 1
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[ "$magic" != "27051956" ] && {
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echo "Invalid image type."
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return 1
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}
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return 0
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}
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platform_do_upgrade() {
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default_do_upgrade "$1"
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}
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@ -1,368 +0,0 @@
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# CONFIG_AIO is not set
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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CONFIG_ARCH_CNS3XXX=y
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CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
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CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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CONFIG_ARCH_HAS_KCOV=y
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CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
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CONFIG_ARCH_HAS_PHYS_TO_DMA=y
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CONFIG_ARCH_HAS_SET_MEMORY=y
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CONFIG_ARCH_HAS_SG_CHAIN=y
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CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
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CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
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CONFIG_ARCH_HAS_TICK_BROADCAST=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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CONFIG_ARCH_MULTI_V6=y
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CONFIG_ARCH_MULTI_V6_V7=y
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CONFIG_ARCH_NR_GPIO=0
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARM=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_HAS_SG_CHAIN=y
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CONFIG_ARM_HEAVY_MB=y
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CONFIG_ARM_L1_CACHE_SHIFT=5
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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CONFIG_ARM_THUMB=y
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CONFIG_ATA=y
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CONFIG_ATAGS=y
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# CONFIG_ATA_SFF is not set
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CONFIG_ATA_VERBOSE_ERROR=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BCM_NET_PHYLIB=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_SCSI_REQUEST=y
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CONFIG_BROADCOM_PHY=y
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CONFIG_CACHE_L2X0=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="console=ttyS0,115200"
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CONFIG_CMDLINE_FORCE=y
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CONFIG_CNS3XXX_ETH=y
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CONFIG_COMMON_CLK=y
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CONFIG_COREDUMP=y
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CONFIG_CPU_32v6=y
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CONFIG_CPU_32v6K=y
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CONFIG_CPU_ABRT_EV6=y
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_CPU_CACHE_V6=y
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CONFIG_CPU_CACHE_VIPT=y
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CONFIG_CPU_COPY_V6=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_HAS_ASID=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_PABRT_V6=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_THUMB_CAPABLE=y
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CONFIG_CPU_TLB_V6=y
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CONFIG_CPU_V6K=y
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CONFIG_CRASH_DUMP=y
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CONFIG_CRC_CCITT=m
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CONFIG_CRYPTO_AEAD=y
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CONFIG_CRYPTO_AEAD2=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_CRYPTO_MANAGER=y
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CONFIG_CRYPTO_MANAGER2=y
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CONFIG_CRYPTO_NULL2=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_WORKQUEUE=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_ALIGN_RODATA=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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# CONFIG_DEBUG_USER is not set
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CONFIG_DMA_CACHE_FIQ_BROADCAST=y
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CONFIG_DTC=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_ELF_CORE=y
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CONFIG_FIQ=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FRAME_POINTER=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GLOB=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_PCA953X=y
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CONFIG_GPIO_PCA953X_IRQ=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HAVE_ARCH_AUDITSYSCALL=y
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_PFN_VALID=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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CONFIG_HAVE_ARM_SCU=y
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CONFIG_HAVE_ARM_TWD=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CLK_PREPARE=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
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CONFIG_HAVE_EBPF_JIT=y
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CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_OPTPROBES=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PERF_REGS=y
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CONFIG_HAVE_PERF_USER_STACK_DUMP=y
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CONFIG_HAVE_PROC_CPU=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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CONFIG_HAVE_RSEQ=y
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CONFIG_HAVE_SMP=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_UID16=y
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
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CONFIG_HWMON=y
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CONFIG_HZ_FIXED=0
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_CNS3XXX=y
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# CONFIG_INITRAMFS_FORCE is not set
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IP6_NF_FILTER=m
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CONFIG_IP6_NF_IPTABLES=m
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CONFIG_IP6_NF_MANGLE=m
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CONFIG_IP6_NF_TARGET_REJECT=m
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CONFIG_IPV6=y
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CONFIG_IPV6_MROUTE=y
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CONFIG_IPV6_MULTIPLE_TABLES=y
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# CONFIG_IPV6_PIMSM_V2 is not set
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CONFIG_IPV6_SUBTREES=y
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CONFIG_IP_MROUTE_COMMON=y
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CONFIG_IP_NF_FILTER=m
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CONFIG_IP_NF_IPTABLES=m
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CONFIG_IP_NF_MANGLE=m
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CONFIG_IP_NF_NAT=m
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CONFIG_IP_NF_TARGET_MASQUERADE=m
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CONFIG_IP_NF_TARGET_REDIRECT=m
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CONFIG_IP_NF_TARGET_REJECT=m
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_KALLSYMS=y
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CONFIG_KALLSYMS_UNCOMPRESSED=y
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CONFIG_LEDS_GPIO=y
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# CONFIG_LEDS_TRIGGER_NETDEV is not set
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CONFIG_LIBFDT=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_LOCK_SPIN_ON_OWNER=y
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# CONFIG_MACH_CNS3420VB is not set
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CONFIG_MACH_GW2388=y
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MIGHT_HAVE_CACHE_L2X0=y
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CONFIG_MIGHT_HAVE_PCI=y
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CONFIG_MIGRATION=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_CNS3XXX=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MPCORE_WATCHDOG=y
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CONFIG_MTD_M25P80=y
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# CONFIG_MTD_OF_PARTS is not set
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CONFIG_MTD_PHYSMAP=y
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# CONFIG_MTD_PHYSMAP_OF is not set
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_SPLIT_UIMAGE_FW=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NETFILTER=y
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CONFIG_NETFILTER_ADVANCED=y
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CONFIG_NETFILTER_XTABLES=m
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CONFIG_NETFILTER_XT_MARK=m
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CONFIG_NETFILTER_XT_MATCH_COMMENT=m
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CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
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CONFIG_NETFILTER_XT_MATCH_LIMIT=m
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CONFIG_NETFILTER_XT_MATCH_MAC=m
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CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
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CONFIG_NETFILTER_XT_MATCH_STATE=m
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CONFIG_NETFILTER_XT_MATCH_TIME=m
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CONFIG_NETFILTER_XT_NAT=m
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CONFIG_NETFILTER_XT_TARGET_LOG=m
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CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
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CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NF_CONNTRACK=m
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CONFIG_NF_CONNTRACK_RTCACHE=m
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CONFIG_NF_DEFRAG_IPV4=m
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CONFIG_NF_DEFRAG_IPV6=m
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CONFIG_NF_LOG_COMMON=m
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CONFIG_NF_LOG_IPV4=m
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CONFIG_NF_LOG_IPV6=m
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CONFIG_NF_NAT=m
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CONFIG_NF_NAT_IPV4=m
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CONFIG_NF_NAT_NEEDED=y
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CONFIG_NF_NAT_REDIRECT=y
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CONFIG_NF_REJECT_IPV4=m
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CONFIG_NF_REJECT_IPV6=m
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CONFIG_NLS=y
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CONFIG_NO_BOOTMEM=y
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CONFIG_NR_CPUS=2
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CONFIG_NTP_PPS=y
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CONFIG_NVMEM=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_KOBJ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_NET=y
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CONFIG_OF_RESERVED_MEM=y
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CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND3=y
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CONFIG_OUTER_CACHE=y
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CONFIG_OUTER_CACHE_SYNC=y
|
||||
CONFIG_PADATA=y
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CONFIG_PAGE_OFFSET=0xC0000000
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CONFIG_PCI=y
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||||
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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||||
CONFIG_PCI_DOMAINS=y
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||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
# CONFIG_PCI_V3_SEMI is not set
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||||
CONFIG_PERF_USE_VMALLOC=y
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||||
CONFIG_PGTABLE_LEVELS=2
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||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PL310_ERRATA_588369=y
|
||||
CONFIG_PL310_ERRATA_727915=y
|
||||
CONFIG_PL310_ERRATA_753970=y
|
||||
CONFIG_PL310_ERRATA_769419=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PPS_CLIENT_GPIO=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PROC_VMCORE=y
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||||
CONFIG_RAID_ATTRS=y
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||||
CONFIG_RATIONAL=y
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||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_REFCOUNT_FULL=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_SPI=y
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_DS1672=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_MC146818_LIB=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_SATA_AHCI_PLATFORM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SENSORS_AD7418=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=3
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SLHC=m
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_CNS3XXX=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SRCU=y
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_CNS3XXX_EHCI=y
|
||||
CONFIG_USB_CNS3XXX_OHCI=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_DWC2_HOST=y
|
||||
# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_ROLE_SWITCH is not set
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_WATCHDOG_NOWAYOUT=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZBOOT_ROM_BSS=0
|
||||
CONFIG_ZBOOT_ROM_TEXT=0
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Gateworks Corporation
|
||||
* Chris Lang <clang@gateworks.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
|
||||
#define D_CACHE_LINE_SIZE 32
|
||||
|
||||
.text
|
||||
|
||||
/*
|
||||
* R8 - DMA Start Address
|
||||
* R9 - DMA Length
|
||||
* R10 - DMA Direction
|
||||
* R11 - DMA type
|
||||
* R12 - fiq_buffer Address
|
||||
*/
|
||||
|
||||
.global cns3xxx_fiq_end
|
||||
ENTRY(cns3xxx_fiq_start)
|
||||
str r8, [r13]
|
||||
|
||||
ldmia r12, {r8, r9, r10}
|
||||
and r11, r10, #0x3000000
|
||||
and r10, r10, #0xff
|
||||
|
||||
teq r11, #0x1000000
|
||||
beq cns3xxx_dma_map_area
|
||||
teq r11, #0x2000000
|
||||
beq cns3xxx_dma_unmap_area
|
||||
/* fall through */
|
||||
cns3xxx_dma_flush_range:
|
||||
bic r8, r8, #D_CACHE_LINE_SIZE - 1
|
||||
1:
|
||||
mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line
|
||||
add r8, r8, #D_CACHE_LINE_SIZE
|
||||
cmp r8, r9
|
||||
blo 1b
|
||||
/* fall through */
|
||||
cns3xxx_fiq_exit:
|
||||
mov r8, #0
|
||||
str r8, [r12, #8]
|
||||
mcr p15, 0, r8, c7, c10, 4 @ drain write buffer
|
||||
subs pc, lr, #4
|
||||
|
||||
cns3xxx_dma_map_area:
|
||||
add r9, r9, r8
|
||||
teq r10, #DMA_FROM_DEVICE
|
||||
beq cns3xxx_dma_inv_range
|
||||
teq r10, #DMA_TO_DEVICE
|
||||
bne cns3xxx_dma_flush_range
|
||||
/* fall through */
|
||||
cns3xxx_dma_clean_range:
|
||||
bic r8, r8, #D_CACHE_LINE_SIZE - 1
|
||||
1:
|
||||
mcr p15, 0, r8, c7, c10, 1 @ clean D line
|
||||
add r8, r8, #D_CACHE_LINE_SIZE
|
||||
cmp r8, r9
|
||||
blo 1b
|
||||
b cns3xxx_fiq_exit
|
||||
|
||||
cns3xxx_dma_unmap_area:
|
||||
add r9, r9, r8
|
||||
teq r10, #DMA_TO_DEVICE
|
||||
beq cns3xxx_fiq_exit
|
||||
/* fall through */
|
||||
cns3xxx_dma_inv_range:
|
||||
tst r8, #D_CACHE_LINE_SIZE - 1
|
||||
bic r8, r8, #D_CACHE_LINE_SIZE - 1
|
||||
mcrne p15, 0, r8, c7, c10, 1 @ clean D line
|
||||
tst r9, #D_CACHE_LINE_SIZE - 1
|
||||
bic r9, r9, #D_CACHE_LINE_SIZE - 1
|
||||
mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line
|
||||
1:
|
||||
mcr p15, 0, r8, c7, c6, 1 @ invalidate D line
|
||||
add r8, r8, #D_CACHE_LINE_SIZE
|
||||
cmp r8, r9
|
||||
blo 1b
|
||||
b cns3xxx_fiq_exit
|
||||
|
||||
cns3xxx_fiq_end:
|
||||
|
|
@ -1,292 +0,0 @@
|
|||
/*
|
||||
* Copyright 2012 Gateworks Corporation
|
||||
* Chris Lang <clang@gateworks.com>
|
||||
* Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
/*
|
||||
* Registers
|
||||
*/
|
||||
#define GPIO_INPUT 0x04
|
||||
#define GPIO_DIR 0x08
|
||||
#define GPIO_SET 0x10
|
||||
#define GPIO_CLEAR 0x14
|
||||
#define GPIO_INTERRUPT_ENABLE 0x20
|
||||
#define GPIO_INTERRUPT_RAW_STATUS 0x24
|
||||
#define GPIO_INTERRUPT_MASKED_STATUS 0x28
|
||||
#define GPIO_INTERRUPT_MASK 0x2C
|
||||
#define GPIO_INTERRUPT_CLEAR 0x30
|
||||
#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34
|
||||
#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38
|
||||
#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C
|
||||
|
||||
#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0
|
||||
#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
|
||||
#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0
|
||||
#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1
|
||||
#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0
|
||||
#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
|
||||
#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0
|
||||
#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1
|
||||
|
||||
struct cns3xxx_gpio_chip {
|
||||
struct gpio_chip chip;
|
||||
struct irq_domain *domain;
|
||||
spinlock_t lock;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
|
||||
static int cns3xxx_gpio_chip_count;
|
||||
|
||||
static inline void
|
||||
__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = __raw_readl(cchip->base + GPIO_DIR);
|
||||
if (input)
|
||||
reg &= ~(1 << pin);
|
||||
else
|
||||
reg |= (1 << pin);
|
||||
__raw_writel(reg, cchip->base + GPIO_DIR);
|
||||
}
|
||||
|
||||
/*
|
||||
* GENERIC_GPIO primatives
|
||||
*/
|
||||
static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct cns3xxx_gpio_chip *cchip =
|
||||
container_of(chip, struct cns3xxx_gpio_chip, chip);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&cchip->lock, flags);
|
||||
__set_direction(cchip, pin, 1);
|
||||
spin_unlock_irqrestore(&cchip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct cns3xxx_gpio_chip *cchip =
|
||||
container_of(chip, struct cns3xxx_gpio_chip, chip);
|
||||
int val;
|
||||
|
||||
val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
|
||||
{
|
||||
struct cns3xxx_gpio_chip *cchip =
|
||||
container_of(chip, struct cns3xxx_gpio_chip, chip);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&cchip->lock, flags);
|
||||
if (level)
|
||||
__raw_writel(1 << pin, cchip->base + GPIO_SET);
|
||||
else
|
||||
__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
|
||||
__set_direction(cchip, pin, 0);
|
||||
spin_unlock_irqrestore(&cchip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
|
||||
int level)
|
||||
{
|
||||
struct cns3xxx_gpio_chip *cchip =
|
||||
container_of(chip, struct cns3xxx_gpio_chip, chip);
|
||||
|
||||
if (level)
|
||||
__raw_writel(1 << pin, cchip->base + GPIO_SET);
|
||||
else
|
||||
__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
|
||||
}
|
||||
|
||||
static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
struct cns3xxx_gpio_chip *cchip =
|
||||
container_of(chip, struct cns3xxx_gpio_chip, chip);
|
||||
|
||||
return irq_find_mapping(cchip->domain, pin);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* IRQ support
|
||||
*/
|
||||
|
||||
/* one interrupt per GPIO controller (GPIOA/GPIOB)
|
||||
* this is called in task context, with IRQs enabled
|
||||
*/
|
||||
static void cns3xxx_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct cns3xxx_gpio_chip *cchip = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
u16 i;
|
||||
u32 reg;
|
||||
|
||||
chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
|
||||
|
||||
/* see which pin(s) triggered the interrupt */
|
||||
reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (reg & (1 << i)) {
|
||||
/* let the generic IRQ layer handle an interrupt */
|
||||
generic_handle_irq(irq_find_mapping(cchip->domain, i));
|
||||
}
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc); /* unmask the base interrupt */
|
||||
}
|
||||
|
||||
static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct cns3xxx_gpio_chip *cchip = gc->private;
|
||||
u32 gpio = d->hwirq;
|
||||
unsigned long flags;
|
||||
u32 method, edges, type;
|
||||
|
||||
spin_lock_irqsave(&cchip->lock, flags);
|
||||
method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
|
||||
edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
|
||||
type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
|
||||
method &= ~(1 << gpio);
|
||||
edges &= ~(1 << gpio);
|
||||
type &= ~(1 << gpio);
|
||||
|
||||
switch(irqtype) {
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
|
||||
edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
|
||||
type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
|
||||
edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
|
||||
type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
|
||||
edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
|
||||
type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
|
||||
type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_WARNING "No irq type\n");
|
||||
spin_unlock_irqrestore(&cchip->lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
__raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
|
||||
__raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
|
||||
__raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
|
||||
spin_unlock_irqrestore(&cchip->lock, flags);
|
||||
|
||||
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
|
||||
u32 base, int irq, int secondary_irq_base)
|
||||
{
|
||||
struct cns3xxx_gpio_chip *cchip;
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
char gc_label[16];
|
||||
int irq_base;
|
||||
|
||||
if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
|
||||
return;
|
||||
|
||||
snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
|
||||
cns3xxx_gpio_chip_count);
|
||||
|
||||
cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
|
||||
cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
|
||||
cchip->chip.direction_input = cns3xxx_gpio_direction_input;
|
||||
cchip->chip.get = cns3xxx_gpio_get;
|
||||
cchip->chip.direction_output = cns3xxx_gpio_direction_output;
|
||||
cchip->chip.set = cns3xxx_gpio_set;
|
||||
cchip->chip.to_irq = cns3xxx_gpio_to_irq;
|
||||
cchip->chip.base = gpio_base;
|
||||
cchip->chip.ngpio = ngpio;
|
||||
cchip->chip.can_sleep = 0;
|
||||
spin_lock_init(&cchip->lock);
|
||||
cchip->base = (void __iomem *)base;
|
||||
|
||||
BUG_ON(gpiochip_add(&cchip->chip) < 0);
|
||||
cns3xxx_gpio_chip_count++;
|
||||
|
||||
/* clear GPIO interrupts */
|
||||
__raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
|
||||
|
||||
irq_base = irq_alloc_descs(-1, secondary_irq_base, ngpio,
|
||||
numa_node_id());
|
||||
if (irq_base < 0)
|
||||
goto out_irqdesc_free;
|
||||
|
||||
cchip->domain = irq_domain_add_legacy(NULL, ngpio, irq_base, 0,
|
||||
&irq_domain_simple_ops, NULL);
|
||||
if (!cchip->domain)
|
||||
goto out_irqdesc_free;
|
||||
|
||||
/*
|
||||
* IRQ chip init
|
||||
*/
|
||||
gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, irq_base,
|
||||
cchip->base, handle_edge_irq);
|
||||
|
||||
gc->private = cchip;
|
||||
|
||||
ct = gc->chip_types;
|
||||
ct->type = IRQ_TYPE_EDGE_FALLING;
|
||||
ct->regs.ack = GPIO_INTERRUPT_CLEAR;
|
||||
ct->chip.irq_ack = irq_gc_ack_set_bit;
|
||||
ct->regs.mask = GPIO_INTERRUPT_ENABLE;
|
||||
ct->chip.irq_enable = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_disable = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
|
||||
ct->handler = handle_edge_irq;
|
||||
|
||||
irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
|
||||
IRQ_NOREQUEST, 0);
|
||||
irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
|
||||
irq_set_handler_data(irq, cchip);
|
||||
|
||||
return;
|
||||
|
||||
out_irqdesc_free:
|
||||
irq_free_descs(irq_base, ngpio);
|
||||
}
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-cns3xxx/headsmp.S
|
||||
*
|
||||
* Cloned from linux/arch/arm/plat-versatile/headsmp.S
|
||||
*
|
||||
* Copyright (c) 2003 ARM Limited
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
/*
|
||||
* CNS3XXX specific entry point for secondary CPUs. This provides
|
||||
* a "holding pen" into which all secondary cores are held until we're
|
||||
* ready for them to initialise.
|
||||
*/
|
||||
ENTRY(cns3xxx_secondary_startup)
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #15
|
||||
adr r4, 1f
|
||||
ldmia r4, {r5, r6}
|
||||
sub r4, r4, r5
|
||||
add r6, r6, r4
|
||||
pen: ldr r7, [r6]
|
||||
cmp r7, r0
|
||||
bne pen
|
||||
|
||||
/*
|
||||
* we've been released from the holding pen: secondary_stack
|
||||
* should now contain the SVC stack for this core
|
||||
*/
|
||||
b secondary_startup
|
||||
ENDPROC(cns3xxx_secondary_startup)
|
||||
|
||||
.align 2
|
||||
1: .long .
|
||||
.long pen_release
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
/* linux arch/arm/mach-cns3xxx/hotplug.c
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-realview/hotplug.c
|
||||
*
|
||||
* Copyright (C) 2002 ARM Ltd.
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
extern volatile int pen_release;
|
||||
|
||||
static inline void cpu_enter_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
flush_cache_all();
|
||||
asm volatile(
|
||||
" mcr p15, 0, %1, c7, c5, 0\n"
|
||||
" mcr p15, 0, %1, c7, c10, 4\n"
|
||||
/*
|
||||
* Turn off coherency
|
||||
*/
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" bic %0, %0, %3\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
" mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" bic %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=&r" (v)
|
||||
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline void cpu_leave_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
asm volatile(
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" orr %0, %0, %1\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" orr %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
: "=&r" (v)
|
||||
: "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
|
||||
{
|
||||
/*
|
||||
* there is no power-control hardware on this platform, so all
|
||||
* we can do is put the core into WFI; this is safe as the calling
|
||||
* code will have already disabled interrupts
|
||||
*/
|
||||
for (;;) {
|
||||
/*
|
||||
* here's the WFI
|
||||
*/
|
||||
asm(".word 0xe320f003\n"
|
||||
:
|
||||
:
|
||||
: "memory", "cc");
|
||||
|
||||
if (pen_release == cpu) {
|
||||
/*
|
||||
* OK, proper wakeup, we're done
|
||||
*/
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Getting here, means that we have come out of WFI without
|
||||
* having been woken up - this shouldn't happen
|
||||
*
|
||||
* Just note it happening - when we're woken, we can report
|
||||
* its occurrence.
|
||||
*/
|
||||
(*spurious)++;
|
||||
}
|
||||
}
|
||||
|
||||
int platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* platform-specific code to shutdown a CPU
|
||||
*
|
||||
* Called with IRQs disabled
|
||||
*/
|
||||
void platform_cpu_die(unsigned int cpu)
|
||||
{
|
||||
int spurious = 0;
|
||||
|
||||
/*
|
||||
* we're ready for shutdown now, so do it
|
||||
*/
|
||||
cpu_enter_lowpower();
|
||||
platform_do_lowpower(cpu, &spurious);
|
||||
|
||||
/*
|
||||
* bring this CPU back into the world of cache
|
||||
* coherency, and then restore interrupts
|
||||
*/
|
||||
cpu_leave_lowpower();
|
||||
|
||||
if (spurious)
|
||||
pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
|
||||
}
|
||||
|
||||
int platform_cpu_disable(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* we don't allow CPU 0 to be shutdown (it is still too special
|
||||
* e.g. clock tick interrupts)
|
||||
*/
|
||||
return cpu == 0 ? -EPERM : 0;
|
||||
}
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-cns3xxx/include/mach/gpio.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
|
||||
#define __ASM_ARCH_CNS3XXX_GPIO_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
|
||||
u32 base, int irq, int secondary_irq_base);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
#ifndef __MACH_SMP_H
|
||||
#define __MACH_SMP_H
|
||||
|
||||
extern void smp_dma_map_area(const void *, size_t, int);
|
||||
extern void smp_dma_unmap_area(const void *, size_t, int);
|
||||
extern void smp_dma_flush_range(const void *, const void *);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,327 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-cns3xxx/platsmp.c
|
||||
*
|
||||
* Copyright (C) 2002 ARM Ltd.
|
||||
* Copyright 2012 Gateworks Corporation
|
||||
* Chris Lang <clang@gateworks.com>
|
||||
* Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/unified.h>
|
||||
#include <asm/fiq.h>
|
||||
#include <mach/smp.h>
|
||||
#include "cns3xxx.h"
|
||||
|
||||
static struct fiq_handler fh = {
|
||||
.name = "cns3xxx-fiq"
|
||||
};
|
||||
|
||||
struct fiq_req {
|
||||
union {
|
||||
struct {
|
||||
const void *addr;
|
||||
size_t size;
|
||||
} map;
|
||||
struct {
|
||||
const void *addr;
|
||||
size_t size;
|
||||
} unmap;
|
||||
struct {
|
||||
const void *start;
|
||||
const void *end;
|
||||
} flush;
|
||||
};
|
||||
volatile uint flags;
|
||||
void __iomem *reg;
|
||||
} ____cacheline_aligned;
|
||||
|
||||
extern unsigned int fiq_number[2];
|
||||
|
||||
DEFINE_PER_CPU(struct fiq_req, fiq_data);
|
||||
|
||||
#define FIQ_ENABLED 0x80000000
|
||||
#define FIQ_GENERATE 0x00010000
|
||||
#define CNS3XXX_MAP_AREA 0x01000000
|
||||
#define CNS3XXX_UNMAP_AREA 0x02000000
|
||||
#define CNS3XXX_FLUSH_RANGE 0x03000000
|
||||
|
||||
extern void cns3xxx_secondary_startup(void);
|
||||
extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
|
||||
|
||||
#define SCU_CPU_STATUS 0x08
|
||||
static void __iomem *scu_base;
|
||||
|
||||
static inline void cns3xxx_set_fiq_regs(unsigned int cpu)
|
||||
{
|
||||
struct pt_regs FIQ_regs;
|
||||
struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
|
||||
|
||||
FIQ_regs.ARM_r8 = 0;
|
||||
FIQ_regs.ARM_ip = (unsigned int)fiq_req;
|
||||
FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu);
|
||||
fiq_req->reg = MISC_FIQ_CPU(!cpu);
|
||||
|
||||
set_fiq_regs(&FIQ_regs);
|
||||
}
|
||||
|
||||
static void __init cns3xxx_init_fiq(void)
|
||||
{
|
||||
void *fiqhandler_start;
|
||||
unsigned int fiqhandler_length;
|
||||
int ret;
|
||||
|
||||
fiqhandler_start = &cns3xxx_fiq_start;
|
||||
fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
|
||||
|
||||
ret = claim_fiq(&fh);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
set_fiq_handler(fiqhandler_start, fiqhandler_length);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Write pen_release in a way that is guaranteed to be visible to all
|
||||
* observers, irrespective of whether they're taking part in coherency
|
||||
* or not. This is necessary for the hotplug code to work reliably.
|
||||
*/
|
||||
static void write_pen_release(int val)
|
||||
{
|
||||
pen_release = val;
|
||||
smp_wmb();
|
||||
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
|
||||
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
static void cns3xxx_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* Setup Secondary Core FIQ regs
|
||||
*/
|
||||
cns3xxx_set_fiq_regs(1);
|
||||
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
*/
|
||||
write_pen_release(-1);
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
static int cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/*
|
||||
* Set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/*
|
||||
* The secondary processor is waiting to be released from
|
||||
* the holding pen - release it, then wait for it to flag
|
||||
* that it has been released by resetting pen_release.
|
||||
*
|
||||
* Note that "pen_release" is the hardware CPU ID, whereas
|
||||
* "cpu" is Linux's internal ID.
|
||||
*/
|
||||
write_pen_release(cpu);
|
||||
|
||||
/*
|
||||
* Send the secondary CPU a soft interrupt, thereby causing
|
||||
* the boot monitor to read the system wide flags register,
|
||||
* and branch to the address found there.
|
||||
*/
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));;
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
smp_rmb();
|
||||
if (pen_release == -1)
|
||||
break;
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return pen_release != -1 ? -ENOSYS : 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise the CPU possible map early - this describes the CPUs
|
||||
* which may be present or become present in the system.
|
||||
*/
|
||||
static void __init cns3xxx_smp_init_cpus(void)
|
||||
{
|
||||
unsigned int i, ncores;
|
||||
unsigned int status;
|
||||
|
||||
scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
|
||||
|
||||
/* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
|
||||
* used in scu_get_core_count
|
||||
*/
|
||||
status = __raw_readl(scu_base + SCU_CPU_STATUS);
|
||||
for (i = 0; i < NR_CPUS+1; i++) {
|
||||
if (((status >> (i*2)) & 0x3) == 0)
|
||||
set_cpu_possible(i, true);
|
||||
else
|
||||
break;
|
||||
}
|
||||
ncores = i;
|
||||
}
|
||||
|
||||
static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
/*
|
||||
* enable SCU
|
||||
*/
|
||||
scu_enable(scu_base);
|
||||
|
||||
/*
|
||||
* Write the address of secondary startup into the
|
||||
* system-wide flags register. The boot monitor waits
|
||||
* until it receives a soft interrupt, and then the
|
||||
* secondary CPU branches to this address.
|
||||
*/
|
||||
__raw_writel(virt_to_phys(cns3xxx_secondary_startup),
|
||||
(void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
|
||||
|
||||
/*
|
||||
* Setup FIQ's for main cpu
|
||||
*/
|
||||
cns3xxx_init_fiq();
|
||||
cns3xxx_set_fiq_regs(0);
|
||||
}
|
||||
|
||||
extern void v6_dma_map_area(const void *, size_t, int);
|
||||
extern void v6_dma_unmap_area(const void *, size_t, int);
|
||||
extern void v6_dma_flush_range(const void *, const void *);
|
||||
extern void v6_flush_kern_dcache_area(void *, size_t);
|
||||
|
||||
void fiq_dma_map_area(const void *addr, size_t size, int dir)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct fiq_req *req;
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
/* currently, not possible to take cpu0 down, so only check cpu1 */
|
||||
if (!cpu_online(1)) {
|
||||
raw_local_irq_restore(flags);
|
||||
v6_dma_map_area(addr, size, dir);
|
||||
return;
|
||||
}
|
||||
|
||||
req = this_cpu_ptr(&fiq_data);
|
||||
req->map.addr = addr;
|
||||
req->map.size = size;
|
||||
req->flags = dir | CNS3XXX_MAP_AREA;
|
||||
smp_mb();
|
||||
|
||||
writel_relaxed(FIQ_GENERATE, req->reg);
|
||||
|
||||
v6_dma_map_area(addr, size, dir);
|
||||
while (req->flags)
|
||||
barrier();
|
||||
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct fiq_req *req;
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
/* currently, not possible to take cpu0 down, so only check cpu1 */
|
||||
if (!cpu_online(1)) {
|
||||
raw_local_irq_restore(flags);
|
||||
v6_dma_unmap_area(addr, size, dir);
|
||||
return;
|
||||
}
|
||||
|
||||
req = this_cpu_ptr(&fiq_data);
|
||||
req->unmap.addr = addr;
|
||||
req->unmap.size = size;
|
||||
req->flags = dir | CNS3XXX_UNMAP_AREA;
|
||||
smp_mb();
|
||||
|
||||
writel_relaxed(FIQ_GENERATE, req->reg);
|
||||
|
||||
v6_dma_unmap_area(addr, size, dir);
|
||||
while (req->flags)
|
||||
barrier();
|
||||
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void fiq_dma_flush_range(const void *start, const void *end)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct fiq_req *req;
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
/* currently, not possible to take cpu0 down, so only check cpu1 */
|
||||
if (!cpu_online(1)) {
|
||||
raw_local_irq_restore(flags);
|
||||
v6_dma_flush_range(start, end);
|
||||
return;
|
||||
}
|
||||
|
||||
req = this_cpu_ptr(&fiq_data);
|
||||
|
||||
req->flush.start = start;
|
||||
req->flush.end = end;
|
||||
req->flags = CNS3XXX_FLUSH_RANGE;
|
||||
smp_mb();
|
||||
|
||||
writel_relaxed(FIQ_GENERATE, req->reg);
|
||||
|
||||
v6_dma_flush_range(start, end);
|
||||
|
||||
while (req->flags)
|
||||
barrier();
|
||||
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void fiq_flush_kern_dcache_area(void *addr, size_t size)
|
||||
{
|
||||
fiq_dma_flush_range(addr, addr + size);
|
||||
}
|
||||
|
||||
struct smp_operations cns3xxx_smp_ops __initdata = {
|
||||
.smp_init_cpus = cns3xxx_smp_init_cpus,
|
||||
.smp_prepare_cpus = cns3xxx_smp_prepare_cpus,
|
||||
.smp_secondary_init = cns3xxx_secondary_init,
|
||||
.smp_boot_secondary = cns3xxx_boot_secondary,
|
||||
};
|
||||
|
|
@ -1,374 +0,0 @@
|
|||
/*
|
||||
* Cavium CNS3xxx I2C Host Controller
|
||||
*
|
||||
* Copyright 2010 Cavium Network
|
||||
* Copyright 2012 Gateworks Corporation
|
||||
* Chris Lang <clang@gateworks.com>
|
||||
* Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
/*
|
||||
* We need the memory map
|
||||
*/
|
||||
|
||||
#define I2C_MEM_MAP_ADDR(x) (i2c->base + x)
|
||||
#define I2C_MEM_MAP_VALUE(x) (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x)))
|
||||
|
||||
#define I2C_CONTROLLER_REG I2C_MEM_MAP_VALUE(0x00)
|
||||
#define I2C_TIME_OUT_REG I2C_MEM_MAP_VALUE(0x04)
|
||||
#define I2C_SLAVE_ADDRESS_REG I2C_MEM_MAP_VALUE(0x08)
|
||||
#define I2C_WRITE_DATA_REG I2C_MEM_MAP_VALUE(0x0C)
|
||||
#define I2C_READ_DATA_REG I2C_MEM_MAP_VALUE(0x10)
|
||||
#define I2C_INTERRUPT_STATUS_REG I2C_MEM_MAP_VALUE(0x14)
|
||||
#define I2C_INTERRUPT_ENABLE_REG I2C_MEM_MAP_VALUE(0x18)
|
||||
#define I2C_TWI_OUT_DLY_REG I2C_MEM_MAP_VALUE(0x1C)
|
||||
|
||||
#define I2C_BUS_ERROR_FLAG (0x1)
|
||||
#define I2C_ACTION_DONE_FLAG (0x2)
|
||||
|
||||
#define CNS3xxx_I2C_ENABLE() (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31)
|
||||
#define CNS3xxx_I2C_DISABLE() (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31)
|
||||
#define CNS3xxx_I2C_ENABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) |= 0x03
|
||||
#define CNS3xxx_I2C_DISABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) &= 0xfc
|
||||
|
||||
#define TWI_TIMEOUT (10*HZ)
|
||||
#define I2C_100KHZ 100000
|
||||
#define I2C_200KHZ 200000
|
||||
#define I2C_300KHZ 300000
|
||||
#define I2C_400KHZ 400000
|
||||
|
||||
#define CNS3xxx_I2C_CLK I2C_100KHZ
|
||||
|
||||
#define STATE_DONE 1
|
||||
#define STATE_ERROR 2
|
||||
|
||||
struct cns3xxx_i2c {
|
||||
struct device *dev;
|
||||
void __iomem *base; /* virtual */
|
||||
wait_queue_head_t wait;
|
||||
struct i2c_adapter adap;
|
||||
struct i2c_msg *msg;
|
||||
u8 state; /* see STATE_ */
|
||||
u8 error; /* see TWI_STATUS register */
|
||||
int rd_wr_len;
|
||||
u8 *buf;
|
||||
};
|
||||
|
||||
static u32 cns3xxx_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static int
|
||||
cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg)
|
||||
{
|
||||
struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap);
|
||||
int i, j;
|
||||
u8 buf[1] = { 0 };
|
||||
|
||||
if (msg->len == 0) {
|
||||
/*
|
||||
* We are probably doing a probe for a device here,
|
||||
* so set the length to one, and data to 0
|
||||
*/
|
||||
msg->len = 1;
|
||||
i2c->buf = buf;
|
||||
} else {
|
||||
i2c->buf = msg->buf;
|
||||
}
|
||||
|
||||
if (msg->flags & I2C_M_TEN) {
|
||||
printk
|
||||
("%s:%d: Presently the driver does not handle extended addressing\n",
|
||||
__FUNCTION__, __LINE__);
|
||||
return -EINVAL;
|
||||
}
|
||||
i2c->msg = msg;
|
||||
|
||||
for (i = 0; i < msg->len; i++) {
|
||||
if (msg->len - i >= 4)
|
||||
i2c->rd_wr_len = 3;
|
||||
else
|
||||
i2c->rd_wr_len = msg->len - i - 1;
|
||||
|
||||
// Set Data Width and TWI_EN
|
||||
I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
|
||||
|
||||
// Clear Write Reg
|
||||
I2C_WRITE_DATA_REG = 0;
|
||||
|
||||
// Set the slave address
|
||||
I2C_SLAVE_ADDRESS_REG = (msg->addr << 1);
|
||||
|
||||
// Are we Writing
|
||||
if (!(msg->flags & I2C_M_RD)) {
|
||||
I2C_CONTROLLER_REG |= (1 << 4);
|
||||
if (i != 0) {
|
||||
/*
|
||||
* We need to set the address in the first byte.
|
||||
* The base address is going to be in buf[0] and then
|
||||
* it needs to be incremented by i - 1.
|
||||
*/
|
||||
i2c->buf--;
|
||||
*i2c->buf = buf[0] + i - 1;
|
||||
|
||||
if (i2c->rd_wr_len < 3) {
|
||||
i += i2c->rd_wr_len;
|
||||
i2c->rd_wr_len++;
|
||||
I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len);
|
||||
} else {
|
||||
i += i2c->rd_wr_len - 1;
|
||||
}
|
||||
} else {
|
||||
i += i2c->rd_wr_len;
|
||||
buf[0] = *i2c->buf;
|
||||
}
|
||||
for (j = 0; j <= i2c->rd_wr_len; j++) {
|
||||
I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j));
|
||||
}
|
||||
} else {
|
||||
i += i2c->rd_wr_len;
|
||||
}
|
||||
|
||||
// Start the Transfer
|
||||
i2c->state = 0; // Clear out the State
|
||||
i2c->error = 0;
|
||||
I2C_CONTROLLER_REG |= (1 << 6);
|
||||
|
||||
if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
|
||||
(i2c->state == STATE_DONE), TWI_TIMEOUT)) {
|
||||
if (i2c->state == STATE_ERROR) {
|
||||
dev_dbg(i2c->dev, "controller error: 0x%2x", i2c->error);
|
||||
return -EAGAIN; // try again
|
||||
}
|
||||
} else {
|
||||
dev_err(i2c->dev, "controller timed out "
|
||||
"waiting for start condition to finish\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return num;
|
||||
}
|
||||
|
||||
|
||||
static struct i2c_algorithm cns3xxx_i2c_algo = {
|
||||
.master_xfer = cns3xxx_i2c_xfer,
|
||||
.functionality = cns3xxx_i2c_func,
|
||||
};
|
||||
|
||||
static struct i2c_adapter cns3xxx_i2c_adapter = {
|
||||
.owner = THIS_MODULE,
|
||||
.algo = &cns3xxx_i2c_algo,
|
||||
.algo_data = NULL,
|
||||
.nr = 0,
|
||||
.name = "CNS3xxx I2C 0",
|
||||
.retries = 5,
|
||||
};
|
||||
|
||||
static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = devm_clk_get(i2c->dev, "cpu");
|
||||
if (WARN_ON(!clk))
|
||||
return;
|
||||
|
||||
/* Disable the I2C */
|
||||
I2C_CONTROLLER_REG = 0; /* Disabled the I2C */
|
||||
|
||||
/* Check the Reg Dump when testing */
|
||||
I2C_TIME_OUT_REG =
|
||||
(((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) -
|
||||
1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
|
||||
I2C_TWI_OUT_DLY_REG |= 0x3;
|
||||
|
||||
/* Enable The Interrupt */
|
||||
CNS3xxx_I2C_ENABLE_INTR();
|
||||
|
||||
/* Clear Interrupt Status (0x2 | 0x1) */
|
||||
I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG);
|
||||
|
||||
/* Enable the I2C Controller */
|
||||
CNS3xxx_I2C_ENABLE();
|
||||
}
|
||||
|
||||
static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct cns3xxx_i2c *i2c = dev_id;
|
||||
int i;
|
||||
uint32_t stat = I2C_INTERRUPT_STATUS_REG;
|
||||
|
||||
/* Clear Interrupt */
|
||||
I2C_INTERRUPT_STATUS_REG |= 0x1;
|
||||
|
||||
if (stat & I2C_BUS_ERROR_FLAG) {
|
||||
i2c->state = STATE_ERROR;
|
||||
i2c->error = (I2C_INTERRUPT_STATUS_REG & 0xff00)>>8;
|
||||
} else {
|
||||
if (i2c->msg->flags & I2C_M_RD) {
|
||||
for (i = 0; i <= i2c->rd_wr_len; i++)
|
||||
{
|
||||
*i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff);
|
||||
}
|
||||
}
|
||||
i2c->state = STATE_DONE;
|
||||
}
|
||||
wake_up(&i2c->wait);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int cns3xxx_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct cns3xxx_i2c *i2c;
|
||||
struct resource *res, *res2;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res2) {
|
||||
printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
|
||||
if (!i2c)
|
||||
return -ENOMEM;
|
||||
|
||||
if (!request_mem_region(res->start, res->end - res->start + 1,
|
||||
pdev->name)) {
|
||||
dev_err(&pdev->dev, "Memory region busy\n");
|
||||
ret = -EBUSY;
|
||||
goto request_mem_failed;
|
||||
}
|
||||
|
||||
i2c->dev = &pdev->dev;
|
||||
i2c->base = ioremap(res->start, res->end - res->start + 1);
|
||||
if (!i2c->base) {
|
||||
dev_err(&pdev->dev, "Unable to map registers\n");
|
||||
ret = -EIO;
|
||||
goto map_failed;
|
||||
}
|
||||
|
||||
cns3xxx_i2c_adapter_init(i2c);
|
||||
|
||||
init_waitqueue_head(&i2c->wait);
|
||||
ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
||||
goto request_irq_failed;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, i2c);
|
||||
i2c->adap = cns3xxx_i2c_adapter;
|
||||
i2c_set_adapdata(&i2c->adap, i2c);
|
||||
i2c->adap.dev.parent = &pdev->dev;
|
||||
|
||||
/* add i2c adapter to i2c tree */
|
||||
ret = i2c_add_numbered_adapter(&i2c->adap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to add adapter\n");
|
||||
goto add_adapter_failed;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
add_adapter_failed:
|
||||
free_irq(res2->start, i2c);
|
||||
request_irq_failed:
|
||||
iounmap(i2c->base);
|
||||
map_failed:
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
request_mem_failed:
|
||||
kfree(i2c);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cns3xxx_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev);
|
||||
struct resource *res;
|
||||
|
||||
/* disable i2c logic */
|
||||
CNS3xxx_I2C_DISABLE_INTR();
|
||||
CNS3xxx_I2C_DISABLE();
|
||||
/* remove adapter & data */
|
||||
i2c_del_adapter(&i2c->adap);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (res)
|
||||
free_irq(res->start, i2c);
|
||||
|
||||
iounmap(i2c->base);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res)
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
|
||||
kfree(i2c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver cns3xxx_i2c_driver = {
|
||||
.probe = cns3xxx_i2c_probe,
|
||||
.remove = cns3xxx_i2c_remove,
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "cns3xxx-i2c",
|
||||
},
|
||||
};
|
||||
|
||||
static int __init cns3xxx_i2c_init(void)
|
||||
{
|
||||
return platform_driver_register(&cns3xxx_i2c_driver);
|
||||
}
|
||||
|
||||
static void __exit cns3xxx_i2c_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&cns3xxx_i2c_driver);
|
||||
}
|
||||
|
||||
module_init(cns3xxx_i2c_init);
|
||||
module_exit(cns3xxx_i2c_exit);
|
||||
|
||||
MODULE_AUTHOR("Cavium Networks");
|
||||
MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
config NET_VENDOR_CAVIUM
|
||||
bool "Cavium devices"
|
||||
default y
|
||||
depends on ARCH_CNS3XXX
|
||||
---help---
|
||||
If you have a network (Ethernet) chipset belonging to this class,
|
||||
say Y.
|
||||
|
||||
Note that the answer to this question does not directly affect
|
||||
the kernel: saying N will just case the configurator to skip all
|
||||
the questions regarding AMD chipsets. If you say Y, you will be asked
|
||||
for your specific chipset/driver in the following questions.
|
||||
|
||||
if NET_VENDOR_CAVIUM
|
||||
|
||||
config CNS3XXX_ETH
|
||||
tristate "Cavium CNS3xxx Ethernet support"
|
||||
depends on ARCH_CNS3XXX
|
||||
select PHYLIB
|
||||
help
|
||||
Say Y here if you want to use built-in Ethernet ports
|
||||
on CNS3XXX processor.
|
||||
|
||||
endif
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
#
|
||||
# Makefile for the Cavium ethernet device drivers.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_CNS3XXX_ETH) += cns3xxx_eth.o
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,448 +0,0 @@
|
|||
/*******************************************************************************
|
||||
*
|
||||
* CNS3XXX SPI controller driver (master mode only)
|
||||
*
|
||||
* Copyright (c) 2008 Cavium Networks
|
||||
* Copyright 2011 Gateworks Corporation
|
||||
* Chris Lang <clang@gateworks.com>
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
|
||||
* NONINFRINGEMENT. See the GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this file; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
|
||||
* visit http://www.gnu.org/licenses/.
|
||||
*
|
||||
* This file may also be available under a different license from Cavium.
|
||||
* Contact Cavium Networks for more information
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi_bitbang.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/delay.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
/*
|
||||
* define access macros
|
||||
*/
|
||||
#define SPI_MEM_MAP_VALUE(reg_offset) (*((u32 volatile *)(hw->base + reg_offset)))
|
||||
|
||||
#define SPI_CONFIGURATION_REG SPI_MEM_MAP_VALUE(0x00)
|
||||
#define SPI_SERVICE_STATUS_REG SPI_MEM_MAP_VALUE(0x04)
|
||||
#define SPI_BIT_RATE_CONTROL_REG SPI_MEM_MAP_VALUE(0x08)
|
||||
#define SPI_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x0C)
|
||||
#define SPI_TRANSMIT_BUFFER_REG SPI_MEM_MAP_VALUE(0x10)
|
||||
#define SPI_RECEIVE_CONTROL_REG SPI_MEM_MAP_VALUE(0x14)
|
||||
#define SPI_RECEIVE_BUFFER_REG SPI_MEM_MAP_VALUE(0x18)
|
||||
#define SPI_FIFO_TRANSMIT_CONFIG_REG SPI_MEM_MAP_VALUE(0x1C)
|
||||
#define SPI_FIFO_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x20)
|
||||
#define SPI_FIFO_RECEIVE_CONFIG_REG SPI_MEM_MAP_VALUE(0x24)
|
||||
#define SPI_INTERRUPT_STATUS_REG SPI_MEM_MAP_VALUE(0x28)
|
||||
#define SPI_INTERRUPT_ENABLE_REG SPI_MEM_MAP_VALUE(0x2C)
|
||||
|
||||
#define SPI_TRANSMIT_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x10)
|
||||
#define SPI_RECEIVE_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x18)
|
||||
|
||||
/* Structure for SPI controller of CNS3XXX SOCs */
|
||||
struct cns3xxx_spi {
|
||||
/* bitbang has to be first */
|
||||
struct spi_bitbang bitbang;
|
||||
struct completion done;
|
||||
wait_queue_head_t wait;
|
||||
|
||||
int len;
|
||||
int count;
|
||||
int last_in_message_list;
|
||||
|
||||
/* data buffers */
|
||||
const unsigned char *tx;
|
||||
unsigned char *rx;
|
||||
|
||||
void __iomem *base;
|
||||
struct spi_master *master;
|
||||
struct platform_device *pdev;
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
static inline u8 cns3xxx_spi_bus_idle(struct cns3xxx_spi *hw)
|
||||
{
|
||||
return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1);
|
||||
}
|
||||
|
||||
static inline u8 cns3xxx_spi_tx_buffer_empty(struct cns3xxx_spi *hw)
|
||||
{
|
||||
return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline u8 cns3xxx_spi_rx_buffer_full(struct cns3xxx_spi *hw)
|
||||
{
|
||||
return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0);
|
||||
}
|
||||
|
||||
u8 cns3xxx_spi_tx_rx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof,
|
||||
u32 tx_data, u32 * rx_data)
|
||||
{
|
||||
u8 rx_channel;
|
||||
u8 rx_eof;
|
||||
|
||||
while (!cns3xxx_spi_bus_idle(hw)) ; // do nothing
|
||||
|
||||
while (!cns3xxx_spi_tx_buffer_empty(hw)) ; // do nothing
|
||||
|
||||
SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
|
||||
SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
|
||||
|
||||
SPI_TRANSMIT_BUFFER_REG = tx_data;
|
||||
|
||||
while (!cns3xxx_spi_rx_buffer_full(hw)) ; // do nothing
|
||||
|
||||
rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3;
|
||||
rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0;
|
||||
|
||||
*rx_data = SPI_RECEIVE_BUFFER_REG;
|
||||
|
||||
if ((tx_channel != rx_channel) || (tx_eof != rx_eof)) {
|
||||
return 0;
|
||||
} else {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
u8 cns3xxx_spi_tx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, u32 tx_data)
|
||||
{
|
||||
|
||||
while (!cns3xxx_spi_bus_idle(hw)) ; // do nothing
|
||||
|
||||
while (!cns3xxx_spi_tx_buffer_empty(hw)) ; // do nothing
|
||||
|
||||
SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
|
||||
SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
|
||||
|
||||
SPI_TRANSMIT_BUFFER_REG = tx_data;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline struct cns3xxx_spi *to_hw(struct spi_device *sdev)
|
||||
{
|
||||
return spi_master_get_devdata(sdev->master);
|
||||
}
|
||||
|
||||
static int cns3xxx_spi_setup_transfer(struct spi_device *spi,
|
||||
struct spi_transfer *t)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cns3xxx_spi_chipselect(struct spi_device *spi, int value)
|
||||
{
|
||||
struct cns3xxx_spi *hw = to_hw(spi);
|
||||
unsigned int spi_config;
|
||||
|
||||
switch (value) {
|
||||
case BITBANG_CS_INACTIVE:
|
||||
break;
|
||||
|
||||
case BITBANG_CS_ACTIVE:
|
||||
spi_config = SPI_CONFIGURATION_REG;
|
||||
|
||||
if (spi->mode & SPI_CPHA)
|
||||
spi_config |= (0x1 << 13);
|
||||
else
|
||||
spi_config &= ~(0x1 << 13);
|
||||
|
||||
if (spi->mode & SPI_CPOL)
|
||||
spi_config |= (0x1 << 14);
|
||||
else
|
||||
spi_config &= ~(0x1 << 14);
|
||||
|
||||
/* write new configration */
|
||||
SPI_CONFIGURATION_REG = spi_config;
|
||||
|
||||
SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
|
||||
SPI_TRANSMIT_CONTROL_REG |= (spi->chip_select & 0x3);
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int cns3xxx_spi_setup(struct spi_device *spi)
|
||||
{
|
||||
if (!spi->bits_per_word)
|
||||
spi->bits_per_word = 8;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
||||
{
|
||||
struct cns3xxx_spi *hw = to_hw(spi);
|
||||
|
||||
dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", t->tx_buf, t->rx_buf,
|
||||
t->len);
|
||||
|
||||
hw->tx = t->tx_buf;
|
||||
hw->rx = t->rx_buf;
|
||||
hw->len = t->len;
|
||||
hw->count = 0;
|
||||
hw->last_in_message_list = t->last_in_message_list;
|
||||
|
||||
init_completion(&hw->done);
|
||||
|
||||
if (hw->tx) {
|
||||
int i;
|
||||
u32 rx_data;
|
||||
for (i = 0; i < (hw->len - 1); i++) {
|
||||
dev_dbg(&spi->dev,
|
||||
"[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i,
|
||||
hw->tx[i]);
|
||||
cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
|
||||
&rx_data);
|
||||
if (hw->rx) {
|
||||
hw->rx[i] = rx_data;
|
||||
dev_dbg(&spi->dev,
|
||||
"[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
|
||||
i, hw->rx[i]);
|
||||
}
|
||||
}
|
||||
|
||||
if (t->last_in_message_list) {
|
||||
cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, hw->tx[i],
|
||||
&rx_data);
|
||||
if (hw->rx) {
|
||||
hw->rx[i] = rx_data;
|
||||
dev_dbg(&spi->dev,
|
||||
"[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
|
||||
i, hw->rx[i]);
|
||||
}
|
||||
} else {
|
||||
cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
|
||||
&rx_data);
|
||||
}
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (hw->rx) {
|
||||
int i;
|
||||
u32 rx_data;
|
||||
for (i = 0; i < (hw->len - 1); i++) {
|
||||
cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
|
||||
hw->rx[i] = rx_data;
|
||||
dev_dbg(&spi->dev,
|
||||
"[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i,
|
||||
hw->rx[i]);
|
||||
}
|
||||
|
||||
if (t->last_in_message_list) {
|
||||
cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, 0xff, &rx_data);
|
||||
} else {
|
||||
cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
|
||||
}
|
||||
hw->rx[i] = rx_data;
|
||||
dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
|
||||
i, hw->rx[i]);
|
||||
}
|
||||
done:
|
||||
return hw->len;
|
||||
}
|
||||
|
||||
static void __init cns3xxx_spi_initial(struct cns3xxx_spi *hw)
|
||||
{
|
||||
SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) | /* 8bits shift length */
|
||||
(0x0 << 9) | /* SPI mode */
|
||||
(0x0 << 10) | /* disable FIFO */
|
||||
(0x1 << 11) | /* SPI master mode */
|
||||
(0x0 << 12) | /* disable SPI loopback mode */
|
||||
(0x1 << 13) | /* clock phase */
|
||||
(0x1 << 14) | /* clock polarity */
|
||||
(0x0 << 24) | /* disable - SPI data swap */
|
||||
(0x1 << 29) | /* enable - 2IO Read mode */
|
||||
(0x0 << 30) | /* disable - SPI high speed read for system boot up */
|
||||
(0x0 << 31)); /* disable - SPI */
|
||||
|
||||
/* Set SPI bit rate PCLK/2 */
|
||||
SPI_BIT_RATE_CONTROL_REG = 0x1;
|
||||
|
||||
/* Set SPI Tx channel 0 */
|
||||
SPI_TRANSMIT_CONTROL_REG = 0x0;
|
||||
|
||||
/* Set Tx FIFO Threshold, Tx FIFO has 2 words */
|
||||
SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4);
|
||||
SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4);
|
||||
|
||||
/* Set Rx FIFO Threshold, Rx FIFO has 2 words */
|
||||
SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4);
|
||||
SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4);
|
||||
|
||||
/* Disable all interrupt */
|
||||
SPI_INTERRUPT_ENABLE_REG = 0x0;
|
||||
|
||||
/* Clear spurious interrupt sources */
|
||||
SPI_INTERRUPT_STATUS_REG = (0x0F << 4);
|
||||
|
||||
/* Enable SPI */
|
||||
SPI_CONFIGURATION_REG |= (0x1 << 31);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int cns3xxx_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct cns3xxx_spi *hw;
|
||||
struct resource *res;
|
||||
int err = 0;
|
||||
|
||||
printk("%s: setup CNS3XXX SPI Controller\n", __FUNCTION__);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -ENODEV;
|
||||
|
||||
/* Allocate master with space for cns3xxx_spi */
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi));
|
||||
if (master == NULL) {
|
||||
dev_err(&pdev->dev, "No memory for spi_master\n");
|
||||
err = -ENOMEM;
|
||||
goto err_nomem;
|
||||
}
|
||||
|
||||
hw = spi_master_get_devdata(master);
|
||||
memset(hw, 0, sizeof(struct cns3xxx_spi));
|
||||
|
||||
hw->master = spi_master_get(master);
|
||||
hw->dev = &pdev->dev;
|
||||
|
||||
hw->base = devm_ioremap_resource(hw->dev, res);
|
||||
if (IS_ERR(hw->base)) {
|
||||
dev_err(hw->dev, "Unable to map registers\n");
|
||||
err = PTR_ERR(hw->base);
|
||||
goto err_register;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, hw);
|
||||
init_completion(&hw->done);
|
||||
|
||||
/* setup the master state. */
|
||||
|
||||
master->num_chipselect = 4;
|
||||
master->bus_num = 1;
|
||||
|
||||
/* setup the state for the bitbang driver */
|
||||
|
||||
hw->bitbang.master = hw->master;
|
||||
hw->bitbang.setup_transfer = cns3xxx_spi_setup_transfer;
|
||||
hw->bitbang.chipselect = cns3xxx_spi_chipselect;
|
||||
hw->bitbang.txrx_bufs = cns3xxx_spi_txrx;
|
||||
hw->bitbang.master->setup = cns3xxx_spi_setup;
|
||||
|
||||
dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
|
||||
|
||||
/* SPI controller initializations */
|
||||
cns3xxx_spi_initial(hw);
|
||||
|
||||
/* register SPI controller */
|
||||
|
||||
err = spi_bitbang_start(&hw->bitbang);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to register SPI master\n");
|
||||
goto err_register;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_register:
|
||||
spi_master_put(hw->master);;
|
||||
|
||||
err_nomem:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cns3xxx_spi_remove(struct platform_device *dev)
|
||||
{
|
||||
struct cns3xxx_spi *hw = platform_get_drvdata(dev);
|
||||
|
||||
platform_set_drvdata(dev, NULL);
|
||||
|
||||
spi_unregister_master(hw->master);
|
||||
|
||||
spi_master_put(hw->master);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int cns3xxx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
|
||||
{
|
||||
struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cns3xxx_spi_resume(struct platform_device *pdev)
|
||||
{
|
||||
struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
#define cns3xxx_spi_suspend NULL
|
||||
#define cns3xxx_spi_resume NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver cns3xxx_spi_driver = {
|
||||
.probe = cns3xxx_spi_probe,
|
||||
.remove = cns3xxx_spi_remove,
|
||||
.suspend = cns3xxx_spi_suspend,
|
||||
.resume = cns3xxx_spi_resume,
|
||||
.driver = {
|
||||
.name = "cns3xxx_spi",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init cns3xxx_spi_init(void)
|
||||
{
|
||||
return platform_driver_register(&cns3xxx_spi_driver);
|
||||
}
|
||||
|
||||
static void __exit cns3xxx_spi_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&cns3xxx_spi_driver);
|
||||
}
|
||||
|
||||
module_init(cns3xxx_spi_init);
|
||||
module_exit(cns3xxx_spi_exit);
|
||||
|
||||
MODULE_AUTHOR("Cavium Networks");
|
||||
MODULE_DESCRIPTION("CNS3XXX SPI Controller Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:cns3xxx_spi");
|
||||
|
||||
EXPORT_SYMBOL_GPL(cns3xxx_spi_tx_rx);
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-cns3xxx/include/mach/platform.h
|
||||
*
|
||||
* Copyright 2011 Gateworks Corporation
|
||||
* Chris Lang <clang@gateworks.com
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_PLATFORM_H
|
||||
#define __ASM_ARCH_PLATFORM_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* Information about built-in Ethernet MAC interfaces */
|
||||
struct cns3xxx_plat_info {
|
||||
u8 ports; /* Bitmap of enabled Ports */
|
||||
u8 hwaddr[4][6];
|
||||
u32 phy[3];
|
||||
};
|
||||
|
||||
#endif /* __ASM_ARCH_PLATFORM_H */
|
||||
#endif
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2010-2012 OpenWrt.org
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
define Image/Prepare
|
||||
mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -e 0x20008000 -n '$(VERSION_DIST) Linux-$(LINUX_VERSION)' -d $(KDIR)/zImage $(KDIR)/uImage
|
||||
endef
|
||||
|
||||
LEGACY_NOR_KERNEL_SIZE = 2048k
|
||||
LEGACY_SPI_KERNEL_SIZE = 1536k
|
||||
|
||||
# Build sysupgrade image
|
||||
define BuildFirmware/Legacy
|
||||
dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin \
|
||||
of=$(KDIR)/uImage.pad bs=$(3) count=1
|
||||
dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin \
|
||||
of=$(KDIR)/root.$(1).pad bs=$(3) skip=1
|
||||
sh $(TOPDIR)/scripts/combined-image.sh \
|
||||
$(KDIR)/uImage.pad \
|
||||
$(KDIR)/root.$(1).pad \
|
||||
$(BIN_DIR)/$(IMG_PREFIX)-$(1)-$(2)-legacy-sysupgrade.bin
|
||||
endef
|
||||
|
||||
define Image/BuildKernel/Initramfs
|
||||
mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -e 0x20008000 -n '$(VERSION_DIST) Linux-$(LINUX_VERSION)' -d $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-initramfs-uImage
|
||||
endef
|
||||
|
||||
define Image/Build
|
||||
cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin
|
||||
$(call Image/Build/$(1),$(1))
|
||||
$(call BuildFirmware/Legacy,$(1),laguna_spi,$(LEGACY_SPI_KERNEL_SIZE))
|
||||
$(call BuildFirmware/Legacy,$(1),laguna_nor,$(LEGACY_NOR_KERNEL_SIZE))
|
||||
endef
|
||||
|
||||
define Image/Build/squashfs
|
||||
$(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin)
|
||||
endef
|
||||
|
||||
$(eval $(call BuildImage))
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -1,4 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
+
|
||||
obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
|
||||
cns3xxx-y += core.o pm.o
|
||||
cns3xxx-$(CONFIG_ATAGS) += devices.o
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
--- a/arch/arm/tools/mach-types
|
||||
+++ b/arch/arm/tools/mach-types
|
||||
@@ -449,6 +449,7 @@ gplugd MACH_GPLUGD GPLUGD 2625
|
||||
qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627
|
||||
mx23evk MACH_MX23EVK MX23EVK 2629
|
||||
ap4evb MACH_AP4EVB AP4EVB 2630
|
||||
+gw2388 MACH_GW2388 GW2388 2635
|
||||
mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650
|
||||
guruplug MACH_GURUPLUG GURUPLUG 2659
|
||||
spear310 MACH_SPEAR310 SPEAR310 2660
|
||||
|
|
@ -1,80 +0,0 @@
|
|||
--- a/arch/arm/include/asm/glue-cache.h
|
||||
+++ b/arch/arm/include/asm/glue-cache.h
|
||||
@@ -156,9 +156,15 @@ static inline void nop_dma_unmap_area(co
|
||||
#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
|
||||
#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
|
||||
#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
|
||||
-#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
|
||||
|
||||
-#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
|
||||
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
|
||||
+# define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
|
||||
+# define dmac_flush_range __glue(_CACHE,_dma_flush_range)
|
||||
+#else
|
||||
+# define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area)
|
||||
+# define dmac_flush_range __glue(fiq,_dma_flush_range)
|
||||
+#endif
|
||||
+
|
||||
#endif
|
||||
|
||||
#endif
|
||||
--- a/arch/arm/mm/Kconfig
|
||||
+++ b/arch/arm/mm/Kconfig
|
||||
@@ -916,6 +916,17 @@ config DMA_CACHE_RWFO
|
||||
in hardware, other workarounds are needed (e.g. cache
|
||||
maintenance broadcasting in software via FIQ).
|
||||
|
||||
+config DMA_CACHE_FIQ_BROADCAST
|
||||
+ bool "Enable fiq broadcast DMA cache maintenance"
|
||||
+ depends on CPU_V6K && SMP
|
||||
+ select FIQ
|
||||
+ help
|
||||
+ The Snoop Control Unit on ARM11MPCore does not detect the
|
||||
+ cache maintenance operations and the dma_{map,unmap}_area()
|
||||
+ functions may leave stale cache entries on other CPUs. By
|
||||
+ enabling this option, fiq broadcast in the ARMv6
|
||||
+ DMA cache maintenance functions is performed.
|
||||
+
|
||||
config OUTER_CACHE
|
||||
bool
|
||||
|
||||
--- a/arch/arm/mm/flush.c
|
||||
+++ b/arch/arm/mm/flush.c
|
||||
@@ -319,6 +319,7 @@ void __sync_icache_dcache(pte_t pteval)
|
||||
void flush_dcache_page(struct page *page)
|
||||
{
|
||||
struct address_space *mapping;
|
||||
+ bool skip_broadcast = true;
|
||||
|
||||
/*
|
||||
* The zero page is never written to, so never has any dirty
|
||||
@@ -335,7 +336,10 @@ void flush_dcache_page(struct page *page
|
||||
|
||||
mapping = page_mapping_file(page);
|
||||
|
||||
- if (!cache_ops_need_broadcast() &&
|
||||
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
|
||||
+ skip_broadcast = !cache_ops_need_broadcast();
|
||||
+#endif
|
||||
+ if (skip_broadcast &&
|
||||
mapping && !page_mapcount(page))
|
||||
clear_bit(PG_dcache_clean, &page->flags);
|
||||
else {
|
||||
--- a/arch/arm/mm/dma.h
|
||||
+++ b/arch/arm/mm/dma.h
|
||||
@@ -5,8 +5,13 @@
|
||||
#include <asm/glue-cache.h>
|
||||
|
||||
#ifndef MULTI_CACHE
|
||||
-#define dmac_map_area __glue(_CACHE,_dma_map_area)
|
||||
-#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
|
||||
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
|
||||
+# define dmac_map_area __glue(_CACHE,_dma_map_area)
|
||||
+# define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
|
||||
+#else
|
||||
+# define dmac_map_area __glue(fiq,_dma_map_area)
|
||||
+# define dmac_unmap_area __glue(fiq,_dma_unmap_area)
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* These are private to the dma-mapping API. Do not use directly.
|
||||
|
|
@ -1,184 +0,0 @@
|
|||
Add a watchdog driver for ARM MPcore processors.
|
||||
|
||||
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||
--- a/drivers/watchdog/Kconfig
|
||||
+++ b/drivers/watchdog/Kconfig
|
||||
@@ -375,6 +375,13 @@ config KS8695_WATCHDOG
|
||||
Watchdog timer embedded into KS8695 processor. This will reboot your
|
||||
system when the timeout is reached.
|
||||
|
||||
+config MPCORE_WATCHDOG
|
||||
+ tristate "MPcore watchdog"
|
||||
+ depends on HAVE_ARM_TWD
|
||||
+ select WATCHDOG_CORE
|
||||
+ help
|
||||
+ Watchdog timer embedded into the MPcore system
|
||||
+
|
||||
config HAVE_S3C2410_WATCHDOG
|
||||
bool
|
||||
help
|
||||
--- a/drivers/watchdog/Makefile
|
||||
+++ b/drivers/watchdog/Makefile
|
||||
@@ -49,6 +49,7 @@ obj-$(CONFIG_977_WATCHDOG) += wdt977.o
|
||||
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
|
||||
obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
|
||||
obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
|
||||
+obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
|
||||
obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o
|
||||
obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
|
||||
obj-$(CONFIG_SAMA5D4_WATCHDOG) += sama5d4_wdt.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/watchdog/mpcore_wdt.c
|
||||
@@ -0,0 +1,118 @@
|
||||
+/*
|
||||
+ * Watchdog driver for ARM MPcore
|
||||
+ *
|
||||
+ * Copyright (C) 2017 Felix Fietkau <nbd@nbd.name>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/export.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/watchdog.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <asm/smp_twd.h>
|
||||
+
|
||||
+static void __iomem *wdt_base;
|
||||
+static int wdt_timeout = 60;
|
||||
+
|
||||
+static int mpcore_wdt_keepalive(struct watchdog_device *wdd)
|
||||
+{
|
||||
+ static int perturb;
|
||||
+ u32 count;
|
||||
+
|
||||
+ count = (twd_timer_get_rate() / 256) * wdt_timeout;
|
||||
+
|
||||
+ /* Reload register needs a different value on each refresh */
|
||||
+ count += perturb;
|
||||
+ perturb = !perturb;
|
||||
+
|
||||
+ iowrite32(count, wdt_base + TWD_WDOG_LOAD);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mpcore_wdt_start(struct watchdog_device *wdd)
|
||||
+{
|
||||
+ mpcore_wdt_keepalive(wdd);
|
||||
+
|
||||
+ /* prescale = 256, mode = 1, enable = 1 */
|
||||
+ iowrite32(0x0000FF09, wdt_base + TWD_WDOG_CONTROL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mpcore_wdt_stop(struct watchdog_device *wdd)
|
||||
+{
|
||||
+ iowrite32(0x12345678, wdt_base + TWD_WDOG_DISABLE);
|
||||
+ iowrite32(0x87654321, wdt_base + TWD_WDOG_DISABLE);
|
||||
+ iowrite32(0x0, wdt_base + TWD_WDOG_CONTROL);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mpcore_wdt_set_timeout(struct watchdog_device *wdd,
|
||||
+ unsigned int timeout)
|
||||
+{
|
||||
+ mpcore_wdt_stop(wdd);
|
||||
+ wdt_timeout = timeout;
|
||||
+ mpcore_wdt_start(wdd);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct watchdog_info mpcore_wdt_info = {
|
||||
+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
|
||||
+ .identity = "MPcore Watchdog",
|
||||
+};
|
||||
+
|
||||
+static const struct watchdog_ops mpcore_wdt_ops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .start = mpcore_wdt_start,
|
||||
+ .stop = mpcore_wdt_stop,
|
||||
+ .ping = mpcore_wdt_keepalive,
|
||||
+ .set_timeout = mpcore_wdt_set_timeout,
|
||||
+};
|
||||
+
|
||||
+static struct watchdog_device mpcore_wdt = {
|
||||
+ .info = &mpcore_wdt_info,
|
||||
+ .ops = &mpcore_wdt_ops,
|
||||
+ .min_timeout = 1,
|
||||
+ .max_timeout = 65535,
|
||||
+};
|
||||
+
|
||||
+static int mpcore_wdt_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+ unsigned long rate = twd_timer_get_rate();
|
||||
+
|
||||
+ pr_info("MPCore WD init. clockrate: %lu prescaler: %u countrate: %lu timeout: %us\n", rate, 256, rate / 256, wdt_timeout);
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (!res)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ wdt_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(wdt_base))
|
||||
+ return PTR_ERR(wdt_base);
|
||||
+
|
||||
+ watchdog_register_device(&mpcore_wdt);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mpcore_wdt_remove(struct platform_device *dev)
|
||||
+{
|
||||
+ watchdog_unregister_device(&mpcore_wdt);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver mpcore_wdt_driver = {
|
||||
+ .probe = mpcore_wdt_probe,
|
||||
+ .remove = mpcore_wdt_remove,
|
||||
+ .driver = {
|
||||
+ .name = "mpcore_wdt",
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(mpcore_wdt_driver);
|
||||
+MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- a/arch/arm/include/asm/smp_twd.h
|
||||
+++ b/arch/arm/include/asm/smp_twd.h
|
||||
@@ -34,5 +34,6 @@ struct twd_local_timer name __initdata =
|
||||
};
|
||||
|
||||
int twd_local_timer_register(struct twd_local_timer *);
|
||||
+unsigned long twd_timer_get_rate(void);
|
||||
|
||||
#endif
|
||||
--- a/arch/arm/kernel/smp_twd.c
|
||||
+++ b/arch/arm/kernel/smp_twd.c
|
||||
@@ -15,6 +15,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
+#include <linux/export.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/clockchips.h>
|
||||
@@ -380,6 +381,14 @@ int __init twd_local_timer_register(stru
|
||||
return twd_local_timer_common_register(NULL);
|
||||
}
|
||||
|
||||
+/* Needed by mpcore_wdt */
|
||||
+unsigned long twd_timer_get_rate(void)
|
||||
+{
|
||||
+ return twd_timer_rate;
|
||||
+}
|
||||
+EXPORT_SYMBOL_GPL(twd_timer_get_rate);
|
||||
+
|
||||
+
|
||||
#ifdef CONFIG_OF
|
||||
static int __init twd_local_timer_of_register(struct device_node *np)
|
||||
{
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -6,3 +6,5 @@ cns3xxx-y += core.o pm.o
|
||||
cns3xxx-$(CONFIG_ATAGS) += devices.o
|
||||
cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
+cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -3,6 +3,9 @@ menuconfig ARCH_CNS3XXX
|
||||
bool "Cavium Networks CNS3XXX family"
|
||||
depends on ARCH_MULTI_V6
|
||||
select ARM_GIC
|
||||
+ select HAVE_ARM_SCU if SMP
|
||||
+ select HAVE_ARM_TWD
|
||||
+ select HAVE_SMP
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -13,6 +13,7 @@
|
||||
|
||||
#include <linux/reboot.h>
|
||||
|
||||
+extern struct smp_operations cns3xxx_smp_ops;
|
||||
extern void cns3xxx_timer_init(void);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -281,8 +281,6 @@ void __init cns3xxx_pcie_init_late(void)
|
||||
"imprecise external abort");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
|
||||
- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
|
||||
- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
|
||||
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
|
||||
cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
|
||||
private_data = &cns3xxx_pcie[i];
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -6,6 +6,7 @@ menuconfig ARCH_CNS3XXX
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD
|
||||
select HAVE_SMP
|
||||
+ select FIQ
|
||||
help
|
||||
Support for Cavium Networks CNS3XXX platform.
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -6,5 +6,5 @@ cns3xxx-y += core.o pm.o
|
||||
cns3xxx-$(CONFIG_ATAGS) += devices.o
|
||||
cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
-cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
+cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
|
||||
cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
@@ -261,6 +261,7 @@
|
||||
#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
|
||||
#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
|
||||
|
||||
+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
|
||||
/*
|
||||
* Power management and clock control
|
||||
*/
|
||||
--- a/arch/arm/mm/Kconfig
|
||||
+++ b/arch/arm/mm/Kconfig
|
||||
@@ -899,7 +899,7 @@ config VDSO
|
||||
|
||||
config DMA_CACHE_RWFO
|
||||
bool "Enable read/write for ownership DMA cache maintenance"
|
||||
- depends on CPU_V6K && SMP
|
||||
+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
|
||||
default y
|
||||
help
|
||||
The Snoop Control Unit on ARM11MPCore does not detect the
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -17,6 +17,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
+#include <asm/smp_twd.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
@@ -26,6 +27,8 @@
|
||||
#include "core.h"
|
||||
#include "pm.h"
|
||||
|
||||
+#define IRQ_LOCALTIMER 29
|
||||
+
|
||||
static struct map_desc cns3xxx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
|
||||
@@ -198,6 +201,15 @@ static struct irqaction cns3xxx_timer_ir
|
||||
.handler = cns3xxx_timer_interrupt,
|
||||
};
|
||||
|
||||
+static void __init cns3xxx_init_twd(void)
|
||||
+{
|
||||
+ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer,
|
||||
+ CNS3XXX_TC11MP_TWD_BASE,
|
||||
+ IRQ_LOCALTIMER);
|
||||
+
|
||||
+ twd_local_timer_register(&cns3xx_twd_local_timer);
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Set up the clock source and clock events devices
|
||||
*/
|
||||
@@ -251,6 +263,7 @@ static void __init __cns3xxx_timer_init(
|
||||
setup_irq(timer_irq, &cns3xxx_timer_irq);
|
||||
|
||||
cns3xxx_clockevents_init(timer_irq);
|
||||
+ cns3xxx_init_twd();
|
||||
}
|
||||
|
||||
void __init cns3xxx_timer_init(void)
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -81,6 +81,16 @@ static struct map_desc cns3xxx_io_desc[]
|
||||
.pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
|
||||
+ .length = SZ_16M,
|
||||
+ .type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
|
||||
+ .length = SZ_16M,
|
||||
+ .type = MT_DEVICE,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
|
@ -1,109 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus
|
||||
return base + where + (devfn << 12);
|
||||
}
|
||||
|
||||
+static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
|
||||
+{
|
||||
+ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
|
||||
+
|
||||
+ /* check PCI-compatible status register after access */
|
||||
+ if (cnspci->linked) {
|
||||
+ void __iomem *host_base;
|
||||
+ u32 sreg, ereg;
|
||||
+
|
||||
+ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
|
||||
+ sreg = __raw_readw(host_base + 0x6) & 0xF900;
|
||||
+ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
|
||||
+
|
||||
+ if (sreg | ereg) {
|
||||
+ /* SREG:
|
||||
+ * BIT15 - Detected Parity Error
|
||||
+ * BIT14 - Signaled System Error
|
||||
+ * BIT13 - Received Master Abort
|
||||
+ * BIT12 - Received Target Abort
|
||||
+ * BIT11 - Signaled Target Abort
|
||||
+ * BIT08 - Master Data Parity Error
|
||||
+ *
|
||||
+ * EREG:
|
||||
+ * BIT20 - Unsupported Request
|
||||
+ * BIT19 - ECRC
|
||||
+ * BIT18 - Malformed TLP
|
||||
+ * BIT17 - Receiver Overflow
|
||||
+ * BIT16 - Unexpected Completion
|
||||
+ * BIT15 - Completer Abort
|
||||
+ * BIT14 - Completion Timeout
|
||||
+ * BIT13 - Flow Control Protocol Error
|
||||
+ * BIT12 - Poisoned TLP
|
||||
+ * BIT04 - Data Link Protocol Error
|
||||
+ *
|
||||
+ * TODO: see Documentation/pci-error-recovery.txt
|
||||
+ * implement error_detected handler
|
||||
+ */
|
||||
+/*
|
||||
+ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg);
|
||||
+ if (sreg & BIT(15)) printk(" <PERR");
|
||||
+ if (sreg & BIT(14)) printk(" >SERR");
|
||||
+ if (sreg & BIT(13)) printk(" <MABRT");
|
||||
+ if (sreg & BIT(12)) printk(" <TABRT");
|
||||
+ if (sreg & BIT(11)) printk(" >TABRT");
|
||||
+ if (sreg & BIT( 8)) printk(" MPERR");
|
||||
+
|
||||
+ if (ereg & BIT(20)) printk(" Unsup");
|
||||
+ if (ereg & BIT(19)) printk(" ECRC");
|
||||
+ if (ereg & BIT(18)) printk(" MTLP");
|
||||
+ if (ereg & BIT(17)) printk(" OFLOW");
|
||||
+ if (ereg & BIT(16)) printk(" Unex");
|
||||
+ if (ereg & BIT(15)) printk(" ABRT");
|
||||
+ if (ereg & BIT(14)) printk(" COMPTO");
|
||||
+ if (ereg & BIT(13)) printk(" FLOW");
|
||||
+ if (ereg & BIT(12)) printk(" PTLP");
|
||||
+ if (ereg & BIT( 4)) printk(" DLINK");
|
||||
+ printk("\n");
|
||||
+*/
|
||||
+ pr_debug("%s failed port%d sreg=0x%04x\n", __func__,
|
||||
+ pci_domain_nr(bus), sreg);
|
||||
+
|
||||
+ /* make sure the status bits are reset */
|
||||
+ __raw_writew(sreg, host_base + 6);
|
||||
+ __raw_writel(ereg, host_base + 0x104);
|
||||
+ return 1;
|
||||
+ }
|
||||
+ }
|
||||
+ else
|
||||
+ return 1;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 *val)
|
||||
{
|
||||
@@ -95,6 +168,11 @@ static int cns3xxx_pci_read_config(struc
|
||||
|
||||
ret = pci_generic_config_read(bus, devfn, where, size, val);
|
||||
|
||||
+ if (check_master_abort(bus, devfn, where)) {
|
||||
+ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+ }
|
||||
+
|
||||
if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
|
||||
(where & 0xffc) == PCI_CLASS_REVISION)
|
||||
/*
|
||||
@@ -257,8 +335,14 @@ static void __init cns3xxx_pcie_hw_init(
|
||||
static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
+#if 0
|
||||
+/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE
|
||||
+ * ignore imprecise aborts and use PCI-compatible Status register to
|
||||
+ * determine errors instead
|
||||
+ */
|
||||
if (fsr & (1 << 10))
|
||||
regs->ARM_pc += 4;
|
||||
+#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -366,6 +366,8 @@ void __init cns3xxx_pcie_init_late(void)
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
|
||||
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
|
||||
+ if (!cns3xxx_pcie[i].linked)
|
||||
+ continue;
|
||||
cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
|
||||
private_data = &cns3xxx_pcie[i];
|
||||
pci_common_init(&hw_pci);
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
--- a/drivers/i2c/busses/Kconfig
|
||||
+++ b/drivers/i2c/busses/Kconfig
|
||||
@@ -460,6 +460,18 @@ config I2C_CBUS_GPIO
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called i2c-cbus-gpio.
|
||||
|
||||
+config I2C_CNS3XXX
|
||||
+ tristate "Cavium CNS3xxx I2C driver"
|
||||
+ depends on ARCH_CNS3XXX
|
||||
+ help
|
||||
+ Support for Cavium CNS3xxx I2C controller driver.
|
||||
+
|
||||
+ This driver can also be built as a module. If so, the module
|
||||
+ will be called i2c-cns3xxx.
|
||||
+
|
||||
+ Please note that this driver might be needed to bring up other
|
||||
+ devices such as Cavium CNS3xxx Ethernet.
|
||||
+
|
||||
config I2C_CPM
|
||||
tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
|
||||
depends on CPM1 || CPM2
|
||||
--- a/drivers/i2c/busses/Makefile
|
||||
+++ b/drivers/i2c/busses/Makefile
|
||||
@@ -131,6 +131,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-vipe
|
||||
obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o
|
||||
obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
|
||||
obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o
|
||||
+obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o
|
||||
obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o
|
||||
obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
|
||||
obj-$(CONFIG_I2C_MLXCPLD) += i2c-mlxcpld.o
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
--- a/drivers/spi/Kconfig
|
||||
+++ b/drivers/spi/Kconfig
|
||||
@@ -181,6 +181,13 @@ config SPI_CLPS711X
|
||||
This enables dedicated general purpose SPI/Microwire1-compatible
|
||||
master mode interface (SSI1) for CLPS711X-based CPUs.
|
||||
|
||||
+config SPI_CNS3XXX
|
||||
+ tristate "CNS3XXX SPI controller"
|
||||
+ depends on ARCH_CNS3XXX && SPI_MASTER
|
||||
+ select SPI_BITBANG
|
||||
+ help
|
||||
+ This enables using the CNS3XXX SPI controller in master mode.
|
||||
+
|
||||
config SPI_COLDFIRE_QSPI
|
||||
tristate "Freescale Coldfire QSPI controller"
|
||||
depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
|
||||
--- a/drivers/spi/Makefile
|
||||
+++ b/drivers/spi/Makefile
|
||||
@@ -28,6 +28,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi-bitban
|
||||
obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
|
||||
obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o
|
||||
obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
|
||||
+obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o
|
||||
obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
|
||||
obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
|
||||
obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
|
||||
--- a/include/linux/spi/spi.h
|
||||
+++ b/include/linux/spi/spi.h
|
||||
@@ -795,6 +795,10 @@ struct spi_transfer {
|
||||
u32 speed_hz;
|
||||
|
||||
struct list_head transfer_list;
|
||||
+
|
||||
+#ifdef CONFIG_ARCH_CNS3XXX
|
||||
+ unsigned last_in_message_list;
|
||||
+#endif
|
||||
};
|
||||
|
||||
/**
|
||||
--- a/drivers/spi/spi.c
|
||||
+++ b/drivers/spi/spi.c
|
||||
@@ -1020,6 +1020,9 @@ static int spi_transfer_one_message(stru
|
||||
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
||||
trace_spi_transfer_start(msg, xfer);
|
||||
|
||||
+ xfer->last_in_message_list =
|
||||
+ list_is_last(&xfer->transfer_list, &msg->transfers);
|
||||
+
|
||||
spi_statistics_add_transfer_stats(statm, xfer, ctlr);
|
||||
spi_statistics_add_transfer_stats(stats, xfer, ctlr);
|
||||
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
--- a/drivers/ata/ahci_platform.c
|
||||
+++ b/drivers/ata/ahci_platform.c
|
||||
@@ -44,11 +44,18 @@ static struct scsi_host_template ahci_pl
|
||||
AHCI_SHT(DRV_NAME),
|
||||
};
|
||||
|
||||
+static const struct ata_port_info cns3xxx_port_info = {
|
||||
+ .flags = AHCI_FLAG_COMMON,
|
||||
+ .pio_mask = ATA_PIO4,
|
||||
+ .udma_mask = ATA_UDMA6,
|
||||
+ .port_ops = &ahci_pmp_retry_srst_ops,
|
||||
+};
|
||||
+
|
||||
static int ahci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct ahci_host_priv *hpriv;
|
||||
- const struct ata_port_info *port;
|
||||
+ const struct ata_port_info *port = &ahci_port_info;
|
||||
int rc;
|
||||
|
||||
hpriv = ahci_platform_get_resources(pdev,
|
||||
@@ -66,9 +73,14 @@ static int ahci_probe(struct platform_de
|
||||
if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
|
||||
hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
|
||||
|
||||
- port = acpi_device_get_match_data(dev);
|
||||
- if (!port)
|
||||
- port = &ahci_port_info;
|
||||
+ if (IS_ENABLED(CONFIG_ARCH_CNS3XXX)) {
|
||||
+ port = &cns3xxx_port_info;
|
||||
+ }
|
||||
+ else {
|
||||
+ port = acpi_device_get_match_data(dev);
|
||||
+ if (!port)
|
||||
+ port = &ahci_port_info;
|
||||
+ }
|
||||
|
||||
rc = ahci_platform_init_host(pdev, hpriv, port,
|
||||
&ahci_platform_sht);
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -138,6 +138,7 @@ static int cns3xxx_set_oneshot(struct cl
|
||||
|
||||
/* period set, and timer enabled in 'next_event' hook */
|
||||
ctrl |= (1 << 2) | (1 << 9);
|
||||
+ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
|
||||
writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
return 0;
|
||||
}
|
||||
@@ -148,7 +149,7 @@ static int cns3xxx_set_periodic(struct c
|
||||
int pclk = cns3xxx_cpu_clock() / 8;
|
||||
int reload;
|
||||
|
||||
- reload = pclk * 20 / (3 * HZ) * 0x25000;
|
||||
+ reload = pclk * 1000000 / HZ;
|
||||
writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
|
||||
ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
|
||||
writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
@@ -175,8 +176,8 @@ static struct clock_event_device cns3xxx
|
||||
.set_state_oneshot = cns3xxx_set_oneshot,
|
||||
.tick_resume = cns3xxx_shutdown,
|
||||
.set_next_event = cns3xxx_timer_set_next_event,
|
||||
- .rating = 350,
|
||||
- .cpumask = cpu_all_mask,
|
||||
+ .rating = 300,
|
||||
+ .cpumask = cpu_possible_mask,
|
||||
};
|
||||
|
||||
static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
|
||||
@@ -220,6 +221,32 @@ static void __init cns3xxx_init_twd(void
|
||||
twd_local_timer_register(&cns3xx_twd_local_timer);
|
||||
}
|
||||
|
||||
+static u64 cns3xxx_get_cycles(struct clocksource *cs)
|
||||
+{
|
||||
+ u64 val;
|
||||
+
|
||||
+ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
|
||||
+ val &= 0xffff;
|
||||
+
|
||||
+ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET));
|
||||
+}
|
||||
+
|
||||
+static struct clocksource clocksource_cns3xxx = {
|
||||
+ .name = "freerun",
|
||||
+ .rating = 200,
|
||||
+ .read = cns3xxx_get_cycles,
|
||||
+ .mask = CLOCKSOURCE_MASK(48),
|
||||
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
+};
|
||||
+
|
||||
+static void __init cns3xxx_clocksource_init(void)
|
||||
+{
|
||||
+ /* Reset the FreeRunning counter */
|
||||
+ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
|
||||
+
|
||||
+ clocksource_register_khz(&clocksource_cns3xxx, 100);
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Set up the clock source and clock events devices
|
||||
*/
|
||||
@@ -237,13 +264,12 @@ static void __init __cns3xxx_timer_init(
|
||||
/* stop free running timer3 */
|
||||
writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
|
||||
|
||||
- /* timer1 */
|
||||
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
|
||||
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
|
||||
-
|
||||
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
|
||||
writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
|
||||
|
||||
+ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
|
||||
+ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
|
||||
+
|
||||
/* mask irq, non-mask timer1 overflow */
|
||||
irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
|
||||
irq_mask &= ~(1 << 2);
|
||||
@@ -255,23 +281,9 @@ static void __init __cns3xxx_timer_init(
|
||||
val |= (1 << 9);
|
||||
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
|
||||
- /* timer2 */
|
||||
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
|
||||
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
|
||||
-
|
||||
- /* mask irq */
|
||||
- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
|
||||
- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
|
||||
- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
|
||||
-
|
||||
- /* down counter */
|
||||
- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
- val |= (1 << 10);
|
||||
- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
|
||||
-
|
||||
- /* Make irqs happen for the system timer */
|
||||
setup_irq(timer_irq, &cns3xxx_timer_irq);
|
||||
|
||||
+ cns3xxx_clocksource_init();
|
||||
cns3xxx_clockevents_init(timer_irq);
|
||||
cns3xxx_init_twd();
|
||||
}
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
@@ -162,11 +162,13 @@
|
||||
#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
|
||||
|
||||
#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
|
||||
+#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
|
||||
|
||||
#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
|
||||
#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
|
||||
|
||||
#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
|
||||
+#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
|
||||
|
||||
#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
|
||||
#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
|
||||
@@ -175,13 +177,16 @@
|
||||
#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
|
||||
|
||||
#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
|
||||
+#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
|
||||
|
||||
#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
|
||||
+#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
|
||||
|
||||
#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
|
||||
#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
|
||||
|
||||
#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
|
||||
+#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
|
||||
|
||||
#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
|
||||
#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
|
||||
@@ -190,6 +195,7 @@
|
||||
#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
|
||||
|
||||
#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
|
||||
+#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
|
||||
|
||||
/*
|
||||
* Testchip peripheral and fpga gic regions
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
@@ -223,6 +223,10 @@ static void __init cns3420_init(void)
|
||||
|
||||
cns3xxx_ahci_init();
|
||||
cns3xxx_sdhci_init();
|
||||
+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
|
||||
+ NR_IRQS_CNS3XXX);
|
||||
+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
|
||||
+ NR_IRQS_CNS3XXX + 32);
|
||||
|
||||
pm_power_off = cns3xxx_power_off;
|
||||
}
|
||||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -3,6 +3,8 @@ menuconfig ARCH_CNS3XXX
|
||||
bool "Cavium Networks CNS3XXX family"
|
||||
depends on ARCH_MULTI_V6
|
||||
select ARM_GIC
|
||||
+ select ARCH_REQUIRE_GPIOLIB
|
||||
+ select GENERIC_IRQ_CHIP
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD
|
||||
select HAVE_SMP
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -2,7 +2,7 @@
|
||||
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
|
||||
|
||||
obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
|
||||
-cns3xxx-y += core.o pm.o
|
||||
+cns3xxx-y += core.o pm.o gpio.o
|
||||
cns3xxx-$(CONFIG_ATAGS) += devices.o
|
||||
cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
--- a/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
|
||||
@@ -68,8 +68,10 @@
|
||||
#define SMC_PCELL_ID_3_OFFSET 0xFFC
|
||||
|
||||
#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
|
||||
+#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000
|
||||
|
||||
#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
|
||||
+#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000
|
||||
|
||||
#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
|
||||
.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_GPIOA_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
|
||||
+ .length = SZ_4K,
|
||||
+ .type = MT_DEVICE,
|
||||
+ }, {
|
||||
+ .virtual = CNS3XXX_GPIOB_BASE_VIRT,
|
||||
+ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
|
||||
+ .length = SZ_4K,
|
||||
+ .type = MT_DEVICE,
|
||||
#ifdef CONFIG_PCI
|
||||
}, {
|
||||
.virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/core.c
|
||||
+++ b/arch/arm/mach-cns3xxx/core.c
|
||||
@@ -307,13 +307,26 @@ void __init cns3xxx_timer_init(void)
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
|
||||
-void __init cns3xxx_l2x0_init(void)
|
||||
+static int cns3xxx_l2x0_enable = 1;
|
||||
+
|
||||
+static int __init cns3xxx_l2x0_disable(char *s)
|
||||
+{
|
||||
+ cns3xxx_l2x0_enable = 0;
|
||||
+ return 1;
|
||||
+}
|
||||
+__setup("nol2x0", cns3xxx_l2x0_disable);
|
||||
+
|
||||
+static int __init cns3xxx_l2x0_init(void)
|
||||
{
|
||||
- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
|
||||
+ void __iomem *base;
|
||||
u32 val;
|
||||
|
||||
+ if (!cns3xxx_l2x0_enable)
|
||||
+ return 0;
|
||||
+
|
||||
+ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
|
||||
if (WARN_ON(!base))
|
||||
- return;
|
||||
+ return 0;
|
||||
|
||||
/*
|
||||
* Tag RAM Control register
|
||||
@@ -343,7 +356,10 @@ void __init cns3xxx_l2x0_init(void)
|
||||
|
||||
/* 32 KiB, 8-way, parity disable */
|
||||
l2x0_init(base, 0x00500000, 0xfe0f0fff);
|
||||
+
|
||||
+ return 0;
|
||||
}
|
||||
+arch_initcall(cns3xxx_l2x0_init);
|
||||
|
||||
#endif /* CONFIG_CACHE_L2X0 */
|
||||
|
||||
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
||||
@@ -217,8 +217,6 @@ static struct platform_device *cns3420_p
|
||||
|
||||
static void __init cns3420_init(void)
|
||||
{
|
||||
- cns3xxx_l2x0_init();
|
||||
-
|
||||
platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
|
||||
|
||||
cns3xxx_ahci_init();
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -16,12 +16,6 @@
|
||||
extern struct smp_operations cns3xxx_smp_ops;
|
||||
extern void cns3xxx_timer_init(void);
|
||||
|
||||
-#ifdef CONFIG_CACHE_L2X0
|
||||
-void __init cns3xxx_l2x0_init(void);
|
||||
-#else
|
||||
-static inline void cns3xxx_l2x0_init(void) {}
|
||||
-#endif /* CONFIG_CACHE_L2X0 */
|
||||
-
|
||||
#ifdef CONFIG_PCI
|
||||
extern void __init cns3xxx_pcie_init_late(void);
|
||||
#else
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/Kconfig
|
||||
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
||||
@@ -23,4 +23,12 @@ config MACH_CNS3420VB
|
||||
This is a platform with an on-board ARM11 MPCore and has support
|
||||
for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
|
||||
|
||||
+config MACH_GW2388
|
||||
+ bool "Support for Gateworks Laguna Platform"
|
||||
+ help
|
||||
+ Include support for the Gateworks Laguna Platform
|
||||
+
|
||||
+ This is a platform with an on-board ARM11 MPCore and has support
|
||||
+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
|
||||
+
|
||||
endif
|
||||
--- a/arch/arm/mach-cns3xxx/Makefile
|
||||
+++ b/arch/arm/mach-cns3xxx/Makefile
|
||||
@@ -8,3 +8,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o
|
||||
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
||||
cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
|
||||
cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
+cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o
|
||||
+
|
||||
--- a/arch/arm/mach-cns3xxx/devices.c
|
||||
+++ b/arch/arm/mach-cns3xxx/devices.c
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
+#include <asm/mach-types.h>
|
||||
#include "cns3xxx.h"
|
||||
#include "pm.h"
|
||||
#include "core.h"
|
||||
@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void)
|
||||
u32 gpioa_pins = __raw_readl(gpioa);
|
||||
|
||||
/* MMC/SD pins share with GPIOA */
|
||||
- gpioa_pins |= 0x1fff0004;
|
||||
+ if (machine_is_gw2388()) {
|
||||
+ gpioa_pins |= 0x1fff0000;
|
||||
+ } else {
|
||||
+ gpioa_pins |= 0x1fff0004;
|
||||
+ }
|
||||
__raw_writel(gpioa_pins, gpioa);
|
||||
|
||||
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
--- a/drivers/mmc/host/sdhci-cns3xxx.c
|
||||
+++ b/drivers/mmc/host/sdhci-cns3xxx.c
|
||||
@@ -88,9 +88,9 @@ static const struct sdhci_pltfm_data sdh
|
||||
.ops = &sdhci_cns3xxx_ops,
|
||||
.quirks = SDHCI_QUIRK_BROKEN_DMA |
|
||||
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
||||
- SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
|
||||
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
|
||||
- SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
|
||||
+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
||||
+ SDHCI_QUIRK_BROKEN_CARD_DETECTION,
|
||||
};
|
||||
|
||||
static int sdhci_cns3xxx_probe(struct platform_device *pdev)
|
||||
|
|
@ -1,95 +0,0 @@
|
|||
--- a/arch/arm/mach-cns3xxx/pcie.c
|
||||
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
||||
@@ -18,6 +18,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/interrupt.h>
|
||||
+#include <linux/irq.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include "cns3xxx.h"
|
||||
@@ -27,7 +28,7 @@ struct cns3xxx_pcie {
|
||||
void __iomem *host_regs; /* PCI config registers for host bridge */
|
||||
void __iomem *cfg0_regs; /* PCI Type 0 config registers */
|
||||
void __iomem *cfg1_regs; /* PCI Type 1 config registers */
|
||||
- unsigned int irqs[2];
|
||||
+ unsigned int irqs[5];
|
||||
struct resource res_io;
|
||||
struct resource res_mem;
|
||||
int port;
|
||||
@@ -95,7 +96,7 @@ static inline int check_master_abort(str
|
||||
void __iomem *host_base;
|
||||
u32 sreg, ereg;
|
||||
|
||||
- host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual;
|
||||
+ host_base = (void __iomem *) cnspci->host_regs;
|
||||
sreg = __raw_readw(host_base + 0x6) & 0xF900;
|
||||
ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg
|
||||
|
||||
@@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops =
|
||||
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
|
||||
- int irq = cnspci->irqs[!!dev->bus->number];
|
||||
+ int irq = cnspci->irqs[!!dev->bus->number + pin - 1];
|
||||
|
||||
pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
|
||||
pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
|
||||
@@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
|
||||
.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
|
||||
+ .irqs = {
|
||||
+ IRQ_CNS3XXX_PCIE0_RC,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE0_DEVICE,
|
||||
+ },
|
||||
.port = 0,
|
||||
},
|
||||
[1] = {
|
||||
@@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
|
||||
.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
|
||||
+ .irqs = {
|
||||
+ IRQ_CNS3XXX_PCIE1_RC,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ IRQ_CNS3XXX_PCIE1_DEVICE,
|
||||
+ },
|
||||
.port = 1,
|
||||
},
|
||||
};
|
||||
@@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un
|
||||
return 0;
|
||||
}
|
||||
|
||||
+void __init cns3xxx_pcie_set_irqs(int bus, int *irqs)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < 4; i++)
|
||||
+ cns3xxx_pcie[bus].irqs[i + 1] = irqs[i];
|
||||
+}
|
||||
+
|
||||
void __init cns3xxx_pcie_init_late(void)
|
||||
{
|
||||
int i;
|
||||
--- a/arch/arm/mach-cns3xxx/core.h
|
||||
+++ b/arch/arm/mach-cns3xxx/core.h
|
||||
@@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
extern void __init cns3xxx_pcie_init_late(void);
|
||||
+extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs);
|
||||
#else
|
||||
static inline void __init cns3xxx_pcie_init_late(void) {}
|
||||
+static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {}
|
||||
#endif
|
||||
|
||||
void __init cns3xxx_map_io(void);
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
--- a/drivers/pci/probe.c
|
||||
+++ b/drivers/pci/probe.c
|
||||
@@ -2655,7 +2655,8 @@ static void pcie_write_mrrs(struct pci_d
|
||||
* In the "safe" case, do not configure the MRRS. There appear to be
|
||||
* issues with setting MRRS to 0 on a number of devices.
|
||||
*/
|
||||
- if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
|
||||
+ if (pcie_bus_config != PCIE_BUS_PERFORMANCE &&
|
||||
+ pcie_bus_config != PCIE_BUS_PEER2PEER)
|
||||
return;
|
||||
|
||||
/*
|
||||
--- a/include/linux/pci.h
|
||||
+++ b/include/linux/pci.h
|
||||
@@ -868,7 +868,7 @@ enum pcie_bus_config_types {
|
||||
PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
|
||||
PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
|
||||
PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
|
||||
- PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
|
||||
+ PCIE_BUS_PEER2PEER, /* set MPS and MRSS to 128 for all devices */
|
||||
};
|
||||
|
||||
extern enum pcie_bus_config_types pcie_bus_config;
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
--- a/drivers/net/phy/broadcom.c
|
||||
+++ b/drivers/net/phy/broadcom.c
|
||||
@@ -429,7 +429,11 @@ static int bcm5481_config_aneg(struct ph
|
||||
ret = genphy_config_aneg(phydev);
|
||||
|
||||
/* Then we can set up the delay. */
|
||||
- bcm5481x_config(phydev);
|
||||
+ //bcm5481x_config(phydev);
|
||||
+
|
||||
+ phy_write(phydev, 0x18, 0xf1e7);
|
||||
+ phy_write(phydev, 0x1c, 0x8e00);
|
||||
+ phy_write(phydev, 0x1c, 0xa41f);
|
||||
|
||||
if (of_property_read_bool(np, "enet-phy-lane-swap")) {
|
||||
/* Lane Swap - Undocumented register...magic! */
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
--- a/drivers/usb/dwc2/params.c
|
||||
+++ b/drivers/usb/dwc2/params.c
|
||||
@@ -152,6 +152,36 @@ static void dwc2_set_stm32f7_hsotg_param
|
||||
p->host_perio_tx_fifo_size = 256;
|
||||
}
|
||||
|
||||
+static void dwc2_set_cns3xxx_params(struct dwc2_hsotg *hsotg)
|
||||
+{
|
||||
+ struct dwc2_core_params *p = &hsotg->params;
|
||||
+
|
||||
+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; /* non-HNP/non-SRP capable */
|
||||
+ p->host_dma = 1;
|
||||
+ p->dma_desc_enable = 0;
|
||||
+ p->speed = DWC2_SPEED_PARAM_HIGH; /* High Speed */
|
||||
+ p->enable_dynamic_fifo = 1;
|
||||
+ p->en_multiple_tx_fifo = 1;
|
||||
+ p->host_rx_fifo_size = 658; /* 774 DWORDs */
|
||||
+ p->host_nperio_tx_fifo_size = 128; /* 256 DWORDs */
|
||||
+ p->host_perio_tx_fifo_size = 658; /* 512 DWORDs */
|
||||
+ p->max_transfer_size = 65535,
|
||||
+ p->max_packet_count = 511;
|
||||
+ p->host_channels = 16;
|
||||
+ p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; /* UTMI */
|
||||
+ p->phy_utmi_width = 16; /* 8 bits */
|
||||
+ p->phy_ulpi_ddr = 0; /* Single */
|
||||
+ p->phy_ulpi_ext_vbus = 0;
|
||||
+ p->i2c_enable = 0;
|
||||
+ p->ulpi_fs_ls = 0;
|
||||
+ p->host_support_fs_ls_low_power = 0;
|
||||
+ p->host_ls_low_power_phy_clk = 0; /* 48 MHz */
|
||||
+ p->ts_dline = 0;
|
||||
+ p->reload_ctl = 0;
|
||||
+ p->ahbcfg = 0x10;
|
||||
+ p->uframe_sched = false;
|
||||
+}
|
||||
+
|
||||
const struct of_device_id dwc2_of_match_table[] = {
|
||||
{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
|
||||
{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
|
||||
@@ -820,17 +850,23 @@ int dwc2_get_hwparams(struct dwc2_hsotg
|
||||
|
||||
int dwc2_init_params(struct dwc2_hsotg *hsotg)
|
||||
{
|
||||
+ /*
|
||||
const struct of_device_id *match;
|
||||
void (*set_params)(void *data);
|
||||
+ */
|
||||
|
||||
dwc2_set_default_params(hsotg);
|
||||
dwc2_get_device_properties(hsotg);
|
||||
|
||||
+ /*
|
||||
match = of_match_device(dwc2_of_match_table, hsotg->dev);
|
||||
if (match && match->data) {
|
||||
set_params = match->data;
|
||||
set_params(hsotg);
|
||||
}
|
||||
+ */
|
||||
+
|
||||
+ dwc2_set_cns3xxx_params(hsotg);
|
||||
|
||||
dwc2_check_params(hsotg);
|
||||
|
||||
Loading…
Reference in New Issue