hak5
/
openwrt
mirror of https://github.com/hak5/openwrt.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

many more code cleanups for checkpatch.pl, most flagged as errors 

SVN-Revision: 13665
lede-17.01
Thomas Langer 2008-12-16 19:39:34 +00:00
parent cb87dfde7b
commit a38b23a894
22 changed files with 856 additions and 911 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

99
target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
View File

@ -70,33 +70,31 @@ unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }
#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3] #define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
static inline unsigned int get_input_clock(int pll)
static inline unsigned int
get_input_clock(int pll)
{ {
switch(pll) switch (pll) {
{
case 0: case 0:
if(ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC) if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
return BASIS_INPUT_CRYSTAL_USB; return BASIS_INPUT_CRYSTAL_USB;
else if(CGU_PLL0_PHASE_DIVIDER_ENABLE) else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
return BASIC_INPUT_CLOCK_FREQUENCY_1; return BASIC_INPUT_CLOCK_FREQUENCY_1;
else else
return BASIC_INPUT_CLOCK_FREQUENCY_2; return BASIC_INPUT_CLOCK_FREQUENCY_2;
case 1: case 1:
if(CGU_PLL1_SRC) if (CGU_PLL1_SRC)
return BASIS_INPUT_CRYSTAL_USB; return BASIS_INPUT_CRYSTAL_USB;
else if(CGU_PLL0_PHASE_DIVIDER_ENABLE) else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
return BASIC_INPUT_CLOCK_FREQUENCY_1; return BASIC_INPUT_CLOCK_FREQUENCY_1;
else else
return BASIC_INPUT_CLOCK_FREQUENCY_2; return BASIC_INPUT_CLOCK_FREQUENCY_2;
case 2: case 2:
switch(CGU_PLL2_SRC) switch (CGU_PLL2_SRC) {
{
case 0: case 0:
return cgu_get_pll0_fdiv(); return cgu_get_pll0_fdiv();
case 1: case 1:
return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2; return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
BASIC_INPUT_CLOCK_FREQUENCY_1 :
BASIC_INPUT_CLOCK_FREQUENCY_2;
case 2: case 2:
return BASIS_INPUT_CRYSTAL_USB; return BASIS_INPUT_CRYSTAL_USB;
} }
@ -105,8 +103,7 @@ get_input_clock(int pll)
} }
} }
static inline unsigned int static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
cal_dsm(int pll, unsigned int num, unsigned int den)
{ {
u64 res, clock = get_input_clock(pll); u64 res, clock = get_input_clock(pll);
@ -115,8 +112,8 @@ cal_dsm(int pll, unsigned int num, unsigned int den)
return res; return res;
} }
static inline unsigned int static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K) unsigned int K)
{ {
unsigned int num = ((N + 1) << 10) + K; unsigned int num = ((N + 1) << 10) + K;
unsigned int den = (M + 1) << 10; unsigned int den = (M + 1) << 10;
@ -124,8 +121,8 @@ mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
return cal_dsm(pll, num, den); return cal_dsm(pll, num, den);
} }
static inline unsigned int static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K) unsigned int K)
{ {
unsigned int num = ((N + 1) << 11) + K + 512; unsigned int num = ((N + 1) << 11) + K + 512;
unsigned int den = (M + 1) << 11; unsigned int den = (M + 1) << 11;
@ -133,8 +130,8 @@ ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
return cal_dsm(pll, num, den); return cal_dsm(pll, num, den);
} }
static inline unsigned int static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K) unsigned int K)
{ {
unsigned int num = K >= 512 ? unsigned int num = K >= 512 ?
((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
@ -143,22 +140,20 @@ ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
return cal_dsm(pll, num, den); return cal_dsm(pll, num, den);
} }
static inline unsigned int static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
dsm(int pll, unsigned int M, unsigned int N, unsigned int K, unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
unsigned int dsmsel, unsigned int phase_div_en)
{ {
if(!dsmsel) if (!dsmsel)
return mash_dsm(pll, M, N, K); return mash_dsm(pll, M, N, K);
else if(!phase_div_en) else if (!phase_div_en)
return mash_dsm(pll, M, N, K); return mash_dsm(pll, M, N, K);
else else
return ssff_dsm_2(pll, M, N, K); return ssff_dsm_2(pll, M, N, K);
} }
static inline unsigned int static inline unsigned int cgu_get_pll0_fosc(void)
cgu_get_pll0_fosc(void)
{ {
if(CGU_PLL0_BYPASS) if (CGU_PLL0_BYPASS)
return get_input_clock(0); return get_input_clock(0);
else else
return !CGU_PLL0_CFG_FRAC_EN return !CGU_PLL0_CFG_FRAC_EN
@ -168,19 +163,16 @@ cgu_get_pll0_fosc(void)
CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE); CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
} }
static unsigned int static unsigned int cgu_get_pll0_fdiv(void)
cgu_get_pll0_fdiv(void)
{ {
register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
return (cgu_get_pll0_fosc() + (div >> 1)) / div; return (cgu_get_pll0_fosc() + (div >> 1)) / div;
} }
unsigned int unsigned int cgu_get_io_region_clock(void)
cgu_get_io_region_clock(void)
{ {
register unsigned int ret = cgu_get_pll0_fosc(); unsigned int ret = cgu_get_pll0_fosc();
switch(ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
{
default: default:
case 0: case 0:
return (ret + 1) / 2; return (ret + 1) / 2;
@ -193,36 +185,36 @@ cgu_get_io_region_clock(void)
} }
} }
unsigned int unsigned int cgu_get_fpi_bus_clock(int fpi)
cgu_get_fpi_bus_clock(int fpi)
{ {
register unsigned int ret = cgu_get_io_region_clock(); unsigned int ret = cgu_get_io_region_clock();
if((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL)) if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
ret >>= 1; ret >>= 1;
return ret; return ret;
} }
void cgu_setup_pci_clk(int external_clock) void cgu_setup_pci_clk(int external_clock)
{ {
//set clock to 33Mhz /* set clock to 33Mhz */
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR); ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR); IFXMIPS_CGU_IFCCR);
if(external_clock) ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
{ IFXMIPS_CGU_IFCCR);
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR); if (external_clock) {
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
IFXMIPS_CGU_IFCCR);
ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR); ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
} else { } else {
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR); ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
IFXMIPS_CGU_IFCCR);
ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR); ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
} }
} }
unsigned int unsigned int ifxmips_get_cpu_hz(void)
ifxmips_get_cpu_hz(void)
{ {
unsigned int ddr_clock = DDR_HZ; unsigned int ddr_clock = DDR_HZ;
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) {
{
case 0: case 0:
return CLOCK_333M; return CLOCK_333M;
case 4: case 4:
@ -232,11 +224,10 @@ ifxmips_get_cpu_hz(void)
} }
EXPORT_SYMBOL(ifxmips_get_cpu_hz); EXPORT_SYMBOL(ifxmips_get_cpu_hz);
unsigned int unsigned int ifxmips_get_fpi_hz(void)
ifxmips_get_fpi_hz(void)
{ {
unsigned int ddr_clock = DDR_HZ; unsigned int ddr_clock = DDR_HZ;
if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40) if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
return ddr_clock >> 1; return ddr_clock >> 1;
return ddr_clock; return ddr_clock;
} }

56
target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
View File

@ -37,13 +37,13 @@ extern void ifxmips_enable_irq(unsigned int irq_nr);
extern void ifxmips_disable_irq(unsigned int irq_nr); extern void ifxmips_disable_irq(unsigned int irq_nr);
u64 *g_desc_list; u64 *g_desc_list;
_dma_device_info dma_devs[MAX_DMA_DEVICE_NUM]; struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
_dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM]; struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
static const char *global_device_name[MAX_DMA_DEVICE_NUM] = static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
{ "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" }; { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
_dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = { struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
{"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0}, {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
{"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0}, {"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
{"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1}, {"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
@ -66,7 +66,7 @@ _dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
{"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1} {"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
}; };
_dma_chan_map *chan_map = default_dma_map; struct dma_chan_map *chan_map = default_dma_map;
volatile u32 g_ifxmips_dma_int_status; volatile u32 g_ifxmips_dma_int_status;
volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */ volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */
@ -87,7 +87,7 @@ void common_buffer_free(u8 *dataptr, void *opt)
kfree(dataptr); kfree(dataptr);
} }
void enable_ch_irq(_dma_channel_info *pCh) void enable_ch_irq(struct dma_channel_info *pCh)
{ {
int chan_no = (int)(pCh - dma_chan); int chan_no = (int)(pCh - dma_chan);
unsigned long flag; unsigned long flag;
@ -100,7 +100,7 @@ void enable_ch_irq(_dma_channel_info *pCh)
ifxmips_enable_irq(pCh->irq); ifxmips_enable_irq(pCh->irq);
} }
void disable_ch_irq(_dma_channel_info *pCh) void disable_ch_irq(struct dma_channel_info *pCh)
{ {
unsigned long flag; unsigned long flag;
int chan_no = (int) (pCh - dma_chan); int chan_no = (int) (pCh - dma_chan);
@ -114,7 +114,7 @@ void disable_ch_irq(_dma_channel_info *pCh)
ifxmips_mask_and_ack_irq(pCh->irq); ifxmips_mask_and_ack_irq(pCh->irq);
} }
void open_chan(_dma_channel_info *pCh) void open_chan(struct dma_channel_info *pCh)
{ {
unsigned long flag; unsigned long flag;
int chan_no = (int)(pCh - dma_chan); int chan_no = (int)(pCh - dma_chan);
@ -127,7 +127,7 @@ void open_chan(_dma_channel_info *pCh)
local_irq_restore(flag); local_irq_restore(flag);
} }
void close_chan(_dma_channel_info *pCh) void close_chan(struct dma_channel_info *pCh)
{ {
unsigned long flag; unsigned long flag;
int chan_no = (int) (pCh - dma_chan); int chan_no = (int) (pCh - dma_chan);
@ -139,7 +139,7 @@ void close_chan(_dma_channel_info *pCh)
local_irq_restore(flag); local_irq_restore(flag);
} }
void reset_chan(_dma_channel_info *pCh) void reset_chan(struct dma_channel_info *pCh)
{ {
int chan_no = (int) (pCh - dma_chan); int chan_no = (int) (pCh - dma_chan);
@ -149,8 +149,8 @@ void reset_chan(_dma_channel_info *pCh)
void rx_chan_intr_handler(int chan_no) void rx_chan_intr_handler(int chan_no)
{ {
_dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev; struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
_dma_channel_info *pCh = &dma_chan[chan_no]; struct dma_channel_info *pCh = &dma_chan[chan_no];
struct rx_desc *rx_desc_p; struct rx_desc *rx_desc_p;
int tmp; int tmp;
unsigned long flag; unsigned long flag;
@ -179,8 +179,8 @@ void rx_chan_intr_handler(int chan_no)
inline void tx_chan_intr_handler(int chan_no) inline void tx_chan_intr_handler(int chan_no)
{ {
_dma_device_info *pDev = (_dma_device_info *)dma_chan[chan_no].dma_dev; struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
_dma_channel_info *pCh = &dma_chan[chan_no]; struct dma_channel_info *pCh = &dma_chan[chan_no];
int tmp; int tmp;
unsigned long flag; unsigned long flag;
@ -242,11 +242,11 @@ void do_dma_tasklet(unsigned long unused)
irqreturn_t dma_interrupt(int irq, void *dev_id) irqreturn_t dma_interrupt(int irq, void *dev_id)
{ {
_dma_channel_info *pCh; struct dma_channel_info *pCh;
int chan_no = 0; int chan_no = 0;
int tmp; int tmp;
pCh = (_dma_channel_info *)dev_id; pCh = (struct dma_channel_info *)dev_id;
chan_no = (int)(pCh - dma_chan); chan_no = (int)(pCh - dma_chan);
if (chan_no < 0 || chan_no > 19) if (chan_no < 0 || chan_no > 19)
BUG(); BUG();
@ -265,7 +265,7 @@ irqreturn_t dma_interrupt(int irq, void *dev_id)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
_dma_device_info *dma_device_reserve(char *dev_name) struct dma_device_info *dma_device_reserve(char *dev_name)
{ {
int i; int i;
@ -282,21 +282,21 @@ _dma_device_info *dma_device_reserve(char *dev_name)
} }
EXPORT_SYMBOL(dma_device_reserve); EXPORT_SYMBOL(dma_device_reserve);
void dma_device_release(_dma_device_info *dev) void dma_device_release(struct dma_device_info *dev)
{ {
dev->reserved = 0; dev->reserved = 0;
} }
EXPORT_SYMBOL(dma_device_release); EXPORT_SYMBOL(dma_device_release);
void dma_device_register(_dma_device_info *dev) void dma_device_register(struct dma_device_info *dev)
{ {
int i, j; int i, j;
int chan_no = 0; int chan_no = 0;
u8 *buffer; u8 *buffer;
int byte_offset; int byte_offset;
unsigned long flag; unsigned long flag;
_dma_device_info *pDev; struct dma_device_info *pDev;
_dma_channel_info *pCh; struct dma_channel_info *pCh;
struct rx_desc *rx_desc_p; struct rx_desc *rx_desc_p;
struct tx_desc *tx_desc_p; struct tx_desc *tx_desc_p;
@ -331,7 +331,7 @@ void dma_device_register(_dma_device_info *dev)
for (j = 0; j < pCh->desc_len; j++) { for (j = 0; j < pCh->desc_len; j++) {
rx_desc_p = (struct rx_desc *)pCh->desc_base + j; rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
pDev = (_dma_device_info *)(pCh->dma_dev); pDev = (struct dma_device_info *)(pCh->dma_dev);
buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j])); buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
if (!buffer) if (!buffer)
break; break;
@ -364,11 +364,11 @@ void dma_device_register(_dma_device_info *dev)
} }
EXPORT_SYMBOL(dma_device_register); EXPORT_SYMBOL(dma_device_register);
void dma_device_unregister(_dma_device_info *dev) void dma_device_unregister(struct dma_device_info *dev)
{ {
int i, j; int i, j;
int chan_no; int chan_no;
_dma_channel_info *pCh; struct dma_channel_info *pCh;
struct rx_desc *rx_desc_p; struct rx_desc *rx_desc_p;
struct tx_desc *tx_desc_p; struct tx_desc *tx_desc_p;
unsigned long flag; unsigned long flag;
@ -442,7 +442,7 @@ int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
int len; int len;
int byte_offset = 0; int byte_offset = 0;
void *p = NULL; void *p = NULL;
_dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan]; struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
struct rx_desc *rx_desc_p; struct rx_desc *rx_desc_p;
/* get the rx data first */ /* get the rx data first */
@ -488,13 +488,13 @@ int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void
{ {
unsigned long flag; unsigned long flag;
u32 tmp, byte_offset; u32 tmp, byte_offset;
_dma_channel_info *pCh; struct dma_channel_info *pCh;
int chan_no; int chan_no;
struct tx_desc *tx_desc_p; struct tx_desc *tx_desc_p;
local_irq_save(flag); local_irq_save(flag);
pCh = dma_dev->tx_chan[dma_dev->current_tx_chan]; pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
chan_no = (int)(pCh - (_dma_channel_info *) dma_chan); chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc; tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) { while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
@ -546,13 +546,13 @@ int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void
} }
EXPORT_SYMBOL(dma_device_write); EXPORT_SYMBOL(dma_device_write);
int map_dma_chan(_dma_chan_map *map) int map_dma_chan(struct dma_chan_map *map)
{ {
int i, j; int i, j;
int result; int result;
for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
strcpy(dma_devs[i].device_name, global_device_name[i]); dma_devs[i].device_name = &global_device_name[i];
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
dma_chan[i].irq = map[i].irq; dma_chan[i].irq = map[i].irq;

136
target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
View File

@ -51,7 +51,7 @@ static struct timer_list rst_button_timer;
extern struct sock *uevent_sock; extern struct sock *uevent_sock;
extern u64 uevent_next_seqnum(void); extern u64 uevent_next_seqnum(void);
static unsigned long seen; static unsigned long seen;
static int pressed = 0; static int pressed;
struct event_t { struct event_t {
struct work_struct wq; struct work_struct wq;
@ -61,26 +61,24 @@ struct event_t {
#endif #endif
#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; } #define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
int
ifxmips_port_reserve_pin(unsigned int port, unsigned int pin) int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__); printk(KERN_INFO "%s : call to obseleted function\n", __func__);
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_reserve_pin); EXPORT_SYMBOL(ifxmips_port_reserve_pin);
int int ifxmips_port_free_pin(unsigned int port, unsigned int pin)
ifxmips_port_free_pin(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__); printk(KERN_INFO "%s : call to obseleted function\n", __func__);
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_free_pin); EXPORT_SYMBOL(ifxmips_port_free_pin);
int int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin),
@ -89,8 +87,7 @@ ifxmips_port_set_open_drain(unsigned int port, unsigned int pin)
} }
EXPORT_SYMBOL(ifxmips_port_set_open_drain); EXPORT_SYMBOL(ifxmips_port_set_open_drain);
int int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin),
@ -99,110 +96,99 @@ ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin)
} }
EXPORT_SYMBOL(ifxmips_port_clear_open_drain); EXPORT_SYMBOL(ifxmips_port_clear_open_drain);
int int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
ifxmips_port_set_pudsel(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)); IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_pudsel); EXPORT_SYMBOL(ifxmips_port_set_pudsel);
int int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin)
ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)); IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_clear_pudsel); EXPORT_SYMBOL(ifxmips_port_clear_pudsel);
int int ifxmips_port_set_puden(unsigned int port, unsigned int pin)
ifxmips_port_set_puden(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)); IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_puden); EXPORT_SYMBOL(ifxmips_port_set_puden);
int int ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
ifxmips_port_clear_puden(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)); IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_clear_puden); EXPORT_SYMBOL(ifxmips_port_clear_puden);
int int ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
ifxmips_port_set_stoff(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC)); IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_stoff); EXPORT_SYMBOL(ifxmips_port_set_stoff);
int int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
ifxmips_port_clear_stoff(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_STOFF + (port * 0xC)); IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_clear_stoff); EXPORT_SYMBOL(ifxmips_port_clear_stoff);
int int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
ifxmips_port_set_dir_out(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC)); IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_dir_out); EXPORT_SYMBOL(ifxmips_port_set_dir_out);
int int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
ifxmips_port_set_dir_in(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_DIR + (port * 0xC)); IFXMIPS_GPIO_P0_DIR + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_dir_in); EXPORT_SYMBOL(ifxmips_port_set_dir_in);
int int ifxmips_port_set_output(unsigned int port, unsigned int pin)
ifxmips_port_set_output(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC)); IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_output); EXPORT_SYMBOL(ifxmips_port_set_output);
int int ifxmips_port_clear_output(unsigned int port, unsigned int pin)
ifxmips_port_clear_output(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_OUT + (port * 0xC)); IFXMIPS_GPIO_P0_OUT + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_clear_output); EXPORT_SYMBOL(ifxmips_port_clear_output);
int int ifxmips_port_get_input(unsigned int port, unsigned int pin)
ifxmips_port_get_input(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin)) if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
return 0; return 0;
else else
@ -210,40 +196,36 @@ ifxmips_port_get_input(unsigned int port, unsigned int pin)
} }
EXPORT_SYMBOL(ifxmips_port_get_input); EXPORT_SYMBOL(ifxmips_port_get_input);
int int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
ifxmips_port_set_altsel0(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)); IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_altsel0); EXPORT_SYMBOL(ifxmips_port_set_altsel0);
int int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)); IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_clear_altsel0); EXPORT_SYMBOL(ifxmips_port_clear_altsel0);
int int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
ifxmips_port_set_altsel1(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)); IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0; return 0;
} }
EXPORT_SYMBOL(ifxmips_port_set_altsel1); EXPORT_SYMBOL(ifxmips_port_set_altsel1);
int int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
{ {
IFXMIPS_GPIO_SANITY; IFXMIPS_GPIO_SANITY;
ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin),
IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)); IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
return 0; return 0;
@ -251,16 +233,14 @@ ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin)
EXPORT_SYMBOL(ifxmips_port_clear_altsel1); EXPORT_SYMBOL(ifxmips_port_clear_altsel1);
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN #ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
static inline void static inline void add_msg(struct sk_buff *skb, char *msg)
add_msg(struct sk_buff *skb, char *msg)
{ {
char *scratch; char *scratch;
scratch = skb_put(skb, strlen(msg) + 1); scratch = skb_put(skb, strlen(msg) + 1);
sprintf(scratch, msg); sprintf(scratch, msg);
} }
static void static void hotplug_button(struct work_struct *wq)
hotplug_button(struct work_struct *wq)
{ {
struct sk_buff *skb; struct sk_buff *skb;
struct event_t *event; struct event_t *event;
@ -269,17 +249,17 @@ hotplug_button(struct work_struct *wq)
char buf[128]; char buf[128];
event = container_of(wq, struct event_t, wq); event = container_of(wq, struct event_t, wq);
if(!uevent_sock) if (!uevent_sock)
goto done; goto done;
s = event->set ? "pressed" : "released"; s = event->set ? "pressed" : "released";
len = strlen(s) + 2; len = strlen(s) + 2;
skb = alloc_skb(len + 2048, GFP_KERNEL); skb = alloc_skb(len + 2048, GFP_KERNEL);
if(!skb) if (!skb)
goto done; goto done;
scratch = skb_put(skb, len); scratch = skb_put(skb, len);
sprintf(scratch, "%s@",s); sprintf(scratch, "%s@", s);
add_msg(skb, "HOME=/"); add_msg(skb, "HOME=/");
add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin");
add_msg(skb, "SUBSYSTEM=button"); add_msg(skb, "SUBSYSTEM=button");
@ -296,24 +276,21 @@ done:
kfree(event); kfree(event);
} }
static void static void reset_button_poll(unsigned long unused)
reset_button_poll(unsigned long unused)
{ {
struct event_t *event; struct event_t *event;
rst_button_timer.expires = jiffies + (HZ / 4); rst_button_timer.expires = jiffies + (HZ / 4);
add_timer(&rst_button_timer); add_timer(&rst_button_timer);
if (pressed != ifxmips_port_get_input(rst_port, rst_pin)) if (pressed != ifxmips_port_get_input(rst_port, rst_pin)) {
{ if (pressed)
if(pressed)
pressed = 0; pressed = 0;
else else
pressed = 1; pressed = 1;
event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); event = kzalloc(sizeof(struct event_t), GFP_ATOMIC);
if (!event) if (!event) {
{ printk(KERN_INFO "Could not alloc hotplug event\n");
printk("Could not alloc hotplug event\n");
return; return;
} }
event->set = pressed; event->set = pressed;
@ -325,8 +302,7 @@ reset_button_poll(unsigned long unused)
} }
#endif #endif
static int static int ifxmips_gpio_probe(struct platform_device *dev)
ifxmips_gpio_probe(struct platform_device *dev)
{ {
int retval = 0; int retval = 0;
@ -346,8 +322,7 @@ ifxmips_gpio_probe(struct platform_device *dev)
return retval; return retval;
} }
static int static int ifxmips_gpio_remove(struct platform_device *pdev)
ifxmips_gpio_remove(struct platform_device *pdev)
{ {
#ifdef CONFIG_IFXMIPS_GPIO_RST_BTN #ifdef CONFIG_IFXMIPS_GPIO_RST_BTN
del_timer_sync(&rst_button_timer); del_timer_sync(&rst_button_timer);
@ -355,8 +330,7 @@ ifxmips_gpio_remove(struct platform_device *pdev)
return 0; return 0;
} }
static struct static struct platform_driver ifxmips_gpio_driver = {
platform_driver ifxmips_gpio_driver = {
.probe = ifxmips_gpio_probe, .probe = ifxmips_gpio_probe,
.remove = ifxmips_gpio_remove, .remove = ifxmips_gpio_remove,
.driver = { .driver = {
@ -365,8 +339,7 @@ platform_driver ifxmips_gpio_driver = {
}, },
}; };
int __init int __init ifxmips_gpio_init(void)
ifxmips_gpio_init(void)
{ {
int ret = platform_driver_register(&ifxmips_gpio_driver); int ret = platform_driver_register(&ifxmips_gpio_driver);
if (ret) if (ret)
@ -374,8 +347,7 @@ ifxmips_gpio_init(void)
return ret; return ret;
} }
void __exit void __exit ifxmips_gpio_exit(void)
ifxmips_gpio_exit(void)
{ {
platform_driver_unregister(&ifxmips_gpio_driver); platform_driver_unregister(&ifxmips_gpio_driver);
} }

14
target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
View File

@ -13,7 +13,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
@ -21,21 +21,21 @@
#include <linux/version.h> #include <linux/version.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
void void ifxmips_pmu_enable(unsigned int module)
ifxmips_pmu_enable(unsigned int module)
{ {
int err = 1000000; int err = 1000000;
ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR); ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module,
while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module)) {} IFXMIPS_PMU_PWDCR);
while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module))
;
if (!err) if (!err)
panic("activating PMU module failed!"); panic("activating PMU module failed!");
} }
EXPORT_SYMBOL(ifxmips_pmu_enable); EXPORT_SYMBOL(ifxmips_pmu_enable);
void void ifxmips_pmu_disable(unsigned int module)
ifxmips_pmu_disable(unsigned int module)
{ {
ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR); ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
} }

25
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
View File

@ -26,11 +26,11 @@
static char buf[1024]; /* for prom_printf() */ static char buf[1024]; /* for prom_printf() */
/* for voice cpu (MIPS24K) */ /* for voice cpu (MIPS24K) */
unsigned int *prom_cp1_base = NULL; unsigned int *prom_cp1_base;
unsigned int prom_cp1_size = 0; unsigned int prom_cp1_size;
/* for Multithreading (APRP) on MIPS34K */ /* for Multithreading (APRP) on MIPS34K */
unsigned long physical_memsize = 0L; unsigned long physical_memsize;
#ifdef IFXMIPS_PROM_ASC0 #ifdef IFXMIPS_PROM_ASC0
#define IFXMIPS_ASC_DIFF 0 #define IFXMIPS_ASC_DIFF 0
@ -57,7 +57,8 @@ void prom_putchar(char c)
unsigned long flags; unsigned long flags;
local_irq_save(flags); local_irq_save(flags);
while((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF); while ((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF)
;
if (c == '\n') if (c == '\n')
asc_w32('\r', IFXMIPS_ASC_TBUF); asc_w32('\r', IFXMIPS_ASC_TBUF);
@ -105,10 +106,9 @@ void __init prom_init(void)
mips_machtype = MACH_INFINEON_IFXMIPS; mips_machtype = MACH_INFINEON_IFXMIPS;
if (argc) { if (argc) {
argv = (char**)KSEG1ADDR((unsigned long)argv); argv = (char **)KSEG1ADDR((unsigned long)argv);
arcs_cmdline[0] = '\0'; arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) for (i = 1; i < argc; i++) {
{
char *a = (char *)KSEG1ADDR(argv[i]); char *a = (char *)KSEG1ADDR(argv[i]);
if (!argv[i]) if (!argv[i])
continue; continue;
@ -129,25 +129,22 @@ void __init prom_init(void)
strcpy(&(arcs_cmdline[0]), strcpy(&(arcs_cmdline[0]),
"console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit"); "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
} }
envp = (char**)KSEG1ADDR((unsigned long)envp); envp = (char **)KSEG1ADDR((unsigned long)envp);
while(*envp) while (*envp) {
{
char *e = (char *)KSEG1ADDR(*envp); char *e = (char *)KSEG1ADDR(*envp);
if (!strncmp(e, "memsize=", 8)) if (!strncmp(e, "memsize=", 8)) {
{
e += 8; e += 8;
memsize = simple_strtoul(e, NULL, 10); memsize = simple_strtoul(e, NULL, 10);
} }
envp++; envp++;
} }
memsize *= 1024 * 1024; memsize *= 1024 * 1024;
/* only on Twinpass/Danube a second CPU is used for Voice */ /* only on Twinpass/Danube a second CPU is used for Voice */
if ((cpu_data[0].cputype == CPU_24K) && (prom_cp1_size)) { if ((cpu_data[0].cputype == CPU_24K) && (prom_cp1_size)) {
memsize -= prom_cp1_size; memsize -= prom_cp1_size;
prom_cp1_base = (unsigned int*)KSEG1ADDR(memsize); prom_cp1_base = (unsigned int *)KSEG1ADDR(memsize);
prom_printf("Using %dMB Ram and reserving %dMB for cp1\n", prom_printf("Using %dMB Ram and reserving %dMB for cp1\n",
memsize>>20, prom_cp1_size>>20); memsize>>20, prom_cp1_size>>20);

20
target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
View File

@ -13,14 +13,14 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/pm.h> #include <linux/pm.h>
#include <asm/reboot.h> #include <linux/reboot.h>
#include <linux/io.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/io.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
static void ifxmips_machine_restart(char *command) static void ifxmips_machine_restart(char *command)
@ -28,22 +28,26 @@ static void ifxmips_machine_restart(char *command)
printk(KERN_NOTICE "System restart\n"); printk(KERN_NOTICE "System restart\n");
local_irq_disable(); local_irq_disable();
ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL, IFXMIPS_RCU_RST); ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL,
for(;;); IFXMIPS_RCU_RST);
for (;;)
;
} }
static void ifxmips_machine_halt(void) static void ifxmips_machine_halt(void)
{ {
printk(KERN_NOTICE "System halted.\n"); printk(KERN_NOTICE "System halted.\n");
local_irq_disable(); local_irq_disable();
for(;;); for (;;)
;
} }
static void ifxmips_machine_power_off(void) static void ifxmips_machine_power_off(void)
{ {
printk (KERN_NOTICE "Please turn off the power now.\n"); printk(KERN_NOTICE "Please turn off the power now.\n");
local_irq_disable(); local_irq_disable();
for(;;); for (;;)
;
} }
void ifxmips_reboot_setup(void) void ifxmips_reboot_setup(void)

6
target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
View File

@ -19,11 +19,13 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/time.h> #include <linux/time.h>
#include <asm/traps.h>
#include <linux/cpu.h> #include <linux/cpu.h>
#include <asm/traps.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_irq.h> #include <asm/ifxmips/ifxmips_irq.h>
#include <asm/ifxmips/ifxmips_pmu.h> #include <asm/ifxmips/ifxmips_pmu.h>

565
target/linux/ifxmips/files/arch/mips/ifxmips/timer.c
View File

File diff suppressed because it is too large Load Diff

25
target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c
View File

@ -1251,24 +1251,13 @@ static int ssc_session(char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
else else
eff_size = tx_len; eff_size = tx_len;
//4 bytes alignment, required by driver /* 4 bytes alignment, required by driver */
/* change by TaiCheng */ ssc_tx_buf = kmalloc(sizeof(char) *
//if (in_irq()){ ((eff_size + 3) & (~3)),
if (1) { GFP_ATOMIC);
ssc_tx_buf = kmalloc(sizeof(char) * ssc_rx_buf = kmalloc(sizeof(char) *
((eff_size + 3) & (~3)), ((eff_size + 3) & (~3)),
GFP_ATOMIC); GFP_ATOMIC);
ssc_rx_buf = kmalloc(sizeof(char) *
((eff_size + 3) & (~3)),
GFP_ATOMIC);
} else {
ssc_tx_buf = kmalloc(sizeof(char) *
((eff_size + 3) & (~3)),
GFP_KERNEL);
ssc_rx_buf = kmalloc(sizeof(char) *
((eff_size + 3) & (~3)),
GFP_KERNEL);
}
if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) { if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
printk("no memory for size of %d\n", eff_size); printk("no memory for size of %d\n", eff_size);
ret = -ENOMEM; ret = -ENOMEM;

56
target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c
View File

@ -14,7 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2006 infineon * Copyright (C) 2006 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
* *
*/ */
@ -37,8 +37,11 @@
#define DRVNAME "ifxmips_led" #define DRVNAME "ifxmips_led"
#if 1
#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING #define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING
//#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING #else
#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING
#endif
#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ #define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ
@ -51,45 +54,47 @@ struct ifxmips_led {
u8 bit; u8 bit;
}; };
void ifxmips_led_set (unsigned int led) void ifxmips_led_set(unsigned int led)
{ {
led &= 0xffffff; led &= 0xffffff;
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
} }
EXPORT_SYMBOL(ifxmips_led_set); EXPORT_SYMBOL(ifxmips_led_set);
void ifxmips_led_clear (unsigned int led) void ifxmips_led_clear(unsigned int led)
{ {
led = ~(led & 0xffffff); led = ~(led & 0xffffff);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
} }
EXPORT_SYMBOL(ifxmips_led_clear); EXPORT_SYMBOL(ifxmips_led_clear);
void ifxmips_led_blink_set (unsigned int led) void ifxmips_led_blink_set(unsigned int led)
{ {
led &= 0xffffff; led &= 0xffffff;
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
} }
EXPORT_SYMBOL(ifxmips_led_blink_set); EXPORT_SYMBOL(ifxmips_led_blink_set);
void ifxmips_led_blink_clear (unsigned int led) void ifxmips_led_blink_clear(unsigned int led)
{ {
led = ~(led & 0xffffff); led = ~(led & 0xffffff);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
} }
EXPORT_SYMBOL(ifxmips_led_blink_clear); EXPORT_SYMBOL(ifxmips_led_blink_clear);
void ifxmips_ledapi_set(struct led_classdev *led_cdev, enum led_brightness value) static void ifxmips_ledapi_set(struct led_classdev *led_cdev,
enum led_brightness value)
{ {
struct ifxmips_led *led_dev = container_of(led_cdev, struct ifxmips_led, cdev); struct ifxmips_led *led_dev =
container_of(led_cdev, struct ifxmips_led, cdev);
if(value) if (value)
ifxmips_led_set(1 << led_dev->bit); ifxmips_led_set(1 << led_dev->bit);
else else
ifxmips_led_clear(1 << led_dev->bit); ifxmips_led_clear(1 << led_dev->bit);
} }
void ifxmips_led_setup_gpio (void) void ifxmips_led_setup_gpio(void)
{ {
int i = 0; int i = 0;
@ -115,28 +120,36 @@ static int ifxmips_led_probe(struct platform_device *dev)
ifxmips_w32(0, IFXMIPS_LED_CON1); ifxmips_w32(0, IFXMIPS_LED_CON1);
/* setup the clock edge that the shift register is triggered on */ /* setup the clock edge that the shift register is triggered on */
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK,
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0); IFXMIPS_LED_CON0);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE,
IFXMIPS_LED_CON0);
/* per default leds 15-0 are set */ /* per default leds 15-0 are set */
ifxmips_w32(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1); ifxmips_w32(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
/* leds are update periodically by the FPID */ /* leds are update periodically by the FPID */
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK,
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1); IFXMIPS_LED_CON1);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI,
IFXMIPS_LED_CON1);
/* set led update speed */ /* set led update speed */
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK,
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1); IFXMIPS_LED_CON1);
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED,
IFXMIPS_LED_CON1);
/* adsl 0 and 1 leds are updated by the arc */ /* adsl 0 and 1 leds are updated by the arc */
ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0); ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC,
IFXMIPS_LED_CON0);
/* per default, the leds are turned on */ /* per default, the leds are turned on */
ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED); ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED);
for (i = 0; i < IFXMIPS_MAX_LED; i++) { for (i = 0; i < IFXMIPS_MAX_LED; i++) {
struct ifxmips_led *tmp = kzalloc(sizeof(struct ifxmips_led), GFP_KERNEL); struct ifxmips_led *tmp =
kzalloc(sizeof(struct ifxmips_led), GFP_KERNEL);
tmp->cdev.brightness_set = ifxmips_ledapi_set; tmp->cdev.brightness_set = ifxmips_ledapi_set;
tmp->cdev.name = kmalloc(sizeof("ifxmips:led:00"), GFP_KERNEL); tmp->cdev.name = kmalloc(sizeof("ifxmips:led:00"), GFP_KERNEL);
sprintf((char *)tmp->cdev.name, "ifxmips:led:%02d", i); sprintf((char *)tmp->cdev.name, "ifxmips:led:%02d", i);
@ -162,16 +175,17 @@ static struct platform_driver ifxmips_led_driver = {
}, },
}; };
int __init ifxmips_led_init (void) int __init ifxmips_led_init(void)
{ {
int ret = platform_driver_register(&ifxmips_led_driver); int ret = platform_driver_register(&ifxmips_led_driver);
if (ret) if (ret)
printk(KERN_INFO "ifxmips_led: Error registering platfom driver!"); printk(KERN_INFO
"ifxmips_led: Error registering platfom driver!");
return ret; return ret;
} }
void __exit ifxmips_led_exit (void) void __exit ifxmips_led_exit(void)
{ {
platform_driver_unregister(&ifxmips_led_driver); platform_driver_unregister(&ifxmips_led_driver);
} }

11
target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
View File

@ -55,7 +55,8 @@ void ifxmips_write_mdio(u32 phy_addr, u32 phy_reg, u16 phy_data)
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) | ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
phy_data; phy_data;
while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST); while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
;
ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
} }
EXPORT_SYMBOL(ifxmips_write_mdio); EXPORT_SYMBOL(ifxmips_write_mdio);
@ -66,9 +67,11 @@ unsigned short ifxmips_read_mdio(u32 phy_addr, u32 phy_reg)
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET); ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST) ; while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
;
ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST) ; while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
;
val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK; val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val; return val;
} }
@ -302,7 +305,7 @@ static int ifxmips_mii_dev_init(struct net_device *dev)
printk(KERN_INFO "ifxmips_mii0: using mac="); printk(KERN_INFO "ifxmips_mii0: using mac=");
for (i = 0; i < 6; i++) { for (i = 0; i < 6; i++) {
dev->dev_addr[i] = mac_addr[i]; dev->dev_addr[i] = mac_addr[i];
printk("%02X%c", dev->dev_addr[i], (i == 5)?('\n'):(':')); printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':'));
} }
return 0; return 0;
} }

83
target/linux/ifxmips/files/drivers/watchdog/ifxmips_wdt.c
View File

@ -3,7 +3,7 @@
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
@ -23,36 +23,35 @@
#include <linux/miscdevice.h> #include <linux/miscdevice.h>
#include <linux/watchdog.h> #include <linux/watchdog.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <asm/uaccess.h> #include <linux/uaccess.h>
#include <asm-mips/ifxmips/ifxmips_cgu.h>
#include <asm-mips/ifxmips/ifxmips.h>
#define IFXMIPS_WDT_PW1 0x00BE0000 #include <asm/ifxmips/ifxmips_cgu.h>
#define IFXMIPS_WDT_PW2 0x00DC0000 #include <asm/ifxmips/ifxmips.h>
#define IFXMIPS_WDT_PW1 0x00BE0000
#define IFXMIPS_WDT_PW2 0x00DC0000
#ifndef CONFIG_WATCHDOG_NOWAYOUT #ifndef CONFIG_WATCHDOG_NOWAYOUT
static int wdt_ok_to_close = 0; static int wdt_ok_to_close;
#endif #endif
int wdt_timeout = 30; static int wdt_timeout = 30;
int int ifxmips_wdt_enable(unsigned int timeout)
ifxmips_wdt_enable(unsigned int timeout)
{ {
u32 fpi; u32 fpi;
fpi = cgu_get_io_region_clock(); fpi = cgu_get_io_region_clock();
ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR); ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR);
ifxmips_w32(IFXMIPS_WDT_PW2 | ifxmips_w32(IFXMIPS_WDT_PW2 |
(0x3 << 26) | // PWL (0x3 << 26) | /* PWL */
(0x3 << 24) | // CLKDIV (0x3 << 24) | /* CLKDIV */
(0x1 << 31) | // enable (0x1 << 31) | /* enable */
((timeout * (fpi / 0x40000)) + 0x1000), // reload ((timeout * (fpi / 0x40000)) + 0x1000), /* reload */
IFXMIPS_BIU_WDT_CR); IFXMIPS_BIU_WDT_CR);
return 0; return 0;
} }
void void ifxmips_wdt_disable(void)
ifxmips_wdt_disable(void)
{ {
#ifndef CONFIG_WATCHDOG_NOWAYOUT #ifndef CONFIG_WATCHDOG_NOWAYOUT
wdt_ok_to_close = 0; wdt_ok_to_close = 0;
@ -61,22 +60,20 @@ ifxmips_wdt_disable(void)
ifxmips_w32(IFXMIPS_WDT_PW2, IFXMIPS_BIU_WDT_CR); ifxmips_w32(IFXMIPS_WDT_PW2, IFXMIPS_BIU_WDT_CR);
} }
static ssize_t static ssize_t ifxmips_wdt_write(struct file *file, const char __user *data,
ifxmips_wdt_write(struct file *file, const char __user *data, size_t len, size_t len, loff_t *ppos)
loff_t *ppos)
{ {
size_t i; size_t i;
if(!len) if (!len)
return 0; return 0;
#ifndef CONFIG_WATCHDOG_NOWAYOUT #ifndef CONFIG_WATCHDOG_NOWAYOUT
for(i = 0; i != len; i++) for (i = 0; i != len; i++) {
{
char c; char c;
if(get_user(c, data + i)) if (get_user(c, data + i))
return -EFAULT; return -EFAULT;
if(c == 'V') if (c == 'V')
wdt_ok_to_close = 1; wdt_ok_to_close = 1;
} }
#endif #endif
@ -89,14 +86,12 @@ static struct watchdog_info ident = {
.identity = "ifxmips Watchdog", .identity = "ifxmips Watchdog",
}; };
static int static int ifxmips_wdt_ioctl(struct inode *inode, struct file *file,
ifxmips_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned int cmd, unsigned long arg)
unsigned long arg)
{ {
int ret = -ENOTTY; int ret = -ENOTTY;
switch(cmd) switch (cmd) {
{
case WDIOC_GETSUPPORT: case WDIOC_GETSUPPORT:
ret = copy_to_user((struct watchdog_info __user *)arg, &ident, ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
sizeof(ident)) ? -EFAULT : 0; sizeof(ident)) ? -EFAULT : 0;
@ -107,7 +102,7 @@ ifxmips_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
break; break;
case WDIOC_SETTIMEOUT: case WDIOC_SETTIMEOUT:
ret = get_user(wdt_timeout, (int __user*)arg); ret = get_user(wdt_timeout, (int __user *)arg);
break; break;
case WDIOC_KEEPALIVE: case WDIOC_KEEPALIVE:
@ -118,8 +113,7 @@ ifxmips_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
return ret; return ret;
} }
static int static int ifxmips_wdt_open(struct inode *inode, struct file *file)
ifxmips_wdt_open(struct inode *inode, struct file *file)
{ {
ifxmips_wdt_enable(wdt_timeout); ifxmips_wdt_enable(wdt_timeout);
return nonseekable_open(inode, file); return nonseekable_open(inode, file);
@ -128,11 +122,12 @@ ifxmips_wdt_open(struct inode *inode, struct file *file)
static int ifxmips_wdt_release(struct inode *inode, struct file *file) static int ifxmips_wdt_release(struct inode *inode, struct file *file)
{ {
#ifndef CONFIG_WATCHDOG_NOWAYOUT #ifndef CONFIG_WATCHDOG_NOWAYOUT
if(wdt_ok_to_close) if (wdt_ok_to_close)
ifxmips_wdt_disable(); ifxmips_wdt_disable();
else else
#endif #endif
printk("ifxmips_wdt: watchdog closed without warning, rebooting system\n"); printk(KERN_ERR "ifxmips_wdt: watchdog closed without warning,"
" rebooting system\n");
return 0; return 0;
} }
@ -150,20 +145,18 @@ static struct miscdevice ifxmips_wdt_miscdev = {
.fops = &ifxmips_wdt_fops, .fops = &ifxmips_wdt_fops,
}; };
static int static int ifxmips_wdt_probe(struct platform_device *dev)
ifxmips_wdt_probe(struct platform_device *dev)
{ {
int err; int err;
err = misc_register(&ifxmips_wdt_miscdev); err = misc_register(&ifxmips_wdt_miscdev);
if(err) if (err)
printk("ifxmips_wdt: error creating device\n"); printk(KERN_INFO "ifxmips_wdt: error creating device\n");
else else
printk("ifxmips_wdt: loaded\n"); printk(KERN_INFO "ifxmips_wdt: loaded\n");
return err; return err;
} }
static int static int ifxmips_wdt_remove(struct platform_device *dev)
ifxmips_wdt_remove(struct platform_device *dev)
{ {
ifxmips_wdt_disable(); ifxmips_wdt_disable();
misc_deregister(&ifxmips_wdt_miscdev); misc_deregister(&ifxmips_wdt_miscdev);
@ -180,17 +173,15 @@ static struct platform_driver ifxmips_wdt_driver = {
}, },
}; };
static int __init static int __init init_ifxmips_wdt(void)
init_ifxmips_wdt(void)
{ {
int ret = platform_driver_register(&ifxmips_wdt_driver); int ret = platform_driver_register(&ifxmips_wdt_driver);
if(ret) if (ret)
printk(KERN_INFO "ifxmips_wdt: error registering platfom driver!"); printk(KERN_INFO "ifxmips_wdt: error registering platfom driver!");
return ret; return ret;
} }
static void __exit static void __exit exit_ifxmips_wdt(void)
exit_ifxmips_wdt(void)
{ {
platform_driver_unregister(&ifxmips_wdt_driver); platform_driver_unregister(&ifxmips_wdt_driver);
} }

382
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
View File

@ -19,9 +19,9 @@
#ifndef _IFXMIPS_H__ #ifndef _IFXMIPS_H__
#define _IFXMIPS_H__ #define _IFXMIPS_H__
#define ifxmips_r32(reg) __raw_readl(reg) #define ifxmips_r32(reg) __raw_readl(reg)
#define ifxmips_w32(val,reg) __raw_writel(val,reg) #define ifxmips_w32(val, reg) __raw_writel(val, reg)
#define ifxmips_w32_mask(clear,set,reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) #define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
/*------------ GENERAL */ /*------------ GENERAL */
@ -111,7 +111,7 @@
#define IFXMIPS_RCU_BASE_ADDR 0xBF203000 #define IFXMIPS_RCU_BASE_ADDR 0xBF203000
/* reset request */ /* reset request */
#define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010)) #define IFXMIPS_RCU_RST ((u32 *)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
#define IFXMIPS_RCU_RST_CPU1 (1 << 3) #define IFXMIPS_RCU_RST_CPU1 (1 << 3)
#define IFXMIPS_RCU_RST_ALL 0x40000000 #define IFXMIPS_RCU_RST_ALL 0x40000000
@ -125,13 +125,13 @@
#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300 #define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
/* clock control register */ /* clock control register */
#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000)) #define IFXMIPS_GPTU_GPT_CLC ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
/* captur reload register */ /* captur reload register */
#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030)) #define IFXMIPS_GPTU_GPT_CAPREL ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
/* timer 6 control register */ /* timer 6 control register */
#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020)) #define IFXMIPS_GPTU_GPT_T6CON ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
/*------------ EBU */ /*------------ EBU */
@ -139,33 +139,33 @@
#define IFXMIPS_EBU_BASE_ADDR 0xBE105300 #define IFXMIPS_EBU_BASE_ADDR 0xBE105300
/* bus configuration register */ /* bus configuration register */
#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060)) #define IFXMIPS_EBU_BUSCON0 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090)) #define IFXMIPS_EBU_PCC_CON ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4)) #define IFXMIPS_EBU_PCC_IEN ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0)) #define IFXMIPS_EBU_PCC_ISTAT ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
/*------------ CGU */ /*------------ CGU */
#define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000) #define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
#define IFXMIPS_CGU_PLL0_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0004)) #define IFXMIPS_CGU_PLL0_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0004))
#define IFXMIPS_CGU_PLL1_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0008)) #define IFXMIPS_CGU_PLL1_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0008))
#define IFXMIPS_CGU_PLL2_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x000C)) #define IFXMIPS_CGU_PLL2_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x000C))
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) #define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014)) #define IFXMIPS_CGU_UPDATE ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) #define IFXMIPS_CGU_IF_CLK ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C)) #define IFXMIPS_CGU_OSC_CON ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020)) #define IFXMIPS_CGU_SMD ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028)) #define IFXMIPS_CGU_CT1SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C)) #define IFXMIPS_CGU_CT2SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030)) #define IFXMIPS_CGU_PCMCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) #define IFXMIPS_CGU_PCI_CR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038)) #define IFXMIPS_CGU_PD_PC ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C)) #define IFXMIPS_CGU_FMR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
/* clock mux */ /* clock mux */
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) #define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) #define IFXMIPS_CGU_IFCCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) #define IFXMIPS_CGU_PCICR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
#define CLOCK_60M 60000000 #define CLOCK_60M 60000000
#define CLOCK_83M 83333333 #define CLOCK_83M 83333333
@ -179,8 +179,8 @@
#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000) #define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C)) #define IFXMIPS_PMU_PWDCR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020)) #define IFXMIPS_PMU_PWDSR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
/*------------ ICU */ /*------------ ICU */
@ -188,17 +188,17 @@
#define IFXMIPS_ICU_BASE_ADDR 0xBF880200 #define IFXMIPS_ICU_BASE_ADDR 0xBF880200
#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000)) #define IFXMIPS_ICU_IM0_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008)) #define IFXMIPS_ICU_IM0_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010)) #define IFXMIPS_ICU_IM0_IOSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018)) #define IFXMIPS_ICU_IM0_IRSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020)) #define IFXMIPS_ICU_IM0_IMR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028)) #define IFXMIPS_ICU_IM1_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
#define IFXMIPS_ICU_IM2_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0058)) #define IFXMIPS_ICU_IM2_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0058))
#define IFXMIPS_ICU_IM3_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0080)) #define IFXMIPS_ICU_IM3_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0080))
#define IFXMIPS_ICU_IM4_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00A8)) #define IFXMIPS_ICU_IM4_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00A8))
#define IFXMIPS_ICU_IM5_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00D0)) #define IFXMIPS_ICU_IM5_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))
#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR) #define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
@ -209,15 +209,15 @@
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 #define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) #define IFXMIPS_PPE32_MEM_MAP ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
#define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080)) #define IFXMIPS_PPE32_SRST ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))
#define MII_MODE 1 #define MII_MODE 1
#define REV_MII_MODE 2 #define REV_MII_MODE 2
/* mdio access */ /* mdio access */
#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800)) #define IFXMIPS_PPE32_MDIO_CFG ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804)) #define IFXMIPS_PPE32_MDIO_ACC ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
#define MDIO_ACC_REQUEST 0x80000000 #define MDIO_ACC_REQUEST 0x80000000
#define MDIO_ACC_READ 0x40000000 #define MDIO_ACC_READ 0x40000000
@ -228,20 +228,20 @@
#define MDIO_ACC_VAL_MASK 0xffff #define MDIO_ACC_VAL_MASK 0xffff
/* configuration */ /* configuration */
#define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808)) #define IFXMIPS_PPE32_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
#define PPE32_MII_MASK 0xfffffffc #define PPE32_MII_MASK 0xfffffffc
#define PPE32_MII_NORMAL 0x8 #define PPE32_MII_NORMAL 0x8
#define PPE32_MII_REVERSE 0xe #define PPE32_MII_REVERSE 0xe
/* packet length */ /* packet length */
#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820)) #define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
#define PPE32_PLEN_OVER 0x5ee #define PPE32_PLEN_OVER 0x5ee
#define PPE32_PLEN_UNDER 0x400000 #define PPE32_PLEN_UNDER 0x400000
/* enet */ /* enet */
#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840)) #define IFXMIPS_PPE32_ENET_MAC_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
#define PPE32_CGEN 0x800 #define PPE32_CGEN 0x800
@ -249,45 +249,45 @@
/*------------ DMA */ /*------------ DMA */
#define IFXMIPS_DMA_BASE_ADDR 0xBE104100 #define IFXMIPS_DMA_BASE_ADDR 0xBE104100
#define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18)) #define IFXMIPS_DMA_CS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x18))
#define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C)) #define IFXMIPS_DMA_CIE ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
#define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4)) #define IFXMIPS_DMA_IRNEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
#define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C)) #define IFXMIPS_DMA_CCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
#define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28)) #define IFXMIPS_DMA_CIS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x28))
#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24)) #define IFXMIPS_DMA_CDLEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x24))
#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40)) #define IFXMIPS_DMA_PS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x40))
#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44)) #define IFXMIPS_DMA_PCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x44))
#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10)) #define IFXMIPS_DMA_CTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x10))
#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14)) #define IFXMIPS_DMA_CPOLL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x14))
#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20)) #define IFXMIPS_DMA_CDBA ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x20))
/*------------ PCI */ /*------------ PCI */
#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400) #define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0)) #define PCI_CR_FCI_ADDR_MAP0 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4)) #define PCI_CR_FCI_ADDR_MAP1 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8)) #define PCI_CR_FCI_ADDR_MAP2 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC)) #define PCI_CR_FCI_ADDR_MAP3 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0)) #define PCI_CR_FCI_ADDR_MAP4 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4)) #define PCI_CR_FCI_ADDR_MAP5 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8)) #define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC)) #define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000)) #define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030)) #define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080)) #define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4)) #define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044)) #define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048)) #define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C)) #define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010)) #define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064)) #define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8)) #define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C)) #define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000) #define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004)) #define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
#define PCI_MASTER0_REQ_MASK_2BITS 8 #define PCI_MASTER0_REQ_MASK_2BITS 8
#define PCI_MASTER1_REQ_MASK_2BITS 10 #define PCI_MASTER1_REQ_MASK_2BITS 10
@ -299,18 +299,18 @@
#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000) #define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0)) #define IFXMIPS_BIU_WDT_CR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8)) #define IFXMIPS_BIU_WDT_SR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
/*------------ LED */ /*------------ LED */
#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0) #define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000)) #define IFXMIPS_LED_CON0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0000))
#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004)) #define IFXMIPS_LED_CON1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0004))
#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008)) #define IFXMIPS_LED_CPU0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0008))
#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C)) #define IFXMIPS_LED_CPU1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x000C))
#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010)) #define IFXMIPS_LED_AR ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0010))
#define LED_CON0_SWU (1 << 31) #define LED_CON0_SWU (1 << 31)
#define LED_CON0_AD1 (1 << 25) #define LED_CON0_AD1 (1 << 25)
@ -339,24 +339,24 @@
#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00) #define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
#define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) #define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
#define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) #define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
#define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) #define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) #define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) #define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) #define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) #define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) #define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) #define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) #define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) #define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) #define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) #define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) #define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) #define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) #define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) #define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) #define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
/*------------ SSC */ /*------------ SSC */
@ -364,71 +364,71 @@
#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800) #define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
#define IFXMIPS_SSC_CLC ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0000)) #define IFXMIPS_SSC_CLC ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4)) #define IFXMIPS_SSC_IRN ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060)) #define IFXMIPS_SSC_SFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) #define IFXMIPS_SSC_WHBGPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014)) #define IFXMIPS_SSC_STATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) #define IFXMIPS_SSC_WHBSTATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038)) #define IFXMIPS_SSC_FSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008)) #define IFXMIPS_SSC_ID ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
#define IFXMIPS_SSC_TB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0020)) #define IFXMIPS_SSC_TB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
#define IFXMIPS_SSC_RXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0030)) #define IFXMIPS_SSC_RXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
#define IFXMIPS_SSC_TXFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0034)) #define IFXMIPS_SSC_TXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
#define IFXMIPS_SSC_CON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0010)) #define IFXMIPS_SSC_CON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
#define IFXMIPS_SSC_GPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0074)) #define IFXMIPS_SSC_GPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
#define IFXMIPS_SSC_RB ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0024)) #define IFXMIPS_SSC_RB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) #define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
#define IFXMIPS_SSC_GPOCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0070)) #define IFXMIPS_SSC_GPOCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
#define IFXMIPS_SSC_BR ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0040)) #define IFXMIPS_SSC_BR ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
#define IFXMIPS_SSC_RXREQ ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0080)) #define IFXMIPS_SSC_RXREQ ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
#define IFXMIPS_SSC_SFSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0064)) #define IFXMIPS_SSC_SFSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
#define IFXMIPS_SSC_RXCNT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) #define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
/*------------ MEI */ /*------------ MEI */
#define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000) #define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000)
#define MEI_DATA_XFR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0000)) #define MEI_DATA_XFR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0000))
#define MEI_VERSION ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0004)) #define MEI_VERSION ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0004))
#define MEI_ARC_GP_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0008)) #define MEI_ARC_GP_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0008))
#define MEI_DATA_XFR_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x000C)) #define MEI_DATA_XFR_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x000C))
#define MEI_XFR_ADDR ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0010)) #define MEI_XFR_ADDR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0010))
#define MEI_MAX_WAIT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0014)) #define MEI_MAX_WAIT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0014))
#define MEI_TO_ARC_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0018)) #define MEI_TO_ARC_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0018))
#define ARC_TO_MEI_INT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x001C)) #define ARC_TO_MEI_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x001C))
#define ARC_TO_MEI_INT_MASK ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0020)) #define ARC_TO_MEI_INT_MASK ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0020))
#define MEI_DEBUG_WAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0024)) #define MEI_DEBUG_WAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0024))
#define MEI_DEBUG_RAD ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0028)) #define MEI_DEBUG_RAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0028))
#define MEI_DEBUG_DATA ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x002C)) #define MEI_DEBUG_DATA ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x002C))
#define MEI_DEBUG_DEC ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0030)) #define MEI_DEBUG_DEC ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0030))
#define MEI_CONFIG ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0034)) #define MEI_CONFIG ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0034))
#define MEI_RST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0038)) #define MEI_RST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0038))
#define MEI_DBG_MASTER ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x003C)) #define MEI_DBG_MASTER ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x003C))
#define MEI_CLK_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0040)) #define MEI_CLK_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0040))
#define MEI_BIST_CONTROL ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0044)) #define MEI_BIST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0044))
#define MEI_BIST_STAT ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0048)) #define MEI_BIST_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0048))
#define MEI_XDATA_BASE_SH ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x004c)) #define MEI_XDATA_BASE_SH ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x004c))
#define MEI_XDATA_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0050)) #define MEI_XDATA_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0050))
#define MEI_XMEM_BAR_BASE ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) #define MEI_XMEM_BAR_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
#define MEI_XMEM_BAR0 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) #define MEI_XMEM_BAR0 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
#define MEI_XMEM_BAR1 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0058)) #define MEI_XMEM_BAR1 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0058))
#define MEI_XMEM_BAR2 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x005C)) #define MEI_XMEM_BAR2 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x005C))
#define MEI_XMEM_BAR3 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0060)) #define MEI_XMEM_BAR3 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0060))
#define MEI_XMEM_BAR4 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0064)) #define MEI_XMEM_BAR4 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0064))
#define MEI_XMEM_BAR5 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0068)) #define MEI_XMEM_BAR5 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0068))
#define MEI_XMEM_BAR6 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x006C)) #define MEI_XMEM_BAR6 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x006C))
#define MEI_XMEM_BAR7 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0070)) #define MEI_XMEM_BAR7 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0070))
#define MEI_XMEM_BAR8 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0074)) #define MEI_XMEM_BAR8 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0074))
#define MEI_XMEM_BAR9 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0078)) #define MEI_XMEM_BAR9 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0078))
#define MEI_XMEM_BAR10 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x007C)) #define MEI_XMEM_BAR10 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x007C))
#define MEI_XMEM_BAR11 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0080)) #define MEI_XMEM_BAR11 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0080))
#define MEI_XMEM_BAR12 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0084)) #define MEI_XMEM_BAR12 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0084))
#define MEI_XMEM_BAR13 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0088)) #define MEI_XMEM_BAR13 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0088))
#define MEI_XMEM_BAR14 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x008C)) #define MEI_XMEM_BAR14 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x008C))
#define MEI_XMEM_BAR15 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0090)) #define MEI_XMEM_BAR15 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0090))
#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094)) #define MEI_XMEM_BAR16 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
/*------------ DEU */ /*------------ DEU */
@ -478,39 +478,39 @@
/*------------ MPS */ /*------------ MPS */
#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
#define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000)) #define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344)) #define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
#define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000)) #define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
#define IFXMIPS_MPS_VC1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0004)) #define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
#define IFXMIPS_MPS_VC2ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0008)) #define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
#define IFXMIPS_MPS_VC3ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x000C)) #define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
#define IFXMIPS_MPS_RVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0010)) #define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
#define IFXMIPS_MPS_RVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0014)) #define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
#define IFXMIPS_MPS_RVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0018)) #define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
#define IFXMIPS_MPS_RVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x001C)) #define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
#define IFXMIPS_MPS_SVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0020)) #define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
#define IFXMIPS_MPS_SVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0024)) #define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
#define IFXMIPS_MPS_SVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0028)) #define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
#define IFXMIPS_MPS_SVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x002C)) #define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
#define IFXMIPS_MPS_CVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0030)) #define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
#define IFXMIPS_MPS_CVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0034)) #define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
#define IFXMIPS_MPS_CVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0038)) #define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
#define IFXMIPS_MPS_CVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x003C)) #define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
#define IFXMIPS_MPS_RAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0040)) #define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
#define IFXMIPS_MPS_RAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0044)) #define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
#define IFXMIPS_MPS_SAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0048)) #define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
#define IFXMIPS_MPS_SAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x004C)) #define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
#define IFXMIPS_MPS_CAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0050)) #define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
#define IFXMIPS_MPS_CAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0054)) #define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
#define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058)) #define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
#define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C)) #define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) #define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) #define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28)
#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) #define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)
#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) #define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) #define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)
#endif #endif

142
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_dma.h
View File

@ -14,7 +14,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2005 infineon * Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
* *
*/ */
#ifndef _IFXMIPS_DMA_H__ #ifndef _IFXMIPS_DMA_H__
@ -56,16 +56,16 @@ enum attr_t{
#define IFXMIPS_DMA_RX -1 #define IFXMIPS_DMA_RX -1
#define IFXMIPS_DMA_TX 1 #define IFXMIPS_DMA_TX 1
typedef struct dma_chan_map { struct dma_chan_map {
const char *dev_name; const char *dev_name;
enum attr_t dir; enum attr_t dir;
int pri; int pri;
int irq; int irq;
int rel_chan_no; int rel_chan_no;
} _dma_chan_map; };
#ifdef CONFIG_CPU_LITTLE_ENDIAN #ifdef CONFIG_CPU_LITTLE_ENDIAN
typedef struct rx_desc{ struct rx_desc {
u32 data_length:16; u32 data_length:16;
volatile u32 reserved:7; volatile u32 reserved:7;
volatile u32 byte_offset:2; volatile u32 byte_offset:2;
@ -74,11 +74,10 @@ typedef struct rx_desc{
volatile u32 Res:1; volatile u32 Res:1;
volatile u32 C:1; volatile u32 C:1;
volatile u32 OWN:1; volatile u32 OWN:1;
volatile u32 Data_Pointer; volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
/* fix me:should be 28 bits here, 32 bits just for host simulation purpose */ };
}_rx_desc;
typedef struct tx_desc{ struct tx_desc {
volatile u32 data_length:16; volatile u32 data_length:16;
volatile u32 reserved1:7; volatile u32 reserved1:7;
volatile u32 byte_offset:5; volatile u32 byte_offset:5;
@ -86,14 +85,12 @@ typedef struct tx_desc{
volatile u32 SoP:1; volatile u32 SoP:1;
volatile u32 C:1; volatile u32 C:1;
volatile u32 OWN:1; volatile u32 OWN:1;
volatile u32 Data_Pointer;/* fix me:should be 28 bits here */ volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
}_tx_desc; };
#else /* BIG */ #else /* BIG */
typedef struct rx_desc{ struct rx_desc {
union union {
{ struct {
struct
{
volatile u32 OWN:1; volatile u32 OWN:1;
volatile u32 C:1; volatile u32 C:1;
volatile u32 SoP:1; volatile u32 SoP:1;
@ -102,17 +99,15 @@ typedef struct rx_desc{
volatile u32 byte_offset:2; volatile u32 byte_offset:2;
volatile u32 reserve:7; volatile u32 reserve:7;
volatile u32 data_length:16; volatile u32 data_length:16;
}field; } field;
volatile u32 word; volatile u32 word;
}status; } status;
volatile u32 Data_Pointer; volatile u32 Data_Pointer;
}_rx_desc; };
typedef struct tx_desc{ struct tx_desc {
union union {
{ struct {
struct
{
volatile u32 OWN:1; volatile u32 OWN:1;
volatile u32 C:1; volatile u32 C:1;
volatile u32 SoP:1; volatile u32 SoP:1;
@ -120,84 +115,81 @@ typedef struct tx_desc{
volatile u32 byte_offset:5; volatile u32 byte_offset:5;
volatile u32 reserved:7; volatile u32 reserved:7;
volatile u32 data_length:16; volatile u32 data_length:16;
}field; } field;
volatile u32 word; volatile u32 word;
}status; } status;
volatile u32 Data_Pointer; volatile u32 Data_Pointer;
}_tx_desc; };
#endif //ENDIAN #endif /* ENDIAN */
typedef struct dma_channel_info{ struct dma_channel_info {
/*relative channel number*/ /* relative channel number */
int rel_chan_no; int rel_chan_no;
/*class for this channel for QoS*/ /* class for this channel for QoS */
int pri; int pri;
/*specify byte_offset*/ /* specify byte_offset */
int byte_offset; int byte_offset;
/*direction*/ /* direction */
int dir; int dir;
/*irq number*/ /* irq number */
int irq; int irq;
/*descriptor parameter*/ /* descriptor parameter */
int desc_base; int desc_base;
int desc_len; int desc_len;
int curr_desc; int curr_desc;
int prev_desc;/*only used if it is a tx channel*/ int prev_desc; /* only used if it is a tx channel*/
/*weight setting for WFQ algorithm*/ /* weight setting for WFQ algorithm*/
int weight; int weight;
int default_weight; int default_weight;
int packet_size; int packet_size;
int burst_len; int burst_len;
/*on or off of this channel*/ /* on or off of this channel */
int control; int control;
/**optional information for the upper layer devices*/ /* optional information for the upper layer devices */
#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA) #if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
void* opt[64]; void *opt[64];
#else #else
void* opt[25]; void *opt[25];
#endif #endif
/*Pointer to the peripheral device who is using this channel*/ /* Pointer to the peripheral device who is using this channel */
void* dma_dev; void *dma_dev;
/*channel operations*/ /* channel operations */
void (*open)(struct dma_channel_info* pCh); void (*open)(struct dma_channel_info *pCh);
void (*close)(struct dma_channel_info* pCh); void (*close)(struct dma_channel_info *pCh);
void (*reset)(struct dma_channel_info* pCh); void (*reset)(struct dma_channel_info *pCh);
void (*enable_irq)(struct dma_channel_info* pCh); void (*enable_irq)(struct dma_channel_info *pCh);
void (*disable_irq)(struct dma_channel_info* pCh); void (*disable_irq)(struct dma_channel_info *pCh);
}_dma_channel_info; };
typedef struct dma_device_info{ struct dma_device_info {
/*device name of this peripheral*/ /* device name of this peripheral */
char device_name[15]; const char *device_name;
int reserved; int reserved;
int tx_burst_len; int tx_burst_len;
int rx_burst_len; int rx_burst_len;
int default_weight; int default_weight;
int current_tx_chan; int current_tx_chan;
int current_rx_chan; int current_rx_chan;
int num_tx_chan; int num_tx_chan;
int num_rx_chan; int num_rx_chan;
int max_rx_chan_num; int max_rx_chan_num;
int max_tx_chan_num; int max_tx_chan_num;
_dma_channel_info* tx_chan[20]; struct dma_channel_info *tx_chan[20];
_dma_channel_info* rx_chan[20]; struct dma_channel_info *rx_chan[20];
/*functions, optional*/ /*functions, optional*/
u8* (*buffer_alloc)(int len,int* offset, void** opt); u8 *(*buffer_alloc)(int len, int *offset, void **opt);
void (*buffer_free)(u8* dataptr, void* opt); void (*buffer_free)(u8 *dataptr, void *opt);
int (*intr_handler)(struct dma_device_info* info, int status); int (*intr_handler)(struct dma_device_info *info, int status);
void * priv; /* used by peripheral driver only */ void *priv; /* used by peripheral driver only */
}_dma_device_info; };
_dma_device_info* dma_device_reserve(char* dev_name); struct dma_device_info *dma_device_reserve(char *dev_name);
void dma_device_release(struct dma_device_info *dev);
void dma_device_register(struct dma_device_info *info);
void dma_device_unregister(struct dma_device_info *info);
int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
void *opt);
void dma_device_release(_dma_device_info* dev);
void dma_device_register(_dma_device_info* info);
void dma_device_unregister(_dma_device_info* info);
int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
#endif #endif

2
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ebu.h
View File

@ -13,7 +13,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/ */
#ifndef _IFXMIPS_EBU_H__ #ifndef _IFXMIPS_EBU_H__
#define _IFXMIPS_EBU_H__ #define _IFXMIPS_EBU_H__

40
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h
View File

@ -12,29 +12,29 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/ */
#ifndef _IFXMIPS_GPIO_H__ #ifndef _IFXMIPS_GPIO_H__
#define _IFXMIPS_GPIO_H__ #define _IFXMIPS_GPIO_H__
extern int ifxmips_port_reserve_pin (unsigned int port, unsigned int pin); extern int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin);
extern int ifxmips_port_free_pin (unsigned int port, unsigned int pin); extern int ifxmips_port_free_pin(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_open_drain (unsigned int port, unsigned int pin); extern int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_open_drain (unsigned int port, unsigned int pin); extern int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_pudsel (unsigned int port, unsigned int pin); extern int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin); extern int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_puden (unsigned int port, unsigned int pin); extern int ifxmips_port_set_puden(unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_puden (unsigned int port, unsigned int pin); extern int ifxmips_port_clear_puden(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_stoff (unsigned int port, unsigned int pin); extern int ifxmips_port_set_stoff(unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_stoff (unsigned int port, unsigned int pin); extern int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_dir_out (unsigned int port, unsigned int pin); extern int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_dir_in (unsigned int port, unsigned int pin); extern int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_output (unsigned int port, unsigned int pin); extern int ifxmips_port_set_output(unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_output (unsigned int port, unsigned int pin); extern int ifxmips_port_clear_output(unsigned int port, unsigned int pin);
extern int ifxmips_port_get_input (unsigned int port, unsigned int pin); extern int ifxmips_port_get_input(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_altsel0 (unsigned int port, unsigned int pin); extern int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_altsel0 (unsigned int port, unsigned int pin); extern int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin);
extern int ifxmips_port_set_altsel1 (unsigned int port, unsigned int pin); extern int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_altsel1 (unsigned int port, unsigned int pin); extern int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin);
#endif #endif

28
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h
View File

@ -141,21 +141,15 @@ struct gptu_ioctl_param {
*/ */
typedef void (*timer_callback)(unsigned long arg); typedef void (*timer_callback)(unsigned long arg);
xtern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
extern int ifxmips_free_timer(unsigned int);
extern int ifxmips_start_timer(unsigned int, int);
extern int ifxmips_stop_timer(unsigned int);
extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
extern int ifxmips_get_count_value(unsigned int, unsigned long *);
extern u32 ifxmips_cal_divider(unsigned long);
extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
u32 reload, unsigned long arg1, unsigned long arg2);
#if defined(__KERNEL__) #endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
extern int ifxmips_free_timer(unsigned int);
extern int ifxmips_start_timer(unsigned int, int);
extern int ifxmips_stop_timer(unsigned int);
extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
extern int ifxmips_get_count_value(unsigned int, unsigned long *);
extern u32 cal_divider(unsigned long);
extern int set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
extern int set_counter (unsigned int timer, unsigned int flag, u32 reload, unsigned long arg1, unsigned long arg2);
// extern int set_counter(unsigned int, int, int, int, unsigned int, unsigned int, unsigned long, unsigned long);
#endif // defined(__KERNEL__)
#endif // __DANUBE_GPTU_DEV_H__2005_07_26__10_19__

4
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
View File

@ -13,9 +13,9 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/ */
#ifndef _IFXMIPS_LED_H__ #ifndef _IFXMIPS_LED_H__
#define _IFXMIPS_LED_H__ #define _IFXMIPS_LED_H__
extern void ifxmips_led_set(unsigned int led); extern void ifxmips_led_set(unsigned int led);

16
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h
View File

@ -13,18 +13,18 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/ */
#ifndef _IFXMIPS_PMU_H__ #ifndef _IFXMIPS_PMU_H__
#define _IFXMIPS_PMU_H__ #define _IFXMIPS_PMU_H__
#define IFXMIPS_PMU_PWDCR_DMA 0x20 #define IFXMIPS_PMU_PWDCR_DMA 0x20
#define IFXMIPS_PMU_PWDCR_LED 0x800 #define IFXMIPS_PMU_PWDCR_LED 0x800
#define IFXMIPS_PMU_PWDCR_GPT 0x1000 #define IFXMIPS_PMU_PWDCR_GPT 0x1000
#define IFXMIPS_PMU_PWDCR_PPE 0x2000 #define IFXMIPS_PMU_PWDCR_PPE 0x2000
#define IFXMIPS_PMU_PWDCR_FPI 0x4000 #define IFXMIPS_PMU_PWDCR_FPI 0x4000
void ifxmips_pmu_enable (unsigned int module); void ifxmips_pmu_enable(unsigned int module);
void ifxmips_pmu_disable (unsigned int module); void ifxmips_pmu_disable(unsigned int module);
#endif #endif

4
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h
View File

@ -13,12 +13,12 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2008 John Crispin <blogic@openwrt.org> * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*/ */
#ifndef _IFXPROM_H__ #ifndef _IFXPROM_H__
#define _IFXPROM_H__ #define _IFXPROM_H__
extern void prom_printf(const char * fmt, ...); extern void prom_printf(const char *fmt, ...);
extern u32 *prom_get_cp1_base(void); extern u32 *prom_get_cp1_base(void);
extern u32 prom_get_cp1_size(void); extern u32 prom_get_cp1_size(void);
extern int ifxmips_has_brn_block(void); extern int ifxmips_has_brn_block(void);

46
target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h
View File

@ -1,5 +1,5 @@
/* /*
* include/asm-mips/mach-ifxmips/gpio.h * include/asm-mips/mach-ifxmips/gpio.h
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -25,10 +25,11 @@
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_gpio.h> #include <asm/ifxmips/ifxmips_gpio.h>
#define GPIO_TO_PORT(x) ((x > 15)?(1):(0)) #define GPIO_TO_PORT(x) ((x > 15) ? (1) : (0))
#define GPIO_TO_GPIO(x) ((x > 15)?(x-16):(x)) #define GPIO_TO_GPIO(x) ((x > 15) ? (x-16) : (x))
static inline int gpio_direction_input(unsigned gpio) { static inline int gpio_direction_input(unsigned gpio)
{
ifxmips_port_set_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_set_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
@ -36,7 +37,8 @@ static inline int gpio_direction_input(unsigned gpio) {
return 0; return 0;
} }
static inline int gpio_direction_output(unsigned gpio, int value) { static inline int gpio_direction_output(unsigned gpio, int value)
{
ifxmips_port_clear_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_open_drain(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel0(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_altsel1(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
@ -44,43 +46,53 @@ static inline int gpio_direction_output(unsigned gpio, int value) {
return 0; return 0;
} }
static inline int gpio_get_value(unsigned gpio) { static inline int gpio_get_value(unsigned gpio)
{
ifxmips_port_get_input(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_get_input(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
return 0; return 0;
} }
static inline void gpio_set_value(unsigned gpio, int value) { static inline void gpio_set_value(unsigned gpio, int value)
if(value) {
if (value)
ifxmips_port_set_output(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_set_output(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio));
else else
ifxmips_port_clear_output(GPIO_TO_PORT(gpio), GPIO_TO_GPIO(gpio)); ifxmips_port_clear_output(GPIO_TO_PORT(gpio),
GPIO_TO_GPIO(gpio));
} }
static inline int gpio_request(unsigned gpio, const char *label) { static inline int gpio_request(unsigned gpio, const char *label)
{
return 0; return 0;
} }
static inline void gpio_free(unsigned gpio) { static inline void gpio_free(unsigned gpio)
{
} }
static inline int gpio_to_irq(unsigned gpio) { static inline int gpio_to_irq(unsigned gpio)
{
return 0; return 0;
} }
static inline int irq_to_gpio(unsigned irq) { static inline int irq_to_gpio(unsigned irq)
{
return 0; return 0;
} }
static inline int gpio_cansleep(unsigned gpio) { static inline int gpio_cansleep(unsigned gpio)
{
return 0; return 0;
} }
static inline int gpio_get_value_cansleep(unsigned gpio) { static inline int gpio_get_value_cansleep(unsigned gpio)
{
might_sleep(); might_sleep();
return gpio_get_value(gpio); return gpio_get_value(gpio);
} }
static inline void gpio_set_value_cansleep(unsigned gpio, int value) { static inline void gpio_set_value_cansleep(unsigned gpio, int value)
{
might_sleep(); might_sleep();
gpio_set_value(gpio, value); gpio_set_value(gpio, value);
} }

7
target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h
View File

@ -1,5 +1,5 @@
/* /*
* include/asm-mips/mach-ifxmips/irq.h * include/asm-mips/mach-ifxmips/irq.h
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -15,15 +15,14 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
* *
*/ */
#ifndef __IFXMIPS_IRQ_H #ifndef __IFXMIPS_IRQ_H
#define __IFXMIPS_IRQ_H #define __IFXMIPS_IRQ_H
#define NR_IRQS 256 #define NR_IRQS 256
#include_next <irq.h> #include_next <irq.h>
#endif #endif