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ath79: fix qca956x SoC boot 

based on old ar71xx irq.c driver

Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
openwrt-19.07
Lucian Cristian 2018-06-04 02:09:15 +03:00 committed by John Crispin
parent e36f8b3f39
commit a0a616e1b8
1 changed files with 17 additions and 0 deletions
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17
target/linux/ath79/patches-4.14/0035-MIPS-ath79-fix-QCA956x-boot.patch Normal file
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@ -0,0 +1,17 @@
--- a/arch/mips/ath79/clock.c 2018-06-01 13:56:30.376729328 +0300
+++ b/arch/mips/ath79/clock.c 2018-06-04 02:06:57.039616840 +0300
@@ -525,6 +525,14 @@
u32 cpu_pll, ddr_pll;
u32 bootstrap;
+ /* QCA956x timer init workaround has to be applied right before setting
+ * up the clock. Else, there will be no jiffies */
+ u32 misc;
+
+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
+
bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
ref_rate = 40 * 1000 * 1000;