mirror of https://github.com/hak5/openwrt.git
bcm63xx: smp: add NAND support
NAND controller is present on BCM6328, BCM6362, BCM6368 and BCM63268. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>master
Álvaro Fernández Rojas
parent
dcee4eaa42
commit
86583384ff
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@ -2,11 +2,11 @@ include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=bcm63xx-cfe
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PKG_NAME:=bcm63xx-cfe
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PKG_VERSION:=2020-05-18
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PKG_RELEASE:=1
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PKG_RELEASE:=1
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PKG_SOURCE_URL:=https://github.com/openwrt/bcm63xx-cfe.git
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PKG_SOURCE_URL:=https://github.com/openwrt/bcm63xx-cfe.git
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PKG_SOURCE_PROTO:=git
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PKG_SOURCE_PROTO:=git
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PKG_SOURCE_DATE:=2020-05-18
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PKG_SOURCE_VERSION:=efe3b81121a84c0b8ba6a7d0d47cd5eeeb23808d
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PKG_SOURCE_VERSION:=efe3b81121a84c0b8ba6a7d0d47cd5eeeb23808d
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PKG_MIRROR_HASH:=299dcf6ef1ad034df26daee6446b574abcd7526a2fe90fb8115890e71bc0d58b
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PKG_MIRROR_HASH:=299dcf6ef1ad034df26daee6446b574abcd7526a2fe90fb8115890e71bc0d58b
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@ -4,6 +4,7 @@
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compatible = "brcm,bcm63268";
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compatible = "brcm,bcm63268";
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aliases {
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aliases {
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nflash = &nflash;
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pinctrl = &pinctrl;
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pinctrl = &pinctrl;
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serial0 = &uart0;
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serial0 = &uart0;
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serial1 = &uart1;
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serial1 = &uart1;
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@ -239,6 +240,30 @@
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/* clocks = <&clkctl 16>; */
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/* clocks = <&clkctl 16>; */
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};
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};
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nflash: nand@10000200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm6368",
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"brcm,brcmnand-v4.0",
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"brcm,brcmnand";
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reg = <0x10000200 0x180>,
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<0x10000600 0x200>,
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<0x100000b0 0x10>;
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reg-names = "nand",
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"nand-cache",
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"nand-int-base";
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interrupt-parent = <&periph_intc>;
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interrupts = <50>;
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/* clocks = <&clkctl 20>; */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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status = "disabled";
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};
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leds: led-controller@10001900 {
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leds: led-controller@10001900 {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -4,6 +4,7 @@
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compatible = "brcm,bcm6328";
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compatible = "brcm,bcm6328";
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aliases {
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aliases {
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nflash = &nflash;
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pinctrl = &pinctrl;
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pinctrl = &pinctrl;
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serial0 = &uart0;
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serial0 = &uart0;
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serial1 = &uart1;
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serial1 = &uart1;
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@ -179,6 +180,25 @@
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status = "disabled";
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status = "disabled";
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};
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};
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nflash: nand@10000200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm6368",
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"brcm,brcmnand-v2.2",
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"brcm,brcmnand";
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reg = <0x10000200 0x180>,
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<0x10000400 0x200>,
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<0x10000070 0x10>;
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reg-names = "nand",
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"nand-cache",
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"nand-int-base";
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interrupt-parent = <&periph_intc>;
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interrupts = <0>;
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status = "disabled";
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};
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leds: led-controller@10000800 {
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leds: led-controller@10000800 {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -4,6 +4,7 @@
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compatible = "brcm,bcm6362";
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compatible = "brcm,bcm6362";
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aliases {
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aliases {
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nflash = &nflash;
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pinctrl = &pinctrl;
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pinctrl = &pinctrl;
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serial0 = &uart0;
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serial0 = &uart0;
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serial1 = &uart1;
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serial1 = &uart1;
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@ -283,6 +284,30 @@
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/* clocks = <&clkctl 16>; */
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/* clocks = <&clkctl 16>; */
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};
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};
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nflash: nand@10000200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm6368",
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"brcm,brcmnand-v2.2",
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"brcm,brcmnand";
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reg = <0x10000200 0x180>,
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<0x10000600 0x200>,
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<0x10000070 0x10>;
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reg-names = "nand",
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"nand-cache",
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"nand-int-base";
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interrupt-parent = <&periph_intc>;
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interrupts = <12>;
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/* clocks = <&clkctl 20>; */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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status = "disabled";
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};
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leds: led-controller@10001900 {
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leds: led-controller@10001900 {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -4,6 +4,7 @@
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compatible = "brcm,bcm6368";
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compatible = "brcm,bcm6368";
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aliases {
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aliases {
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nflash = &nflash;
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pflash = &pflash;
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pflash = &pflash;
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pinctrl = &pinctrl;
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pinctrl = &pinctrl;
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serial0 = &uart0;
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serial0 = &uart0;
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@ -298,6 +299,27 @@
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status = "disabled";
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status = "disabled";
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};
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};
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nflash: nand@10000200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm6368",
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"brcm,brcmnand-v2.1",
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"brcm,brcmnand";
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reg = <0x10000200 0x180>,
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<0x10000600 0x200>,
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<0x10000070 0x10>;
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reg-names = "nand",
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"nand-cache",
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"nand-int-base";
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interrupt-parent = <&periph_intc>;
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interrupts = <10>;
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/* clocks = <&clkctl 17>; */
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status = "disabled";
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};
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lsspi: spi@10000800 {
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lsspi: spi@10000800 {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -105,6 +105,79 @@ define Build/cfe-bin
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$(CFE_EXTRAS) $(1)
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$(CFE_EXTRAS) $(1)
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endef
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endef
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define Build/cfe-jffs2
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$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \
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--big-endian \
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--pad \
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--no-cleanmarkers \
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--eraseblock=$(patsubst %k,%KiB,$(BLOCKSIZE)) \
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--root=$(1) \
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--output=$@ \
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--compression-mode=none
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$(call Build/pad-to,$(BLOCKSIZE))
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endef
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define Build/cfe-jffs2-cferam
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mv $@ $@.kernel
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rm -rf $@-cferam
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mkdir -p $@-cferam
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# CFE ROM checks JFFS2 dirent version of cferam.
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# If version is not > 0 it will ignore the fs entry.
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# JFFS2 sets version 0 to the first fs entry and increments
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# it on the following ones, so let's create a dummy file that
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# will have version 0 and let cferam be the second (version 1).
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touch $@-cferam/1-openwrt
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# Add cferam as the last file in the JFFS2 partition
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cp $(KDIR)/bcm63xx-cfe/$(CFE_RAM_FILE) $@-cferam/$(CFE_RAM_JFFS2_NAME)
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# The JFFS2 partition creation should result in the following
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# layout:
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# 1) 1-openwrt (version 0, ino 2)
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# 2) cferam.000 (version 1, ino 3)
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$(call Build/cfe-jffs2,$@-cferam)
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# Some devices need padding between CFE RAM and kernel
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$(if $(CFE_RAM_JFFS2_PAD),$(call Build/pad-to,$(CFE_RAM_JFFS2_PAD)))
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# Append kernel
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dd if=$@.kernel >> $@
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rm -f $@.kernel
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endef
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define Build/cfe-jffs2-kernel
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rm -rf $@-kernel
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mkdir -p $@-kernel
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# CFE RAM checks JFFS2 dirent version of vmlinux.
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# If version is not > 0 it will ignore the fs entry.
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# JFFS2 sets version 0 to the first fs entry and increments
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# it on the following ones, so let's create a dummy file that
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# will have version 0 and let cferam be the second (version 1).
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touch $@-kernel/1-openwrt
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# vmlinux is located on a different JFFS2 partition, but CFE RAM
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# ignores it, so let's create another dummy file that will match
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# the JFFS2 ino of cferam entry on the first JFFS2 partition.
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# CFE RAM won't be able to find vmlinux if cferam has the same
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# ino as vmlinux.
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touch $@-kernel/2-openwrt
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# Add vmlinux as the last file in the JFFS2 partition
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$(TOPDIR)/scripts/cfe-bin-header.py \
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--input-file $@ \
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--output-file $@-kernel/vmlinux.lz \
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--load-addr $(LOADER_ENTRY) \
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--entry-addr $(LOADER_ENTRY)
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# The JFFS2 partition creation should result in the following
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# layout:
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# 1) 1-openwrt (version 0, ino 2)
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# 2) 2-openwrt (version 1, ino 3)
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# 3) vmlinux.lz (version 2, ino 4)
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$(call Build/cfe-jffs2,$@-kernel)
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endef
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define Build/cfe-old-bin
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define Build/cfe-old-bin
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$(TOPDIR)/scripts/brcmImage.pl -t -p \
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$(TOPDIR)/scripts/brcmImage.pl -t -p \
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-o $@ -b $(CFE_BOARD_ID) -c $(CFE_CHIP_ID) \
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-o $@ -b $(CFE_BOARD_ID) -c $(CFE_CHIP_ID) \
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@ -121,6 +194,17 @@ define Build/cfe-spw303v-bin
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$(CFE_EXTRAS) $(1)
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$(CFE_EXTRAS) $(1)
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endef
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endef
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define Build/cfe-wfi-tag
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$(TOPDIR)/scripts/cfe-wfi-tag.py \
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--input-file $@ \
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--output-file $@.new \
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--version $(if $(1),$(1),$(CFE_WFI_VERSION)) \
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--chip-id $(CFE_WFI_CHIP_ID) \
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--flash-type $(CFE_WFI_FLASH_TYPE) \
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$(if $(CFE_WFI_FLAGS),--flags $(CFE_WFI_FLAGS))
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mv $@.new $@
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endef
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define Build/spw303v-bin
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define Build/spw303v-bin
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$(STAGING_DIR_HOST)/bin/spw303v -i $@ -o $@.spw303v
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$(STAGING_DIR_HOST)/bin/spw303v -i $@ -o $@.spw303v
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mv $@.spw303v $@
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mv $@.spw303v $@
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@ -170,4 +254,8 @@ USB2_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport
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include bcm63xx.mk
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include bcm63xx.mk
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ifeq ($(SUBTARGET),smp)
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include bcm63xx_nand.mk
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endif
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$(eval $(call BuildImage))
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$(eval $(call BuildImage))
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@ -0,0 +1,35 @@
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#
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# BCM63XX NAND Profiles
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#
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DEVICE_VARS += CFE_RAM_FILE
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DEVICE_VARS += CFE_RAM_JFFS2_NAME CFE_RAM_JFFS2_PAD
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DEVICE_VARS += CFE_WFI_CHIP_ID CFE_WFI_FLASH_TYPE
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DEVICE_VARS += CFE_WFI_FLAGS CFE_WFI_VERSION
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# CFE expects a single JFFS2 partition with cferam and kernel. However,
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# it's possible to fool CFE into properly loading both cferam and kernel
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# from two different JFFS2 partitions by adding dummy files (see
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# cfe-jffs2-cferam and cfe-jffs2-kernel).
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# Separate JFFS2 partitions allow upgrading openwrt without reflashing cferam
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# JFFS2 partition, which is much safer in case anything goes wrong.
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define Device/bcm63xx-nand
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FILESYSTEMS := squashfs ubifs
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KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | cfe-jffs2-kernel
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KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf
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IMAGES := cfe.bin sysupgrade.bin
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IMAGE/cfe.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | cfe-jffs2-cferam | append-ubi | cfe-wfi-tag
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IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
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KERNEL_SIZE := 5120k
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CFE_CHIP_ID :=
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CFE_RAM_FILE :=
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CFE_RAM_JFFS2_NAME :=
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CFE_RAM_JFFS2_PAD :=
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CFE_WFI_VERSION := 0x5731
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CFE_WFI_CHIP_ID = 0x$$(CFE_CHIP_ID)
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CFE_WFI_FLASH_TYPE :=
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CFE_WFI_FLAGS :=
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UBINIZE_OPTS := -E 5
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DEVICE_PACKAGES += nand-utils
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SUPPORTED_DEVICES := $(subst _,$(comma),$(1))
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endef
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@ -0,0 +1,50 @@
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -430,6 +430,23 @@ static struct clk clk_pcie = {
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};
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/*
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+ * NAND clock
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+ */
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+static void nand_set(struct clk *clk, int enable)
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+{
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+ if (BCMCPU_IS_6362())
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+ bcm_hwclock_set(CKCTL_6362_NAND_EN, enable);
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+ else if (BCMCPU_IS_6368())
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+ bcm_hwclock_set(CKCTL_6368_NAND_EN, enable);
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+ else if (BCMCPU_IS_63268())
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+ bcm_hwclock_set(CKCTL_63268_NAND_EN, enable);
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+}
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+
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+static struct clk clk_nand = {
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+ .set = nand_set,
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+};
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+
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+/*
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* Internal peripheral clock
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*/
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||||||
|
static struct clk clk_periph = {
|
||||||
|
@@ -612,6 +629,7 @@ static struct clk_lookup bcm6362_clks[]
|
||||||
|
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
|
||||||
|
CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
|
||||||
|
/* gated clocks */
|
||||||
|
+ CLKDEV_INIT(NULL, "nand", &clk_nand),
|
||||||
|
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
||||||
|
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||||
|
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||||
|
@@ -629,6 +647,7 @@ static struct clk_lookup bcm6368_clks[]
|
||||||
|
CLKDEV_INIT("10000100.serial", "refclk", &clk_periph),
|
||||||
|
CLKDEV_INIT("10000120.serial", "refclk", &clk_periph),
|
||||||
|
/* gated clocks */
|
||||||
|
+ CLKDEV_INIT(NULL, "nand", &clk_nand),
|
||||||
|
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
||||||
|
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||||
|
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||||
|
@@ -647,6 +666,7 @@ static struct clk_lookup bcm63268_clks[]
|
||||||
|
CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
|
||||||
|
CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
|
||||||
|
/* gated clocks */
|
||||||
|
+ CLKDEV_INIT(NULL, "nand", &clk_nand),
|
||||||
|
CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
|
||||||
|
CLKDEV_INIT(NULL, "usbh", &clk_usbh),
|
||||||
|
CLKDEV_INIT(NULL, "usbd", &clk_usbd),
|
||||||
|
|
@ -0,0 +1,145 @@
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
|
||||||
|
@@ -181,7 +181,8 @@ enum bcm63xx_regs_set {
|
||||||
|
RSET_PCMDMAC,
|
||||||
|
RSET_PCMDMAS,
|
||||||
|
RSET_RNG,
|
||||||
|
- RSET_MISC
|
||||||
|
+ RSET_MISC,
|
||||||
|
+ RSET_NAND
|
||||||
|
};
|
||||||
|
|
||||||
|
#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
|
||||||
|
@@ -259,6 +260,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_3368_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_3368_MISC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_3368_NAND_BASE (0xdeadbeef)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 6318 register sets base address
|
||||||
|
@@ -306,6 +308,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6318_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6318_MISC_BASE (0xb0000280)
|
||||||
|
+#define BCM_6318_NAND_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6318_OTP_BASE (0xdeadbeef)
|
||||||
|
|
||||||
|
#define BCM_6318_STRAP_BASE (0xb0000900)
|
||||||
|
@@ -356,6 +359,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6328_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6328_MISC_BASE (0xb0001800)
|
||||||
|
+#define BCM_6328_NAND_BASE (0xb0000200)
|
||||||
|
#define BCM_6328_OTP_BASE (0xb0000600)
|
||||||
|
|
||||||
|
/*
|
||||||
|
@@ -405,6 +409,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6338_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6338_MISC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6338_NAND_BASE (0xdeadbeef)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 6345 register sets base address
|
||||||
|
@@ -453,6 +458,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6345_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6345_MISC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6345_NAND_BASE (0xdeadbeef)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 6348 register sets base address
|
||||||
|
@@ -499,6 +505,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6348_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6348_MISC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6348_NAND_BASE (0xdeadbeef)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 6358 register sets base address
|
||||||
|
@@ -545,7 +552,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
|
||||||
|
#define BCM_6358_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6358_MISC_BASE (0xdeadbeef)
|
||||||
|
-
|
||||||
|
+#define BCM_6358_NAND_BASE (0xdeadbeef)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 6362 register sets base address
|
||||||
|
@@ -593,6 +600,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6362_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_6362_MISC_BASE (0xb0001800)
|
||||||
|
+#define BCM_6362_NAND_BASE (0xb0000200)
|
||||||
|
|
||||||
|
#define BCM_6362_NAND_REG_BASE (0xb0000200)
|
||||||
|
#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
|
||||||
|
@@ -648,6 +656,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
|
||||||
|
#define BCM_6368_RNG_BASE (0xb0004180)
|
||||||
|
#define BCM_6368_MISC_BASE (0xdeadbeef)
|
||||||
|
+#define BCM_6368_NAND_BASE (0xb0000200)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 63268 register sets base address
|
||||||
|
@@ -695,6 +704,7 @@ enum bcm63xx_regs_set {
|
||||||
|
#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
|
||||||
|
#define BCM_63268_RNG_BASE (0xdeadbeef)
|
||||||
|
#define BCM_63268_MISC_BASE (0xb0001800)
|
||||||
|
+#define BCM_63268_NAND_BASE (0xb0000200)
|
||||||
|
|
||||||
|
extern const unsigned long *bcm63xx_regs_base;
|
||||||
|
|
||||||
|
@@ -740,6 +750,7 @@ extern const unsigned long *bcm63xx_regs
|
||||||
|
[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
|
||||||
|
[RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
|
||||||
|
[RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
|
||||||
|
+ [RSET_NAND] = BCM_## __cpu ##_NAND_BASE, \
|
||||||
|
|
||||||
|
|
||||||
|
static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
|
||||||
|
@@ -111,5 +111,7 @@
|
||||||
|
#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
|
||||||
|
#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
|
||||||
|
#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
|
||||||
|
+#define bcm_nand_readl(o) bcm_rset_readl(RSET_NAND, (o))
|
||||||
|
+#define bcm_nand_writel(v, o) bcm_rset_writel(RSET_NAND, (v), (o))
|
||||||
|
|
||||||
|
#endif /* ! BCM63XX_IO_H_ */
|
||||||
|
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
|
||||||
|
@@ -1688,4 +1688,31 @@
|
||||||
|
#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
|
||||||
|
#define OTP_6328_REG3_TP1_DISABLED BIT(9)
|
||||||
|
|
||||||
|
+/*************************************************************************
|
||||||
|
+ * _REG relative to RSET_NAND
|
||||||
|
+ *************************************************************************/
|
||||||
|
+
|
||||||
|
+#define NAND_CS_SEL_REG 0x14
|
||||||
|
+#define NAND_CS_SEL_EBC_CS0_SEL (1 << 0)
|
||||||
|
+#define NAND_CS_SEL_EBC_CS1_SEL (1 << 1)
|
||||||
|
+#define NAND_CS_SEL_EBC_CS2_SEL (1 << 2)
|
||||||
|
+#define NAND_CS_SEL_EBC_CS3_SEL (1 << 3)
|
||||||
|
+#define NAND_CS_SEL_EBC_CS4_SEL (1 << 4)
|
||||||
|
+#define NAND_CS_SEL_EBC_CS5_SEL (1 << 5)
|
||||||
|
+#define NAND_CS_SEL_EBC_CS6_SEL (1 << 6)
|
||||||
|
+#define NAND_CS_SEL_EBC_CS7_SEL (1 << 7)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS0_USES_NAND (1 << 8)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS1_USES_NAND (1 << 9)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS2_USES_NAND (1 << 10)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS3_USES_NAND (1 << 11)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS4_USES_NAND (1 << 12)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS5_USES_NAND (1 << 13)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS6_USES_NAND (1 << 14)
|
||||||
|
+#define NAND_CS_SEL_EBI_CS7_USES_NAND (1 << 15)
|
||||||
|
+#define NAND_CS_SEL_WR_PROT_BLK0 (1 << 28)
|
||||||
|
+#define NAND_CS_SEL_AUTO_DEV_ID (1 << 30)
|
||||||
|
+#define NAND_CS_SEL_CS_LOCK (1 << 31)
|
||||||
|
+
|
||||||
|
+#define NAND_CS_XOR_REG 0x18
|
||||||
|
+
|
||||||
|
#endif /* BCM63XX_REGS_H_ */
|
||||||
|
|
@ -0,0 +1,17 @@
|
||||||
|
--- a/arch/mips/bcm63xx/dev-flash.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-flash.c
|
||||||
|
@@ -229,6 +229,14 @@ void __init bcm63xx_flash_detect(void)
|
||||||
|
}
|
||||||
|
|
||||||
|
bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);
|
||||||
|
+ } else if (flash_type == BCM63XX_FLASH_TYPE_NAND &&
|
||||||
|
+ (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
|
||||||
|
+ BCMCPU_IS_63268())) {
|
||||||
|
+ bcm_nand_writel(NAND_CS_SEL_AUTO_DEV_ID
|
||||||
|
+ | NAND_CS_SEL_EBI_CS0_USES_NAND
|
||||||
|
+ | NAND_CS_SEL_EBC_CS0_SEL,
|
||||||
|
+ NAND_CS_SEL_REG);
|
||||||
|
+ bcm_nand_writel(1, NAND_CS_XOR_REG);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,17 @@
|
||||||
|
--- a/arch/mips/bcm63xx/dev-flash.c
|
||||||
|
+++ b/arch/mips/bcm63xx/dev-flash.c
|
||||||
|
@@ -271,8 +271,12 @@ int __init bcm63xx_flash_register(void)
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
case BCM63XX_FLASH_TYPE_NAND:
|
||||||
|
- pr_warn("unsupported NAND flash detected\n");
|
||||||
|
- return -ENODEV;
|
||||||
|
+ if (board_of_device_present("nflash")) {
|
||||||
|
+ return 0;
|
||||||
|
+ } else {
|
||||||
|
+ pr_warn("unsupported NAND flash detected\n");
|
||||||
|
+ return -ENODEV;
|
||||||
|
+ }
|
||||||
|
default:
|
||||||
|
pr_err("flash detection failed for BCM%x: %d\n",
|
||||||
|
bcm63xx_get_cpu_id(), flash_type);
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/nand_base.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/nand_base.c
|
||||||
|
@@ -488,7 +488,7 @@ static int nand_do_write_oob(struct nand
|
||||||
|
|
||||||
|
nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
|
||||||
|
|
||||||
|
- if (ops->mode == MTD_OPS_RAW)
|
||||||
|
+ if (ops->mode == MTD_OPS_AUTO_OOB || ops->mode == MTD_OPS_RAW)
|
||||||
|
status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
|
||||||
|
else
|
||||||
|
status = chip->ecc.write_oob(chip, page & chip->pagemask);
|
||||||
|
|
@ -0,0 +1,42 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
@@ -1787,28 +1787,31 @@ static int brcmnand_read_by_pio(struct m
|
||||||
|
static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
|
||||||
|
struct nand_chip *chip, void *buf, u64 addr)
|
||||||
|
{
|
||||||
|
- int i, sas;
|
||||||
|
- void *oob = chip->oob_poi;
|
||||||
|
+ struct mtd_oob_region ecc;
|
||||||
|
+ int i;
|
||||||
|
int bitflips = 0;
|
||||||
|
int page = addr >> chip->page_shift;
|
||||||
|
int ret;
|
||||||
|
+ void *ecc_bytes;
|
||||||
|
void *ecc_chunk;
|
||||||
|
|
||||||
|
if (!buf)
|
||||||
|
buf = nand_get_data_buf(chip);
|
||||||
|
|
||||||
|
- sas = mtd->oobsize / chip->ecc.steps;
|
||||||
|
-
|
||||||
|
/* read without ecc for verification */
|
||||||
|
ret = chip->ecc.read_page_raw(chip, buf, true, page);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
- for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
|
||||||
|
+ for (i = 0; i < chip->ecc.steps; i++) {
|
||||||
|
ecc_chunk = buf + chip->ecc.size * i;
|
||||||
|
- ret = nand_check_erased_ecc_chunk(ecc_chunk,
|
||||||
|
- chip->ecc.size,
|
||||||
|
- oob, sas, NULL, 0,
|
||||||
|
+
|
||||||
|
+ mtd_ooblayout_ecc(mtd, i, &ecc);
|
||||||
|
+ ecc_bytes = chip->oob_poi + ecc.offset;
|
||||||
|
+
|
||||||
|
+ ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
|
||||||
|
+ ecc_bytes, ecc.length,
|
||||||
|
+ NULL, 0,
|
||||||
|
chip->ecc.strength);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
@@ -1019,11 +1019,14 @@ static int brcmnand_hamming_ooblayout_fr
|
||||||
|
if (!section) {
|
||||||
|
/*
|
||||||
|
* Small-page NAND use byte 6 for BBI while large-page
|
||||||
|
- * NAND use byte 0.
|
||||||
|
+ * NAND use bytes 0 and 1.
|
||||||
|
*/
|
||||||
|
- if (cfg->page_size > 512)
|
||||||
|
- oobregion->offset++;
|
||||||
|
- oobregion->length--;
|
||||||
|
+ if (cfg->page_size > 512) {
|
||||||
|
+ oobregion->offset += 2;
|
||||||
|
+ oobregion->length -= 2;
|
||||||
|
+ } else {
|
||||||
|
+ oobregion->length--;
|
||||||
|
+ }
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,52 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
@@ -1003,33 +1003,30 @@ static int brcmnand_hamming_ooblayout_fr
|
||||||
|
struct brcmnand_cfg *cfg = &host->hwcfg;
|
||||||
|
int sas = cfg->spare_area_size << cfg->sector_size_1k;
|
||||||
|
int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
|
||||||
|
+ u32 next;
|
||||||
|
|
||||||
|
- if (section >= sectors * 2)
|
||||||
|
+ if (section > sectors)
|
||||||
|
return -ERANGE;
|
||||||
|
|
||||||
|
- oobregion->offset = (section / 2) * sas;
|
||||||
|
+ next = (section * sas);
|
||||||
|
+ if (section < sectors)
|
||||||
|
+ next += 6;
|
||||||
|
|
||||||
|
- if (section & 1) {
|
||||||
|
- oobregion->offset += 9;
|
||||||
|
- oobregion->length = 7;
|
||||||
|
+ if (section) {
|
||||||
|
+ oobregion->offset = ((section - 1) * sas) + 9;
|
||||||
|
} else {
|
||||||
|
- oobregion->length = 6;
|
||||||
|
-
|
||||||
|
- /* First sector of each page may have BBI */
|
||||||
|
- if (!section) {
|
||||||
|
- /*
|
||||||
|
- * Small-page NAND use byte 6 for BBI while large-page
|
||||||
|
- * NAND use bytes 0 and 1.
|
||||||
|
- */
|
||||||
|
- if (cfg->page_size > 512) {
|
||||||
|
- oobregion->offset += 2;
|
||||||
|
- oobregion->length -= 2;
|
||||||
|
- } else {
|
||||||
|
- oobregion->length--;
|
||||||
|
- }
|
||||||
|
+ if (cfg->page_size > 512) {
|
||||||
|
+ /* Large page NAND uses first 2 bytes for BBI */
|
||||||
|
+ oobregion->offset = 2;
|
||||||
|
+ } else {
|
||||||
|
+ /* Small page NAND uses last byte before ECC for BBI */
|
||||||
|
+ oobregion->offset = 0;
|
||||||
|
+ next--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
+ oobregion->length = next - oobregion->offset;
|
||||||
|
+
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
@@ -269,8 +269,8 @@ enum brcmnand_reg {
|
||||||
|
BRCMNAND_FC_BASE,
|
||||||
|
};
|
||||||
|
|
||||||
|
-/* BRCMNAND v4.0 */
|
||||||
|
-static const u16 brcmnand_regs_v40[] = {
|
||||||
|
+/* BRCMNAND v3.3-v4.0 */
|
||||||
|
+static const u16 brcmnand_regs_v33[] = {
|
||||||
|
[BRCMNAND_CMD_START] = 0x04,
|
||||||
|
[BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
|
||||||
|
[BRCMNAND_CMD_ADDRESS] = 0x0c,
|
||||||
|
@@ -522,8 +522,8 @@ static int brcmnand_revision_init(struct
|
||||||
|
ctrl->reg_offsets = brcmnand_regs_v60;
|
||||||
|
else if (ctrl->nand_version >= 0x0500)
|
||||||
|
ctrl->reg_offsets = brcmnand_regs_v50;
|
||||||
|
- else if (ctrl->nand_version >= 0x0400)
|
||||||
|
- ctrl->reg_offsets = brcmnand_regs_v40;
|
||||||
|
+ else if (ctrl->nand_version >= 0x0303)
|
||||||
|
+ ctrl->reg_offsets = brcmnand_regs_v33;
|
||||||
|
|
||||||
|
/* Chip-select stride */
|
||||||
|
if (ctrl->nand_version >= 0x0701)
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
@@ -537,8 +537,9 @@ static int brcmnand_revision_init(struct
|
||||||
|
} else {
|
||||||
|
ctrl->cs_offsets = brcmnand_cs_offsets;
|
||||||
|
|
||||||
|
- /* v5.0 and earlier has a different CS0 offset layout */
|
||||||
|
- if (ctrl->nand_version <= 0x0500)
|
||||||
|
+ /* v3.3-5.0 have a different CS0 offset layout */
|
||||||
|
+ if (ctrl->nand_version >= 0x0303 &&
|
||||||
|
+ ctrl->nand_version <= 0x0500)
|
||||||
|
ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,20 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
@@ -502,7 +502,7 @@ static int brcmnand_revision_init(struct
|
||||||
|
{
|
||||||
|
static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
|
||||||
|
static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
|
||||||
|
- static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
|
||||||
|
+ static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
|
||||||
|
|
||||||
|
ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
|
||||||
|
|
||||||
|
@@ -549,7 +549,7 @@ static int brcmnand_revision_init(struct
|
||||||
|
ctrl->max_page_size = 16 * 1024;
|
||||||
|
ctrl->max_block_size = 2 * 1024 * 1024;
|
||||||
|
} else {
|
||||||
|
- ctrl->page_sizes = page_sizes;
|
||||||
|
+ ctrl->page_sizes = page_sizes_v3_4;
|
||||||
|
if (ctrl->nand_version >= 0x0600)
|
||||||
|
ctrl->block_sizes = block_sizes_v6;
|
||||||
|
else
|
||||||
|
|
@ -0,0 +1,143 @@
|
||||||
|
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||||
|
@@ -269,6 +269,36 @@ enum brcmnand_reg {
|
||||||
|
BRCMNAND_FC_BASE,
|
||||||
|
};
|
||||||
|
|
||||||
|
+/* BRCMNAND v2.1-v2.2 */
|
||||||
|
+static const u16 brcmnand_regs_v21[] = {
|
||||||
|
+ [BRCMNAND_CMD_START] = 0x04,
|
||||||
|
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
|
||||||
|
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
|
||||||
|
+ [BRCMNAND_INTFC_STATUS] = 0x5c,
|
||||||
|
+ [BRCMNAND_CS_SELECT] = 0x14,
|
||||||
|
+ [BRCMNAND_CS_XOR] = 0x18,
|
||||||
|
+ [BRCMNAND_LL_OP] = 0,
|
||||||
|
+ [BRCMNAND_CS0_BASE] = 0x40,
|
||||||
|
+ [BRCMNAND_CS1_BASE] = 0,
|
||||||
|
+ [BRCMNAND_CORR_THRESHOLD] = 0,
|
||||||
|
+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
|
||||||
|
+ [BRCMNAND_UNCORR_COUNT] = 0,
|
||||||
|
+ [BRCMNAND_CORR_COUNT] = 0,
|
||||||
|
+ [BRCMNAND_CORR_EXT_ADDR] = 0x60,
|
||||||
|
+ [BRCMNAND_CORR_ADDR] = 0x64,
|
||||||
|
+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
|
||||||
|
+ [BRCMNAND_UNCORR_ADDR] = 0x6c,
|
||||||
|
+ [BRCMNAND_SEMAPHORE] = 0x50,
|
||||||
|
+ [BRCMNAND_ID] = 0x54,
|
||||||
|
+ [BRCMNAND_ID_EXT] = 0,
|
||||||
|
+ [BRCMNAND_LL_RDATA] = 0,
|
||||||
|
+ [BRCMNAND_OOB_READ_BASE] = 0x20,
|
||||||
|
+ [BRCMNAND_OOB_READ_10_BASE] = 0,
|
||||||
|
+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
|
||||||
|
+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
|
||||||
|
+ [BRCMNAND_FC_BASE] = 0x200,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
/* BRCMNAND v3.3-v4.0 */
|
||||||
|
static const u16 brcmnand_regs_v33[] = {
|
||||||
|
[BRCMNAND_CMD_START] = 0x04,
|
||||||
|
@@ -502,12 +532,16 @@ static int brcmnand_revision_init(struct
|
||||||
|
{
|
||||||
|
static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
|
||||||
|
static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
|
||||||
|
+ static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
|
||||||
|
+ static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
|
||||||
|
static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
|
||||||
|
+ static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
|
||||||
|
+ static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
|
||||||
|
|
||||||
|
ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
|
||||||
|
|
||||||
|
- /* Only support v4.0+? */
|
||||||
|
- if (ctrl->nand_version < 0x0400) {
|
||||||
|
+ /* Only support v2.1+ */
|
||||||
|
+ if (ctrl->nand_version < 0x0201) {
|
||||||
|
dev_err(ctrl->dev, "version %#x not supported\n",
|
||||||
|
ctrl->nand_version);
|
||||||
|
return -ENODEV;
|
||||||
|
@@ -524,6 +558,8 @@ static int brcmnand_revision_init(struct
|
||||||
|
ctrl->reg_offsets = brcmnand_regs_v50;
|
||||||
|
else if (ctrl->nand_version >= 0x0303)
|
||||||
|
ctrl->reg_offsets = brcmnand_regs_v33;
|
||||||
|
+ else if (ctrl->nand_version >= 0x0201)
|
||||||
|
+ ctrl->reg_offsets = brcmnand_regs_v21;
|
||||||
|
|
||||||
|
/* Chip-select stride */
|
||||||
|
if (ctrl->nand_version >= 0x0701)
|
||||||
|
@@ -549,14 +585,27 @@ static int brcmnand_revision_init(struct
|
||||||
|
ctrl->max_page_size = 16 * 1024;
|
||||||
|
ctrl->max_block_size = 2 * 1024 * 1024;
|
||||||
|
} else {
|
||||||
|
- ctrl->page_sizes = page_sizes_v3_4;
|
||||||
|
+ if (ctrl->nand_version >= 0x0304)
|
||||||
|
+ ctrl->page_sizes = page_sizes_v3_4;
|
||||||
|
+ else if (ctrl->nand_version >= 0x0202)
|
||||||
|
+ ctrl->page_sizes = page_sizes_v2_2;
|
||||||
|
+ else
|
||||||
|
+ ctrl->page_sizes = page_sizes_v2_1;
|
||||||
|
+
|
||||||
|
if (ctrl->nand_version >= 0x0600)
|
||||||
|
ctrl->block_sizes = block_sizes_v6;
|
||||||
|
- else
|
||||||
|
+ else if (ctrl->nand_version >= 0x0400)
|
||||||
|
ctrl->block_sizes = block_sizes_v4;
|
||||||
|
+ else if (ctrl->nand_version >= 0x0202)
|
||||||
|
+ ctrl->block_sizes = block_sizes_v2_2;
|
||||||
|
+ else
|
||||||
|
+ ctrl->block_sizes = block_sizes_v2_1;
|
||||||
|
|
||||||
|
if (ctrl->nand_version < 0x0400) {
|
||||||
|
- ctrl->max_page_size = 4096;
|
||||||
|
+ if (ctrl->nand_version < 0x0202)
|
||||||
|
+ ctrl->max_page_size = 2048;
|
||||||
|
+ else
|
||||||
|
+ ctrl->max_page_size = 4096;
|
||||||
|
ctrl->max_block_size = 512 * 1024;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
@@ -724,6 +773,9 @@ static void brcmnand_wr_corr_thresh(stru
|
||||||
|
enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
|
||||||
|
int cs = host->cs;
|
||||||
|
|
||||||
|
+ if (!ctrl->reg_offsets[reg])
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
if (ctrl->nand_version == 0x0702)
|
||||||
|
bits = 7;
|
||||||
|
else if (ctrl->nand_version >= 0x0600)
|
||||||
|
@@ -782,8 +834,10 @@ static inline u32 brcmnand_spare_area_ma
|
||||||
|
return GENMASK(7, 0);
|
||||||
|
else if (ctrl->nand_version >= 0x0600)
|
||||||
|
return GENMASK(6, 0);
|
||||||
|
- else
|
||||||
|
+ else if (ctrl->nand_version >= 0x0303)
|
||||||
|
return GENMASK(5, 0);
|
||||||
|
+ else
|
||||||
|
+ return GENMASK(4, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define NAND_ACC_CONTROL_ECC_SHIFT 16
|
||||||
|
@@ -2158,9 +2212,11 @@ static int brcmnand_set_cfg(struct brcmn
|
||||||
|
|
||||||
|
tmp = nand_readreg(ctrl, acc_control_offs);
|
||||||
|
tmp &= ~brcmnand_ecc_level_mask(ctrl);
|
||||||
|
- tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
|
||||||
|
tmp &= ~brcmnand_spare_area_mask(ctrl);
|
||||||
|
- tmp |= cfg->spare_area_size;
|
||||||
|
+ if (ctrl->nand_version >= 0x0302) {
|
||||||
|
+ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
|
||||||
|
+ tmp |= cfg->spare_area_size;
|
||||||
|
+ }
|
||||||
|
nand_writereg(ctrl, acc_control_offs, tmp);
|
||||||
|
|
||||||
|
brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
|
||||||
|
@@ -2524,6 +2580,8 @@ const struct dev_pm_ops brcmnand_pm_ops
|
||||||
|
EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
|
||||||
|
|
||||||
|
static const struct of_device_id brcmnand_of_match[] = {
|
||||||
|
+ { .compatible = "brcm,brcmnand-v2.1" },
|
||||||
|
+ { .compatible = "brcm,brcmnand-v2.2" },
|
||||||
|
{ .compatible = "brcm,brcmnand-v4.0" },
|
||||||
|
{ .compatible = "brcm,brcmnand-v5.0" },
|
||||||
|
{ .compatible = "brcm,brcmnand-v6.0" },
|
||||||
|
|
@ -76,7 +76,7 @@
|
||||||
#include <bcm63xx_cpu.h>
|
#include <bcm63xx_cpu.h>
|
||||||
#include <bcm63xx_dev_flash.h>
|
#include <bcm63xx_dev_flash.h>
|
||||||
#include <bcm63xx_regs.h>
|
#include <bcm63xx_regs.h>
|
||||||
@@ -248,6 +249,13 @@ int __init bcm63xx_flash_register(void)
|
@@ -256,6 +257,13 @@ int __init bcm63xx_flash_register(void)
|
||||||
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
|
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
|
||||||
val &= MPI_CSBASE_BASE_MASK;
|
val &= MPI_CSBASE_BASE_MASK;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,17 +1,48 @@
|
||||||
CONFIG_CPU_RMAP=y
|
CONFIG_CPU_RMAP=y
|
||||||
|
CONFIG_CRC16=y
|
||||||
|
CONFIG_CRYPTO_ACOMP2=y
|
||||||
CONFIG_CRYPTO_AEAD=y
|
CONFIG_CRYPTO_AEAD=y
|
||||||
CONFIG_CRYPTO_AEAD2=y
|
CONFIG_CRYPTO_AEAD2=y
|
||||||
|
CONFIG_CRYPTO_DEFLATE=y
|
||||||
|
CONFIG_CRYPTO_HASH_INFO=y
|
||||||
CONFIG_CRYPTO_HASH2=y
|
CONFIG_CRYPTO_HASH2=y
|
||||||
|
CONFIG_CRYPTO_LZO=y
|
||||||
CONFIG_CRYPTO_MANAGER=y
|
CONFIG_CRYPTO_MANAGER=y
|
||||||
CONFIG_CRYPTO_MANAGER2=y
|
CONFIG_CRYPTO_MANAGER2=y
|
||||||
CONFIG_CRYPTO_NULL2=y
|
CONFIG_CRYPTO_NULL2=y
|
||||||
|
CONFIG_CRYPTO_ZSTD=y
|
||||||
|
CONFIG_JFFS2_FS_NAND=y
|
||||||
|
CONFIG_LZO_COMPRESS=y
|
||||||
|
CONFIG_LZO_DECOMPRESS=y
|
||||||
|
CONFIG_MTD_NAND_BRCMNAND=y
|
||||||
|
CONFIG_MTD_NAND_CORE=y
|
||||||
|
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||||
|
CONFIG_MTD_RAW_NAND=y
|
||||||
|
CONFIG_MTD_SPLIT_BCM_WFI_FW=y
|
||||||
|
CONFIG_MTD_UBI=y
|
||||||
|
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||||
|
CONFIG_MTD_UBI_BLOCK=y
|
||||||
|
# CONFIG_MTD_UBI_FASTMAP is not set
|
||||||
|
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||||
|
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||||
CONFIG_NET_FLOW_LIMIT=y
|
CONFIG_NET_FLOW_LIMIT=y
|
||||||
CONFIG_NR_CPUS=2
|
CONFIG_NR_CPUS=2
|
||||||
CONFIG_PADATA=y
|
CONFIG_PADATA=y
|
||||||
CONFIG_RCU_STALL_COMMON=y
|
CONFIG_RCU_STALL_COMMON=y
|
||||||
CONFIG_RFS_ACCEL=y
|
CONFIG_RFS_ACCEL=y
|
||||||
CONFIG_RPS=y
|
CONFIG_RPS=y
|
||||||
|
CONFIG_SGL_ALLOC=y
|
||||||
CONFIG_SMP=y
|
CONFIG_SMP=y
|
||||||
CONFIG_SMP_UP=y
|
CONFIG_SMP_UP=y
|
||||||
CONFIG_TREE_RCU=y
|
CONFIG_TREE_RCU=y
|
||||||
|
CONFIG_UBIFS_FS=y
|
||||||
|
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||||
|
CONFIG_UBIFS_FS_LZO=y
|
||||||
|
CONFIG_UBIFS_FS_ZLIB=y
|
||||||
|
CONFIG_UBIFS_FS_ZSTD=y
|
||||||
CONFIG_XPS=y
|
CONFIG_XPS=y
|
||||||
|
CONFIG_XXHASH=y
|
||||||
|
CONFIG_ZLIB_DEFLATE=y
|
||||||
|
CONFIG_ZLIB_INFLATE=y
|
||||||
|
CONFIG_ZSTD_COMPRESS=y
|
||||||
|
CONFIG_ZSTD_DECOMPRESS=y
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,17 @@
|
||||||
BOARDNAME:=smp
|
BOARDNAME:=smp
|
||||||
|
FEATURES+=nand
|
||||||
|
|
||||||
define Target/Description
|
define Target/Description
|
||||||
Build firmware images for BCM63XX boards with SMP support.
|
Build firmware images for BCM63XX boards with SMP and NAND support.
|
||||||
Currently only BCM6362 and BCM6368 supported.
|
SoCs with 2 cores:
|
||||||
|
- BCM6328 (some boards only have 1 core)
|
||||||
|
- BCM6358 (SMP unsupported due to shared TLB)
|
||||||
|
- BCM6362
|
||||||
|
- BCM6368
|
||||||
|
- BCM63268
|
||||||
|
SoCs with NAND controller:
|
||||||
|
- BCM6328 (v2.2)
|
||||||
|
- BCM6362 (v2.2)
|
||||||
|
- BCM6368 (v2.1)
|
||||||
|
- BCM63268 (v4.0)
|
||||||
endef
|
endef
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue