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* fix pci support for more than 1 device * fixes ioport mappings * adds support for arcor easybox 803/arv752DWP22 * gpio direction was not set properly during a gpio_request() * usb compile warning 

bugfix, cleanup,

SVN-Revision: 25072
lede-17.01
John Crispin 2011-01-23 12:08:44 +00:00
parent d6f4fa08eb
commit 7c9e1370e9
9 changed files with 258 additions and 145 deletions
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2
target/linux/lantiq/image/Makefile
View File

@ -60,6 +60,7 @@ define Image/BuildKernel
$(call Image/BuildKernel/Template,EASY50712,$(xway_cmdline)) $(call Image/BuildKernel/Template,EASY50712,$(xway_cmdline))
$(call Image/BuildKernel/Template,EASY50812,$(xway_cmdline)) $(call Image/BuildKernel/Template,EASY50812,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV452,$(xway_cmdline)) $(call Image/BuildKernel/Template,ARV452,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV752DPW22,$(xway_cmdline))
$(call Image/BuildKernel/Template,NONE) $(call Image/BuildKernel/Template,NONE)
endef endef
@ -68,6 +69,7 @@ define Image/Build
$(call Image/Build/$(1),$(1),EASY50712) $(call Image/Build/$(1),$(1),EASY50712)
$(call Image/Build/$(1),$(1),EASY50812) $(call Image/Build/$(1),$(1),EASY50812)
$(call Image/Build/$(1),$(1),ARV452) $(call Image/Build/$(1),$(1),ARV452)
$(call Image/Build/$(1),$(1),ARV752DPW22)
$(call Image/Build/$(1),$(1),NONE) $(call Image/Build/$(1),$(1),NONE)
$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs
endef endef

29
target/linux/lantiq/patches/101-header.patch
View File

@ -97,7 +97,7 @@
+#endif +#endif
--- /dev/null --- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -0,0 +1,36 @@ @@ -0,0 +1,51 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -122,15 +122,30 @@
+ int mii_mode; + int mii_mode;
+}; +};
+ +
+/* struct used to pass info to the pci core */ +#define PCI_EXIN0 0x0001
+enum { +#define PCI_EXIN1 0x0002
+ PCI_CLOCK_INT = 0, +#define PCI_EXIN2 0x0004
+ PCI_CLOCK_EXT +#define PCI_EXIN_SHIFT 0
+}; +
+#define PCI_GNT1 0x0008
+#define PCI_GNT2 0x0010
+#define PCI_GNT3 0x0020
+#define PCI_GNT_SHIFT 3
+
+#define PCI_REQ1 0x0040
+#define PCI_REQ2 0x0080
+#define PCI_REQ3 0x0100
+#define PCI_REQ_SHIFT 6
+
+#define PCI_CLOCK_INT 0
+#define PCI_CLOCK_EXT 1
+ +
+struct lq_pci_data { +struct lq_pci_data {
+ int clock; + int clock;
+ int req_mask; + int gpio;
+ int irq[16];
+}; +};
+ +
+extern int (*ifxmips_pci_plat_dev_init)(struct pci_dev *dev);
+
+#endif +#endif

58
target/linux/lantiq/patches/104-board_xway.patch
View File

@ -23,7 +23,7 @@
+endif +endif
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/gpio_ebu.c +++ b/arch/mips/lantiq/xway/gpio_ebu.c
@@ -0,0 +1,107 @@ @@ -0,0 +1,116 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -54,13 +54,9 @@
+} +}
+ +
+static void +static void
+lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value) +lq_ebu_apply(void)
+{ +{
+ unsigned long flags; + unsigned long flags;
+ if(value)
+ shadow |= (1 << offset);
+ else
+ shadow &= ~(1 << offset);
+ spin_lock_irqsave(&ebu_lock, flags); + spin_lock_irqsave(&ebu_lock, flags);
+ lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1); + lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1);
+ *((__u16*)virt) = shadow; + *((__u16*)virt) = shadow;
@ -68,6 +64,16 @@
+ spin_unlock_irqrestore(&ebu_lock, flags); + spin_unlock_irqrestore(&ebu_lock, flags);
+} +}
+ +
+static void
+lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ if(value)
+ shadow |= (1 << offset);
+ else
+ shadow &= ~(1 << offset);
+ lq_ebu_apply();
+}
+
+static struct gpio_chip +static struct gpio_chip
+lq_ebu_chip = +lq_ebu_chip =
+{ +{
@ -108,7 +114,10 @@
+ +
+ ret = gpiochip_add(&lq_ebu_chip); + ret = gpiochip_add(&lq_ebu_chip);
+ if (!ret) + if (!ret)
+ {
+ lq_ebu_apply();
+ return 0; + return 0;
+ }
+ +
+err_release_mem_region: +err_release_mem_region:
+ release_mem_region(res->start, resource_size(res)); + release_mem_region(res->start, resource_size(res));
@ -130,7 +139,7 @@
+ return platform_driver_register(&lq_ebu_driver); + return platform_driver_register(&lq_ebu_driver);
+} +}
+ +
+arch_initcall(init_lq_ebu); +postcore_initcall(init_lq_ebu);
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/gpio_leds.c +++ b/arch/mips/lantiq/xway/gpio_leds.c
@@ -0,0 +1,161 @@ @@ -0,0 +1,161 @@
@ -294,10 +303,10 @@
+ return ret; + return ret;
+} +}
+ +
+arch_initcall(init_lq_stp); +postcore_initcall(init_lq_stp);
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/mach-easy4010.c +++ b/arch/mips/lantiq/xway/mach-easy4010.c
@@ -0,0 +1,79 @@ @@ -0,0 +1,82 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -353,7 +362,10 @@
+ +
+static struct lq_pci_data lq_pci_data = { +static struct lq_pci_data lq_pci_data = {
+ .clock = PCI_CLOCK_INT, + .clock = PCI_CLOCK_INT,
+ .req_mask = 0xf, + .gpio = PCI_GNT1 | PCI_REQ1,
+ .irq = {
+ [14] = INT_NUM_IM0_IRL0 + 22,
+ },
+}; +};
+ +
+static struct lq_eth_data lq_eth_data = { +static struct lq_eth_data lq_eth_data = {
@ -379,7 +391,7 @@
+ easy4010_init); + easy4010_init);
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/mach-easy50712.c +++ b/arch/mips/lantiq/xway/mach-easy50712.c
@@ -0,0 +1,79 @@ @@ -0,0 +1,82 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -435,7 +447,10 @@
+ +
+static struct lq_pci_data lq_pci_data = { +static struct lq_pci_data lq_pci_data = {
+ .clock = PCI_CLOCK_INT, + .clock = PCI_CLOCK_INT,
+ .req_mask = 0xf, + .gpio = PCI_GNT1 | PCI_REQ1,
+ .irq = {
+ [14] = INT_NUM_IM0_IRL0 + 22,
+ },
+}; +};
+ +
+static struct lq_eth_data lq_eth_data = { +static struct lq_eth_data lq_eth_data = {
@ -461,7 +476,7 @@
+ easy50712_init); + easy50712_init);
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/mach-easy50812.c +++ b/arch/mips/lantiq/xway/mach-easy50812.c
@@ -0,0 +1,78 @@ @@ -0,0 +1,81 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -517,7 +532,10 @@
+ +
+static struct lq_pci_data lq_pci_data = { +static struct lq_pci_data lq_pci_data = {
+ .clock = PCI_CLOCK_INT, + .clock = PCI_CLOCK_INT,
+ .req_mask = 0xf, + .gpio = PCI_GNT1 | PCI_REQ1,
+ .irq = {
+ [14] = INT_NUM_IM0_IRL0 + 22,
+ },
+}; +};
+ +
+static struct lq_eth_data lq_eth_data = { +static struct lq_eth_data lq_eth_data = {
@ -878,7 +896,7 @@
+} +}
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/devices.h +++ b/arch/mips/lantiq/xway/devices.h
@@ -0,0 +1,24 @@ @@ -0,0 +1,25 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -891,6 +909,7 @@
+#define _LQ_DEVICES_H__ +#define _LQ_DEVICES_H__
+ +
+#include <lantiq_platform.h> +#include <lantiq_platform.h>
+#include <xway_irq.h>
+ +
+extern void __init lq_register_gpio(void); +extern void __init lq_register_gpio(void);
+extern void __init lq_register_gpio_stp(void); +extern void __init lq_register_gpio_stp(void);
@ -2867,7 +2886,7 @@
+ +
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/gpio.c +++ b/arch/mips/lantiq/xway/gpio.c
@@ -0,0 +1,203 @@ @@ -0,0 +1,206 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -2944,7 +2963,10 @@
+ printk("failed to register %s gpio\n", name); + printk("failed to register %s gpio\n", name);
+ return -EBUSY; + return -EBUSY;
+ } + }
+ gpio_direction_output(pin, dir); + if(dir)
+ gpio_direction_output(pin, 1);
+ else
+ gpio_direction_input(pin);
+ if(pin >= PINS_PER_PORT) + if(pin >= PINS_PER_PORT)
+ { + {
+ pin -= PINS_PER_PORT; + pin -= PINS_PER_PORT;
@ -3070,7 +3092,7 @@
+ return ret; + return ret;
+} +}
+ +
+arch_initcall(lq_gpio_init); +postcore_initcall(lq_gpio_init);
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/reset.c +++ b/arch/mips/lantiq/xway/reset.c
@@ -0,0 +1,53 @@ @@ -0,0 +1,53 @@

12
target/linux/lantiq/patches/110-machine.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/lantiq/setup.c --- a/arch/mips/lantiq/setup.c
+++ b/arch/mips/lantiq/setup.c +++ b/arch/mips/lantiq/setup.c
@@ -13,7 +13,8 @@ @@ -12,7 +12,8 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <lantiq.h> #include <lantiq.h>
@ -10,7 +10,15 @@
void __init void __init
plat_mem_setup(void) plat_mem_setup(void)
@@ -46,3 +47,25 @@ plat_mem_setup(void) @@ -31,6 +32,7 @@
ioport_resource.end = IOPORT_RESOURCE_END;
iomem_resource.start = IOMEM_RESOURCE_START;
iomem_resource.end = IOMEM_RESOURCE_END;
+ set_io_port_base((unsigned long) KSEG1);
while (*envp)
{
@@ -45,3 +47,25 @@
memsize *= 1024 * 1024; memsize *= 1024 * 1024;
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
} }

152
target/linux/lantiq/patches/260-pci.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/pci/Makefile --- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capc @@ -55,6 +55,7 @@
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
@ -140,7 +140,7 @@
+} +}
--- /dev/null --- /dev/null
+++ b/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c
@@ -0,0 +1,293 @@ @@ -0,0 +1,305 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -181,19 +181,19 @@
+#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8)) +#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
+#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC)) +#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
+#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000)) +#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
+#define PCI_CR_PCI_IRM ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0028))
+#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030)) +#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
+#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080)) +#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
+#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4)) +#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
+#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044)) +#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
+#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048)) +#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
+#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C)) +#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
+#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
+#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064)) +#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
+#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8)) +#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
+#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C)) +#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
+ +
+
+#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004)) +#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
+#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
+ +
+#define PCI_MASTER0_REQ_MASK_2BITS 8 +#define PCI_MASTER0_REQ_MASK_2BITS 8
+#define PCI_MASTER1_REQ_MASK_2BITS 10 +#define PCI_MASTER1_REQ_MASK_2BITS 10
@ -210,10 +210,14 @@
+ +
+u32 lq_pci_mapped_cfg; +u32 lq_pci_mapped_cfg;
+ +
+int (*lqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
+
+/* Since the PCI REQ pins can be reused for other functionality, make it possible +/* Since the PCI REQ pins can be reused for other functionality, make it possible
+ to exclude those from interpretation by the PCI controller */ + to exclude those from interpretation by the PCI controller */
+static int lq_pci_req_mask = 0xf; +static int lq_pci_req_mask = 0xf;
+ +
+static int *lq_pci_irq_map;
+
+struct pci_ops lq_pci_ops = +struct pci_ops lq_pci_ops =
+{ +{
+ .read = lq_pci_read_config_dword, + .read = lq_pci_read_config_dword,
@ -248,26 +252,9 @@
+int +int
+pcibios_plat_dev_init(struct pci_dev *dev) +pcibios_plat_dev_init(struct pci_dev *dev)
+{ +{
+ u8 pin; + if (lqpci_plat_dev_init)
+ return lqpci_plat_dev_init(dev);
+ +
+ pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+ switch(pin)
+ {
+ case 0:
+ break;
+ case 1:
+ //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
+ lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
+ lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
+ break;
+ case 2:
+ case 3:
+ case 4:
+ printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
+ default:
+ printk ("WARNING: invalid interrupt pin %d\n", pin);
+ return 1;
+ }
+ return 0; + return 0;
+} +}
+ +
@ -283,13 +270,63 @@
+ return bar11mask; + return bar11mask;
+} +}
+ +
+struct ltq_pci_gpio_map {
+ int pin;
+ int alt0;
+ int alt1;
+ int dir;
+ char *name;
+};
+
+static struct ltq_pci_gpio_map gmap[] = {
+ { 0, 1, 0, 0, "pci-exin0" },
+ { 1, 1, 0, 0, "pci-exin1" },
+ { 2, 1, 0, 0, "pci-exin2" },
+ { 30, 1, 0, 1, "pci-gnt1" },
+ { 23, 1, 0, 1, "pci-gnt2" },
+ { 19, 1, 0, 1, "pci-gnt3" },
+ { 29, 1, 0, 0, "pci-req1" },
+ { 31, 1, 0, 0, "pci-req2" },
+ { 3, 1, 0, 0, "pci-req3" },
+};
+
+static void +static void
+lq_pci_setup_clk(int external_clock) +lq_pci_setup_gpio(int gpio)
+{ +{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(gmap); i++)
+ {
+ if(gpio & (1 << i))
+ {
+ lq_gpio_request(gmap[i].pin, gmap[i].alt0,
+ gmap[i].alt1, gmap[i].dir, gmap[i].name);
+ }
+ }
+ lq_w32(lq_r32((u32*)0xBF101000) | 0x60, (u32*)0xBF101000);
+ lq_w32(lq_r32((u32*)0xBF101004) & ~2, (u32*)0xBF101004);
+ lq_w32(lq_r32((u32*)0xBF10100C) | 2, (u32*)0xBF10100C);
+ for(i = 0; i < 3; i++)
+ {
+ if(gpio & (1 << i))
+ {
+ lq_w32(lq_r32((u32*)0xBF101000) | (0x6 << (i * 4)), (u32*)0xBF101000);
+ lq_w32(lq_r32((u32*)0xBF101004) & ~(1 << i), (u32*)0xBF101004);
+ lq_w32(lq_r32((u32*)0xBF10100C) | (1 << i), (u32*)0xBF10100C);
+ }
+ }
+ lq_gpio_request(21, 0, 0, 1, "pci-reset");
+ lq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & 0x7;
+}
+
+static int __init
+lq_pci_startup(struct lq_pci_data *conf)
+{
+ u32 temp_buffer;
+
+ /* set clock to 33Mhz */ + /* set clock to 33Mhz */
+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~0xf00000, LQ_CGU_IFCCR); + lq_w32(lq_r32(LQ_CGU_IFCCR) & ~0xf00000, LQ_CGU_IFCCR);
+ lq_w32(lq_r32(LQ_CGU_IFCCR) | 0x800000, LQ_CGU_IFCCR); + lq_w32(lq_r32(LQ_CGU_IFCCR) | 0x800000, LQ_CGU_IFCCR);
+ if (external_clock) + if (conf->clock == PCI_CLOCK_EXT)
+ { + {
+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~(1 << 16), LQ_CGU_IFCCR); + lq_w32(lq_r32(LQ_CGU_IFCCR) & ~(1 << 16), LQ_CGU_IFCCR);
+ lq_w32((1 << 30), LQ_CGU_PCICR); + lq_w32((1 << 30), LQ_CGU_PCICR);
@ -297,28 +334,9 @@
+ lq_w32(lq_r32(LQ_CGU_IFCCR) | (1 << 16), LQ_CGU_IFCCR); + lq_w32(lq_r32(LQ_CGU_IFCCR) | (1 << 16), LQ_CGU_IFCCR);
+ lq_w32((1 << 31) | (1 << 30), LQ_CGU_PCICR); + lq_w32((1 << 31) | (1 << 30), LQ_CGU_PCICR);
+ } + }
+}
+
+static void
+lq_pci_setup_gpio(void)
+{
+ /* PCI reset line is gpio driven */
+ lq_gpio_request(21, 0, 0, 1, "pci-reset");
+
+ /* PCI_REQ line */
+ lq_gpio_request(29, 1, 0, 0, "pci-req");
+
+ /* PCI_GNT line */
+ lq_gpio_request(30, 1, 0, 1, "pci-gnt");
+}
+
+static int __init
+lq_pci_startup(void)
+{
+ u32 temp_buffer;
+ +
+ /* setup pci clock and gpis used by pci */ + /* setup pci clock and gpis used by pci */
+ lq_pci_setup_gpio(); + lq_pci_setup_gpio(conf->gpio);
+ +
+ /* enable auto-switching between PCI and EBU */ + /* enable auto-switching between PCI and EBU */
+ lq_w32(0xa, PCI_CR_CLK_CTRL); + lq_w32(0xa, PCI_CR_CLK_CTRL);
@ -331,7 +349,8 @@
+ +
+ /* enable external 2 PCI masters */ + /* enable external 2 PCI masters */
+ temp_buffer = lq_r32(PCI_CR_PC_ARB); + temp_buffer = lq_r32(PCI_CR_PC_ARB);
+ temp_buffer &= (~(lq_pci_req_mask << 16)); + temp_buffer &= (~((lq_pci_req_mask & 0xf) << 16));
+
+ /* enable internal arbiter */ + /* enable internal arbiter */
+ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); + temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
+ /* enable internal PCI master reqest */ + /* enable internal PCI master reqest */
@ -355,22 +374,28 @@
+ lq_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); + lq_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
+ lq_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); + lq_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
+ lq_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); + lq_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
+
+ lq_w32(lq_calc_bar11mask(), PCI_CR_BAR11MASK); + lq_w32(lq_calc_bar11mask(), PCI_CR_BAR11MASK);
+ lq_w32(0, PCI_CR_PCI_ADDR_MAP11); + lq_w32(0, PCI_CR_PCI_ADDR_MAP11);
+ lq_w32(0, PCI_CS_BASE_ADDR1); + lq_w32(0, PCI_CS_BASE_ADDR1);
+#ifdef CONFIG_SWAP_IO_SPACE +
+ /* both TX and RX endian swap are enabled */ + /* both TX and RX endian swap are enabled */
+ lq_w32(lq_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); + lq_w32(lq_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
+ wmb (); + wmb ();
+#endif +
+ /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */ + /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
+ lq_w32(lq_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK); + lq_w32(lq_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
+ lq_w32(lq_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK); + lq_w32(lq_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
+ /*use 8 dw burst length */ +
+ /* use 8 dw burst length */
+ lq_w32(0x303, PCI_CR_FCI_BURST_LENGTH); + lq_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
+ lq_w32(lq_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); + lq_w32(lq_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
+ wmb(); + wmb();
+ +
+ /* setup irq line */
+ lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
+ lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
+
+ /* toggle reset pin */ + /* toggle reset pin */
+ __gpio_set_value(21, 0); + __gpio_set_value(21, 0);
+ wmb(); + wmb();
@ -381,18 +406,10 @@
+ +
+int __init +int __init
+pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){ +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
+ switch(slot) + if(lq_pci_irq_map[slot])
+ { + return lq_pci_irq_map[slot];
+ case 13: + printk("lq_pci: trying to map irq for unknown slot %d\n", slot);
+ /* IDSEL = AD29 --> USB Host Controller */ + return 0;
+ return (INT_NUM_IM1_IRL0 + 17);
+ case 14:
+ /* IDSEL = AD30 --> mini PCI connector */
+ return (INT_NUM_IM0_IRL0 + 22);
+ default:
+ printk("lq_pci: no IRQ found for slot %d, pin %d\n", slot, pin);
+ return 0;
+ }
+} +}
+ +
+static int +static int
@ -400,17 +417,12 @@
+{ +{
+ struct lq_pci_data *lq_pci_data = (struct lq_pci_data*) pdev->dev.platform_data; + struct lq_pci_data *lq_pci_data = (struct lq_pci_data*) pdev->dev.platform_data;
+ extern int pci_probe_only; + extern int pci_probe_only;
+
+ pci_probe_only = 0; + pci_probe_only = 0;
+ lq_pci_req_mask = lq_pci_data->req_mask; + lq_pci_irq_map = lq_pci_data->irq;
+ lq_pci_setup_clk(lq_pci_data->clock); + lq_pci_startup(lq_pci_data);
+
+ lq_pci_startup();
+ lq_pci_mapped_cfg = + lq_pci_mapped_cfg =
+ (u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_BASE); + (u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_SIZE);
+ lq_pci_controller.io_map_base = + lq_pci_controller.io_map_base = mips_io_port_base + LQ_PCI_IO_BASE;
+ (unsigned long)ioremap(LQ_PCI_IO_BASE, LQ_PCI_IO_SIZE - 1);
+
+ register_pci_controller(&lq_pci_controller); + register_pci_controller(&lq_pci_controller);
+ return 0; + return 0;
+} +}

97
target/linux/lantiq/patches/400-mach-arv45xx.patch
View File

@ -1,12 +1,13 @@
--- a/arch/mips/include/asm/mach-lantiq/machine.h --- a/arch/mips/include/asm/mach-lantiq/machine.h
+++ b/arch/mips/include/asm/mach-lantiq/machine.h +++ b/arch/mips/include/asm/mach-lantiq/machine.h
@@ -11,4 +11,7 @@ @@ -11,4 +11,8 @@
LANTIQ_MACH_EASY4010, /* Twinpass evalkit */ LANTIQ_MACH_EASY4010, /* Twinpass evalkit */
LANTIQ_MACH_EASY50712, /* Danube evalkit */ LANTIQ_MACH_EASY50712, /* Danube evalkit */
LANTIQ_MACH_EASY50812, /* AR9 eval board */ LANTIQ_MACH_EASY50812, /* AR9 eval board */
+ LANTIQ_MACH_ARV4518, /* Airties WAV-221, SMC-7908A-ISP */ + LANTIQ_MACH_ARV4518, /* Airties WAV-221, SMC-7908A-ISP */
+ LANTIQ_MACH_ARV452, /* Airties WAV-281, Arcor EasyboxA800 */ + LANTIQ_MACH_ARV452, /* Airties WAV-281, Arcor EasyboxA800 */
+ LANTIQ_MACH_ARV4525, /* Speedport W502V */ + LANTIQ_MACH_ARV4525, /* Speedport W502V */
+ LANTIQ_MACH_ARV752DPW22, /* Arcor easybox a803 */
}; };
--- a/arch/mips/lantiq/xway/Kconfig --- a/arch/mips/lantiq/xway/Kconfig
+++ b/arch/mips/lantiq/xway/Kconfig +++ b/arch/mips/lantiq/xway/Kconfig
@ -30,7 +31,7 @@
+obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o +obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
--- /dev/null --- /dev/null
+++ b/arch/mips/lantiq/xway/mach-arv45xx.c +++ b/arch/mips/lantiq/xway/mach-arv45xx.c
@@ -0,0 +1,178 @@ @@ -0,0 +1,268 @@
+/* +/*
+ * This program is free software; you can redistribute it and/or modify it + * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published + * under the terms of the GNU General Public License version 2 as published
@ -58,6 +59,7 @@
+#include "devices.h" +#include "devices.h"
+ +
+#define ARV452_LATCH_SWITCH (1 << 10) +#define ARV452_LATCH_SWITCH (1 << 10)
+#define ARV752DPW22_LATCH_DEFAULT (2)
+ +
+#ifdef CONFIG_MTD_PARTITIONS +#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition arv45xx_partitions[] = +static struct mtd_partition arv45xx_partitions[] =
@ -92,9 +94,43 @@
+#endif +#endif
+}; +};
+ +
+static struct mtd_partition arv75xx_partitions[] =
+{
+ {
+ .name = "uboot",
+ .offset = 0x0,
+ .size = 0x40000,
+ },
+ {
+ .name = "uboot_env",
+ .offset = 0x40000,
+ .size = 0x10000,
+ },
+ {
+ .name = "linux",
+ .offset = 0x50000,
+ .size = 0x7a0000,
+ },
+ {
+ .name = "board_config",
+ .offset = 0x7f0000,
+ .size = 0x10000,
+ },
+};
+
+static struct physmap_flash_data arv75xx_flash_data = {
+#ifdef CONFIG_MTD_PARTITIONS
+ .nr_parts = ARRAY_SIZE(arv75xx_partitions),
+ .parts = arv75xx_partitions,
+#endif
+};
+
+static struct lq_pci_data lq_pci_data = { +static struct lq_pci_data lq_pci_data = {
+ .clock = PCI_CLOCK_EXT, + .clock = PCI_CLOCK_EXT,
+ .req_mask = 0xf, + .gpio = PCI_GNT1 | PCI_REQ1,
+ .irq = {
+ [14] = INT_NUM_IM0_IRL0 + 22,
+ },
+}; +};
+ +
+static struct lq_eth_data lq_eth_data = { +static struct lq_eth_data lq_eth_data = {
@ -144,6 +180,25 @@
+ { .name = "soc:green:online", .gpio = 9, .active_low = 1, }, + { .name = "soc:green:online", .gpio = 9, .active_low = 1, },
+}; +};
+ +
+static struct gpio_led
+arv752dpw22_leds_gpio[] __initdata = {
+ { .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:red:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:red:wps", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:red:fxo", .gpio = 35, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:red:voice", .gpio = 36, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:green:usb", .gpio = 37, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:green:wlan", .gpio = 38, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:green:wlan1", .gpio = 39, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:blue:wlan", .gpio = 40, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:blue:wlan1", .gpio = 41, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:green:eth1", .gpio = 43, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:green:eth2", .gpio = 44, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:green:eth3", .gpio = 45, .active_low = 1, .default_trigger = "default-on" },
+ { .name = "soc:green:eth4", .gpio = 46, .active_low = 1, .default_trigger = "default-on", },
+};
+
+static void +static void
+arv45xx_register_ethernet(void) +arv45xx_register_ethernet(void)
+{ +{
@ -153,6 +208,15 @@
+ lq_register_ethernet(&lq_eth_data); + lq_register_ethernet(&lq_eth_data);
+} +}
+ +
+static void
+arv75xx_register_ethernet(void)
+{
+#define ARV75XX_BRN_MAC 0x7f0016
+ memcpy_fromio(lq_eth_data.mac,
+ (void *)KSEG1ADDR(LQ_FLASH_START + ARV75XX_BRN_MAC), 6);
+ lq_register_ethernet(&lq_eth_data);
+}
+
+static void __init +static void __init
+arv4518_init(void) +arv4518_init(void)
+{ +{
@ -209,3 +273,30 @@
+ "ARV4525", + "ARV4525",
+ "ARV4525 - Speedport W502V", + "ARV4525 - Speedport W502V",
+ arv4525_init); + arv4525_init);
+
+static void __init
+arv752dpw22_init(void)
+{
+ lq_register_gpio();
+ lq_register_gpio_ebu(ARV752DPW22_LATCH_DEFAULT);
+ lq_register_asc(0);
+ lq_register_asc(1);
+ lq_register_gpio_leds(arv752dpw22_leds_gpio, ARRAY_SIZE(arv752dpw22_leds_gpio));
+ lq_register_nor(&arv75xx_flash_data);
+ lq_pci_data.irq[15] = (INT_NUM_IM2_IRL0 + 31);
+ lq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2;
+ lq_register_pci(&lq_pci_data);
+ lq_register_wdt();
+ arv75xx_register_ethernet();
+ gpio_request(32, "usb-power");
+ gpio_direction_output(32, 0);
+ mdelay(1);
+ __gpio_set_value(32, 1);
+ gpio_request(33, "relay");
+ gpio_direction_output(33, 1);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV752DPW22,
+ "ARV752DPW22",
+ "ARV752DPW22 - Arcor A803",
+ arv752dpw22_init);

8
target/linux/lantiq/patches/700-dwc_otg.patch
View File

@ -15580,7 +15580,7 @@
+xway_register_dwc(int pin) +xway_register_dwc(int pin)
+{ +{
+ lq_enable_irq(resources[1].start); + lq_enable_irq(resources[1].start);
+ platform_dev.dev.platform_data = pin; + platform_dev.dev.platform_data = (void*) pin;
+ return platform_device_register(&platform_dev); + return platform_device_register(&platform_dev);
+} +}
--- /dev/null --- /dev/null
@ -15612,8 +15612,8 @@
+#include "dev-dwc_otg.h" +#include "dev-dwc_otg.h"
#define ARV452_LATCH_SWITCH (1 << 10) #define ARV452_LATCH_SWITCH (1 << 10)
#define ARV752DPW22_LATCH_DEFAULT (2)
@@ -132,6 +133,7 @@ @@ -195,6 +196,7 @@
lq_register_pci(&lq_pci_data); lq_register_pci(&lq_pci_data);
lq_register_wdt(); lq_register_wdt();
arv45xx_register_ethernet(); arv45xx_register_ethernet();
@ -15621,7 +15621,7 @@
} }
MIPS_MACHINE(LANTIQ_MACH_ARV4518, MIPS_MACHINE(LANTIQ_MACH_ARV4518,
@@ -151,6 +153,7 @@ @@ -214,6 +216,7 @@
lq_register_pci(&lq_pci_data); lq_register_pci(&lq_pci_data);
lq_register_wdt(); lq_register_wdt();
arv45xx_register_ethernet(); arv45xx_register_ethernet();

40
target/linux/lantiq/patches/900-pci_ath5k_hook.patch
View File

@ -1,40 +0,0 @@
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/pci.h
@@ -0,0 +1,14 @@
+/*
+ * lantiq SoCs specific PCI definitions
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_LANTIQ_PCI_H
+#define __ASM_MACH_LANTIQ_PCI_H
+
+extern int (*ifxmips_pci_plat_dev_init)(struct pci_dev *dev);
+
+#endif
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -68,6 +68,8 @@
u32 lq_pci_mapped_cfg;
+int (*lqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
+
/* Since the PCI REQ pins can be reused for other functionality, make it possible
to exclude those from interpretation by the PCI controller */
static int lq_pci_req_mask = 0xf;
@@ -126,6 +128,10 @@
printk ("WARNING: invalid interrupt pin %d\n", pin);
return 1;
}
+
+ if (lqpci_plat_dev_init)
+ return lqpci_plat_dev_init(dev);
+
return 0;
}

3
target/linux/lantiq/xway/config-default
View File

@ -1,8 +1,10 @@
CONFIG_AR8216_PHY=y
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_CRYPTO_HW is not set # CONFIG_CRYPTO_HW is not set
CONFIG_HAVE_IDE=y CONFIG_HAVE_IDE=y
CONFIG_HW_HAS_PCI=y CONFIG_HW_HAS_PCI=y
CONFIG_IMAGE_CMDLINE_HACK=y CONFIG_IMAGE_CMDLINE_HACK=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_ETOP=y CONFIG_LANTIQ_ETOP=y
CONFIG_LANTIQ_MACH_ARV45XX=y CONFIG_LANTIQ_MACH_ARV45XX=y
CONFIG_LANTIQ_MACH_EASY4010=y CONFIG_LANTIQ_MACH_EASY4010=y
@ -15,6 +17,7 @@ CONFIG_LEDS_GPIO=y
# CONFIG_LOONGSON_MC146818 is not set # CONFIG_LOONGSON_MC146818 is not set
CONFIG_LOONGSON_UART_BASE=y CONFIG_LOONGSON_UART_BASE=y
CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_RTL8306_PHY=y
CONFIG_SCSI_MOD=y CONFIG_SCSI_MOD=y
CONFIG_SOC_LANTIQ=y CONFIG_SOC_LANTIQ=y
CONFIG_SOC_LANTIQ_XWAY=y CONFIG_SOC_LANTIQ_XWAY=y