mirror of https://github.com/hak5/openwrt.git
mvebu: drop armada-37xx PCI aardvark patches
These patches were necessarry for Atheros and some Intel WiFi cards. After short testing, the current upstream driver state is enough for these WiFi cards to work. If there are still some issues with other devices, the patches could be easily restored. Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>master
Tomasz Maciej Nowak
Hauke Mehrtens
parent
f72a13b537
commit
779a1c84ea
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@ -1,44 +0,0 @@
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From 5e79c0c381eb085a2aa2da175eedea1950f07520 Mon Sep 17 00:00:00 2001
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From: Tomasz Maciej Nowak <tomek_n@o2.pl>
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Date: Tue, 30 Apr 2019 15:37:34 +0200
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Subject: [PATCH] Revert "PCI: aardvark: Convert to use pci_host_probe()"
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This reverts commit c8e144f8ab00e6c4a070a932ef9c57db09aa41cf.
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---
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drivers/pci/controller/pci-aardvark.c | 12 +++++++++++-
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1 file changed, 11 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -999,6 +999,7 @@ static int advk_pcie_probe(struct platfo
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struct device *dev = &pdev->dev;
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struct advk_pcie *pcie;
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struct resource *res;
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+ struct pci_bus *bus, *child;
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struct pci_host_bridge *bridge;
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int ret, irq;
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@@ -1054,13 +1055,22 @@ static int advk_pcie_probe(struct platfo
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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- ret = pci_host_probe(bridge);
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+ ret = pci_scan_root_bus_bridge(bridge);
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if (ret < 0) {
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advk_pcie_remove_msi_irq_domain(pcie);
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advk_pcie_remove_irq_domain(pcie);
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return ret;
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}
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+ bus = bridge->bus;
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+
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+ pci_bus_size_bridges(bus);
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+ pci_bus_assign_resources(bus);
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+
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+ list_for_each_entry(child, &bus->children, node)
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+ pcie_bus_configure_settings(child);
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+
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+ pci_bus_add_devices(bus);
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return 0;
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}
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@ -1,138 +0,0 @@
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From patchwork Thu Sep 28 12:58:34 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,
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3/7] PCI: aardvark: set host and device to the same MAX payload size
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X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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X-Patchwork-Id: 819587
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Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com>
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To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
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<gregory.clement@free-electrons.com>,
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Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
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Yehuda Yitschak <yehuday@marvell.com>,
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linux-arm-kernel@lists.infradead.org, Antoine Tenart
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<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
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<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
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Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 28 Sep 2017 14:58:34 +0200
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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List-Id: <linux-pci.vger.kernel.org>
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From: Victor Gu <xigu@marvell.com>
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Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
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subsystem will not align the MAX payload size between the host and the
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device. This patch ensures that the host and device have the same MAX
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payload size, fixing a number of problems with various PCIe devices.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/controller/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 59 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -33,9 +33,11 @@
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#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
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#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
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+#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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#define PCIE_CORE_LINK_TRAINING BIT(5)
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@@ -276,7 +278,8 @@ static void advk_pcie_setup_hw(struct ad
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/* Set PCIe Device Control and Status 1 PF0 register */
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reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
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- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
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+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
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PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
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@@ -994,6 +997,58 @@ out_release_res:
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return err;
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}
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+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
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+{
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+ u8 *smpss = data;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ if (*smpss > dev->pcie_mpss)
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+ *smpss = dev->pcie_mpss;
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+
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+ return 0;
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+}
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+
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+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
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+{
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+ int mps;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
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+ pcie_set_mps(dev, mps);
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+
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+ return 0;
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+}
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+
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+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
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+{
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+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
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+ u32 reg;
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+
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+ /* Find the minimal supported MAX payload size */
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+ advk_pcie_find_smpss(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
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+
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+ /* Configure RC MAX payload size */
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+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
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+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
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+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
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+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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+
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+ /* Configure device MAX payload size */
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+ advk_pcie_bus_configure_mps(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
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+}
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+
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static int advk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -1070,6 +1125,9 @@ static int advk_pcie_probe(struct platfo
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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+ /* Configure the MAX pay load size */
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+ advk_pcie_configure_mps(bus, pcie);
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+
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pci_bus_add_devices(bus);
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return 0;
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}
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@ -1,55 +0,0 @@
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From patchwork Thu Sep 28 12:58:36 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,5/7] PCI: aardvark: disable LOS state by default
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X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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X-Patchwork-Id: 819590
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Message-Id: <20170928125838.11887-6-thomas.petazzoni@free-electrons.com>
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To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
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<gregory.clement@free-electrons.com>,
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Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
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Yehuda Yitschak <yehuday@marvell.com>,
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linux-arm-kernel@lists.infradead.org, Antoine Tenart
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<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
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<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
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Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 28 Sep 2017 14:58:36 +0200
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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List-Id: <linux-pci.vger.kernel.org>
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From: Victor Gu <xigu@marvell.com>
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Some PCIe devices do not support LOS, and will cause timeouts if the
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root complex forces the LOS state. This patch disables the LOS state
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by default.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/controller/pci-aardvark.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -347,8 +347,7 @@ static void advk_pcie_setup_hw(struct ad
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advk_pcie_wait_for_link(pcie);
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- reg = PCIE_CORE_LINK_L0S_ENTRY |
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- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
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advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
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reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
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@ -1,43 +0,0 @@
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From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
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From: Tomasz Maciej Nowak <tmn505@gmail.com>
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Date: Thu, 14 Jun 2018 14:24:40 +0200
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Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
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Use DT of_pci_get_max_link_speed() facility to allow specifying link
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capability. If none or unspecified value is given it falls back to gen2,
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which is default for Armada 3700 SoC.
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Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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---
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drivers/pci/controller/pci-aardvark.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -256,6 +256,8 @@ static void advk_pcie_wait_for_retrain(s
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static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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{
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+ struct device *dev = &pcie->pdev->dev;
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+ struct device_node *node = dev->of_node;
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u32 reg;
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/* Set to Direct mode */
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@@ -290,10 +292,15 @@ static void advk_pcie_setup_hw(struct ad
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PCIE_CORE_CTRL2_TD_ENABLE;
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advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
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- /* Set GEN2 */
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+ /* Set GEN */
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reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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reg &= ~PCIE_GEN_SEL_MSK;
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- reg |= SPEED_GEN_2;
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+ if (of_pci_get_max_link_speed(node) == 1)
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+ reg |= SPEED_GEN_1;
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+ else if (of_pci_get_max_link_speed(node) == 3)
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+ reg |= SPEED_GEN_3;
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+ else
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+ reg |= SPEED_GEN_2;
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advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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/* Set lane X1 */
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@ -1,73 +0,0 @@
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From 33f8fdcedb01680427328d710594facef7a0092c Mon Sep 17 00:00:00 2001
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From: Tomasz Maciej Nowak <tmn505@gmail.com>
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Date: Thu, 14 Jun 2018 14:40:26 +0200
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Subject: [PATCH 2/2] arm64: dts: armada-3720-espressobin: set max link to gen1
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Since the beginning there's been an issue with initializing the Atheros
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based MiniPCIe wireless cards. Here's an example of kerenel log:
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OF: PCI: host bridge /soc/pcie@d0070000 ranges:
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OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
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OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
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advk-pcie d0070000.pcie: link up
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advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
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pci_bus 0000:00: root bus resource [bus 00-ff]
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pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
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pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
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pci 0000:00:00.0: BAR 0: assigned [mem0xe8000000-0xe801ffff 64bit]
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pci 0000:00:00.0: BAR 6: assigned [mem0xe8020000-0xe802ffff pref]
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[...]
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advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
|
|
||||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x44
|
|
||||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
|
||||||
ath9k 0000:00:00.0: enabling device (0000 -> 0002)
|
|
||||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
|
|
||||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0xc
|
|
||||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
|
||||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x40
|
|
||||||
ath9k 0000:00:00.0: request_irq failed
|
|
||||||
advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
|
||||||
ath9k: probe of 0000:00:00.0 failed with error -22
|
|
||||||
|
|
||||||
The same happens for ath5k cards, while ath10k card didn't appear at
|
|
||||||
all (not detected):
|
|
||||||
|
|
||||||
OF: PCI: host bridge /soc/pcie@d0070000 ranges:
|
|
||||||
OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
|
|
||||||
OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
|
|
||||||
advk-pcie d0070000.pcie: link never came up
|
|
||||||
advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
|
|
||||||
pci_bus 0000:00: root bus resource [bus 00-ff]
|
|
||||||
pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
|
|
||||||
pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
|
|
||||||
advk-pcie d0070000.pcie: config read/write timed out
|
|
||||||
|
|
||||||
Following the issue on esppressobin.net forum [1] the workaround seems
|
|
||||||
to be limiting the speed of PCIe bridge to 1st generation. This fixed
|
|
||||||
the initialisation of all tested Atheros wireless cards.
|
|
||||||
The patch in the forum thread swaped registers which would limit speed
|
|
||||||
for all Armada 3700 based boards. The approach in this patch, in
|
|
||||||
conjunction with "PCI: aardvark: allow to specify link capability" patch
|
|
||||||
is less invasive, it only touches the affected board.
|
|
||||||
|
|
||||||
For the record, the iwlwifi and mt76 cards were not affected by this
|
|
||||||
issue.
|
|
||||||
|
|
||||||
1. http://espressobin.net/forums/topic/which-pcie-wlan-cards-are-supported
|
|
||||||
|
|
||||||
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++
|
|
||||||
1 file changed, 2 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
||||||
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
||||||
@@ -49,6 +49,8 @@
|
|
||||||
phys = <&comphy1 0>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
|
||||||
+
|
|
||||||
+ max-link-speed = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* J6 */
|
|
||||||
Loading…
Reference in New Issue