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ar71xx: fix ethernet PLL configuration for QCA956x 

QCA956x is configured like AR934x, not like the older chips.
Should fix ethernet hangs when using the WAN port without SGMII

Signed-off-by: Felix Fietkau <nbd@nbd.name>
openwrt-18.06
Felix Fietkau 2017-02-17 11:51:42 +01:00
parent d6baeb5c48
commit 72327d1757
1 changed files with 1 additions and 1 deletions
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target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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@ -1096,7 +1096,7 @@ void __init ath79_register_eth(unsigned int id)
if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII) if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
pdata->set_speed = qca956x_set_speed_sgmii; pdata->set_speed = qca956x_set_speed_sgmii;
else else
pdata->set_speed = ath79_set_speed_ge0; pdata->set_speed = ar934x_set_speed_ge0;
} else { } else {
pdata->reset_bit = QCA955X_RESET_GE1_MAC | pdata->reset_bit = QCA955X_RESET_GE1_MAC |
QCA955X_RESET_GE1_MDIO; QCA955X_RESET_GE1_MDIO;