mirror of https://github.com/hak5/openwrt.git
ralink: improve tx_timeout function
* use default timeout value * print more debug ring info * move timeout reset function to workqueue Signed-off-by: michael lee <igvtee@gmail.com> SVN-Revision: 44043lede-17.01
parent
69ee1807ed
commit
50588ef192
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@ -40,7 +40,6 @@
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#include "mdio.h"
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#include "ralink_ethtool.h"
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#define TX_TIMEOUT (2 * HZ)
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#define MAX_RX_LENGTH 1536
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#define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
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#define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
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@ -72,9 +71,11 @@ static const u32 fe_reg_table_default[FE_REG_COUNT] = {
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[FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
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[FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
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[FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
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[FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
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[FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
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[FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
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[FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
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[FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
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[FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
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[FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
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[FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
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@ -84,6 +85,11 @@ static const u32 fe_reg_table_default[FE_REG_COUNT] = {
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static const u32 *fe_reg_table = fe_reg_table_default;
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struct fe_work_t {
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int bitnr;
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void (*action)(struct fe_priv *);
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};
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static void __iomem *fe_base = 0;
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void fe_w32(u32 val, unsigned reg)
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@ -683,13 +689,11 @@ static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
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return NETDEV_TX_OK;
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}
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spin_lock(&priv->page_lock);
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tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
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tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
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if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
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{
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netif_stop_queue(dev);
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spin_unlock(&priv->page_lock);
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netif_err(priv, tx_queued,dev,
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"Tx Ring full when queue awake!\n");
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return NETDEV_TX_BUSY;
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@ -704,8 +708,6 @@ static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
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stats->tx_bytes += len;
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}
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spin_unlock(&priv->page_lock);
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return NETDEV_TX_OK;
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}
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@ -779,8 +781,8 @@ static int fe_poll_rx(struct napi_struct *napi, int budget,
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dma_unmap_single(&netdev->dev, trxd.rxd1,
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priv->rx_buf_size, DMA_FROM_DEVICE);
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pktlen = RX_DMA_PLEN0(trxd.rxd2);
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skb_put(skb, pktlen);
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skb->dev = netdev;
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skb_put(skb, pktlen);
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if (trxd.rxd4 & checksum_bit) {
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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} else {
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@ -902,7 +904,7 @@ poll_again:
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if (unlikely(netif_msg_intr(priv))) {
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mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
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netdev_info(priv->netdev,
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"done tx %d, rx %d, intr 0x%x/0x%x\n",
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"done tx %d, rx %d, intr 0x%08x/0x%x\n",
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tx_done, rx_done, status, mask);
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}
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@ -924,13 +926,27 @@ static void fe_tx_timeout(struct net_device *dev)
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priv->netdev->stats.tx_errors++;
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netif_err(priv, tx_err, dev,
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"transmit timed out, waking up the queue\n");
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netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
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"dma_ctx_idx=%u, dma_crx_idx=%u\n",
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fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
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"transmit timed out\n");
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netif_info(priv, drv, dev, "dma_cfg:%08x\n",
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fe_reg_r32(FE_REG_PDMA_GLO_CFG));
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netif_info(priv, drv, dev, "tx_ring=%d, " \
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"base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%d\n", 0,
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fe_reg_r32(FE_REG_TX_BASE_PTR0),
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fe_reg_r32(FE_REG_TX_MAX_CNT0),
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fe_reg_r32(FE_REG_TX_CTX_IDX0),
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fe_reg_r32(FE_REG_RX_CALC_IDX0));
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netif_wake_queue(dev);
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fe_reg_r32(FE_REG_TX_DTX_IDX0),
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priv->tx_free_idx
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);
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netif_info(priv, drv, dev, "rx_ring=%d, " \
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"base=%08x, max=%u, calc=%u, drx=%u\n", 0,
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fe_reg_r32(FE_REG_RX_BASE_PTR0),
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fe_reg_r32(FE_REG_RX_MAX_CNT0),
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fe_reg_r32(FE_REG_RX_CALC_IDX0),
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fe_reg_r32(FE_REG_RX_DRX_IDX0)
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);
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if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
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schedule_work(&priv->pending_work);
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}
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static irqreturn_t fe_handle_irq(int irq, void *dev)
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@ -1287,6 +1303,45 @@ static const struct net_device_ops fe_netdev_ops = {
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#endif
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};
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static void fe_reset_pending(struct fe_priv *priv)
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{
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struct net_device *dev = priv->netdev;
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int err;
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rtnl_lock();
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fe_stop(dev);
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err = fe_open(dev);
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if (err)
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goto error;
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rtnl_unlock();
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return;
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error:
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netif_alert(priv, ifup, dev,
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"Driver up/down cycle failed, closing device.\n");
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dev_close(dev);
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rtnl_unlock();
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}
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static const struct fe_work_t fe_work[] = {
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{FE_FLAG_RESET_PENDING, fe_reset_pending},
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};
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static void fe_pending_work(struct work_struct *work)
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{
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struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
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int i;
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bool pending;
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for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
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pending = test_and_clear_bit(fe_work[i].bitnr,
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priv->pending_flags);
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if (pending)
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fe_work[i].action(priv);
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}
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}
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static int fe_probe(struct platform_device *pdev)
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -1323,7 +1378,6 @@ static int fe_probe(struct platform_device *pdev)
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SET_NETDEV_DEV(netdev, &pdev->dev);
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netdev->netdev_ops = &fe_netdev_ops;
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netdev->base_addr = (unsigned long) fe_base;
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netdev->watchdog_timeo = TX_TIMEOUT;
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netdev->irq = platform_get_irq(pdev, 0);
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if (netdev->irq < 0) {
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@ -1370,6 +1424,7 @@ static int fe_probe(struct platform_device *pdev)
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err = -EINVAL;
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goto err_free_dev;
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}
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INIT_WORK(&priv->pending_work, fe_pending_work);
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netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
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fe_set_ethtool_ops(netdev);
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@ -1404,6 +1459,8 @@ static int fe_remove(struct platform_device *pdev)
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if (priv->hw_stats)
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kfree(priv->hw_stats);
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cancel_work_sync(&priv->pending_work);
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unregister_netdev(dev);
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free_netdev(dev);
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platform_set_drvdata(pdev, NULL);
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@ -33,9 +33,11 @@ enum fe_reg {
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FE_REG_TX_BASE_PTR0,
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FE_REG_TX_MAX_CNT0,
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FE_REG_TX_CTX_IDX0,
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FE_REG_TX_DTX_IDX0,
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FE_REG_RX_BASE_PTR0,
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FE_REG_RX_MAX_CNT0,
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FE_REG_RX_CALC_IDX0,
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FE_REG_RX_DRX_IDX0,
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FE_REG_FE_INT_ENABLE,
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FE_REG_FE_INT_STATUS,
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FE_REG_FE_DMA_VID_BASE,
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@ -44,7 +46,12 @@ enum fe_reg {
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FE_REG_COUNT
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};
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#define FE_DRV_VERSION "0.1.0"
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enum fe_work_flag {
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FE_FLAG_RESET_PENDING,
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FE_FLAG_MAX
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};
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#define FE_DRV_VERSION "0.1.1"
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/* power of 2 to let NEXT_TX_DESP_IDX work */
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#ifdef CONFIG_SOC_MT7621
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@ -451,6 +458,8 @@ struct fe_priv
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struct fe_hw_stats *hw_stats;
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unsigned long vlan_map;
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struct work_struct pending_work;
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DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
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};
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extern const struct of_device_id of_fe_match[];
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@ -72,9 +72,11 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = {
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[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
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[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
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[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
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@ -89,9 +91,11 @@ static const u32 mt7621_reg_table[FE_REG_COUNT] = {
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[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
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[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
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[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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[FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
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@ -33,9 +33,11 @@ static const u32 rt5350_reg_table[FE_REG_COUNT] = {
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[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
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[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
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[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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[FE_REG_FE_RST_GL] = 0,
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