mirror of https://github.com/hak5/openwrt.git
ramips: dts file cleanup
cleanup some inconsistencies in the dts files Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37783lede-17.01
parent
eb7669fc5d
commit
41f62983d3
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@ -6,10 +6,6 @@
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compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
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model = "Ralink MT7620a + MT7610e evaluation board";
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memory@0 {
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reg = <0x0 0x2000000>;
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};
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palmbus@10000000 {
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sysc@0 {
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ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
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@ -63,14 +59,14 @@
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status = "okay";
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port@4 {
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compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
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compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
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reg = <4>;
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phy-mode = "rgmii";
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phy-handle = <&phy4>;
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};
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port@5 {
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compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
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compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
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reg = <5>;
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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@ -6,13 +6,6 @@
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compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
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model = "Ralink MT7620A evaluation board";
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memory@0 {
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reg = <0x0 0x2000000>;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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palmbus@10000000 {
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sysc@0 {
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@ -6,10 +6,6 @@
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compatible = "asus,rp-n53", "ralink,mt7620a-soc";
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model = "Asus RP-N53";
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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palmbus@10000000 {
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sysc@0 {
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ralink,pinmux = "spi", "uartlite", "wled", "ephy", "i2c";
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@ -3,8 +3,6 @@
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/include/ "rt3050.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "WNCE2001", "ralink,rt3052-soc";
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model = "Netgear WNCE2001";
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@ -1,7 +1,7 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
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compatible = "ralink,rt3050-soc", "ralink,rt3050-soc", "ralink,rt3350-soc";
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cpus {
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cpu@0 {
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@ -29,12 +29,12 @@
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#size-cells = <1>;
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sysc@0 {
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compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
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compatible = "ralink,rt3050-sysc";
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reg = <0x0 0x100>;
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};
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timer@100 {
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compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
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compatible = "ralink,rt3050-timer", "ralink,rt2880-timer";
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reg = <0x100 0x20>;
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interrupt-parent = <&intc>;
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@ -42,7 +42,7 @@
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};
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watchdog@120 {
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compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
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compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt";
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reg = <0x120 0x10>;
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resets = <&rstctrl 8>;
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@ -53,7 +53,7 @@
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};
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intc: intc@200 {
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compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
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compatible = "ralink,rt3050-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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resets = <&rstctrl 19>;
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@ -67,7 +67,7 @@
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};
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memc@300 {
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compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
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compatible = "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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resets = <&rstctrl 20>;
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@ -78,7 +78,7 @@
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};
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uart@500 {
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compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
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compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0x500 0x100>;
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resets = <&rstctrl 12>;
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@ -93,7 +93,7 @@
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};
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gpio0: gpio@600 {
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compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
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reg = <0x600 0x34>;
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gpio-controller;
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@ -115,7 +115,7 @@
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};
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gpio1: gpio@638 {
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compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
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reg = <0x638 0x24>;
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gpio-controller;
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@ -131,7 +131,7 @@
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};
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gpio2: gpio@660 {
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compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
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reg = <0x660 0x24>;
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gpio-controller;
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@ -160,7 +160,7 @@
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};
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uartlite@c00 {
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compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
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compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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resets = <&rstctrl 19>;
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@ -202,7 +202,7 @@
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status = "disabled";
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port@0 {
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compatible = "lantiq,rt3883-port", "ralink,eth-port";
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compatible = "ralink,rt3883-port", "ralink,eth-port";
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reg = <0>;
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};
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