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lots of ifxmips fixes and features 

SVN-Revision: 11673
lede-17.01
John Crispin 2008-07-05 23:06:07 +00:00
parent 7866f69cbe
commit 3e2c38b0fb
18 changed files with 165 additions and 2592 deletions
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32
target/linux/ifxmips/files/arch/mips/ifxmips/board.c
View File

@ -32,7 +32,6 @@
#include <asm/io.h> #include <asm/io.h>
#include <linux/etherdevice.h> #include <linux/etherdevice.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_mii0.h>
#define MAX_BOARD_NAME_LEN 32 #define MAX_BOARD_NAME_LEN 32
#define MAX_IFXMIPS_DEVS 9 #define MAX_IFXMIPS_DEVS 9
@ -63,7 +62,8 @@ struct ifxmips_board {
spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED; spinlock_t ebu_lock = SPIN_LOCK_UNLOCKED;
EXPORT_SYMBOL_GPL(ebu_lock); EXPORT_SYMBOL_GPL(ebu_lock);
static struct ifxmips_mac ifxmips_mii_mac; static unsigned char ifxmips_mii_mac[6];
static int ifxmips_brn = 0;
static struct platform_device static struct platform_device
ifxmips_led = ifxmips_led =
@ -86,7 +86,7 @@ ifxmips_mii =
.id = 0, .id = 0,
.name = "ifxmips_mii0", .name = "ifxmips_mii0",
.dev = { .dev = {
.platform_data = &ifxmips_mii_mac, .platform_data = ifxmips_mii_mac,
} }
}; };
@ -172,9 +172,9 @@ ifxmips_set_mii0_mac(char *str)
goto out; goto out;
if((i != 5) && (str[(3 * i) + 2] != ':')) if((i != 5) && (str[(3 * i) + 2] != ':'))
goto out; goto out;
ifxmips_mii_mac.mac[i] = simple_strtoul(&str[3 * i], NULL, 16); ifxmips_mii_mac[i] = simple_strtoul(&str[3 * i], NULL, 16);
} }
if(is_valid_ether_addr(ifxmips_mii_mac.mac)) if(is_valid_ether_addr(ifxmips_mii_mac))
cmdline_mac = 1; cmdline_mac = 1;
out: out:
return 1; return 1;
@ -257,7 +257,24 @@ static struct ifxmips_board boards[] =
}, },
}; };
struct ifxmips_board* ifxmips_find_board(void) int
ifxmips_find_brn_block(void){
unsigned char temp[0];
memcpy_fromio(temp, (void*)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8);
if(memcmp(temp, "BRN-BOOT", 8) == 0)
return 1;
else
return 0;
}
int
ifxmips_has_brn_block(void)
{
return ifxmips_brn;
}
struct ifxmips_board*
ifxmips_find_board(void)
{ {
int i; int i;
if(!*board_name) if(!*board_name)
@ -274,9 +291,10 @@ ifxmips_init_devices(void)
struct ifxmips_board *board = ifxmips_find_board(); struct ifxmips_board *board = ifxmips_find_board();
chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID); chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID);
ifxmips_brn = ifxmips_find_brn_block();
if(!cmdline_mac) if(!cmdline_mac)
random_ether_addr(ifxmips_mii_mac.mac); random_ether_addr(ifxmips_mii_mac);
if(!board) if(!board)
{ {

279
target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
View File

@ -31,46 +31,45 @@
#include <linux/errno.h> #include <linux/errno.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#define FIX_FOR_36M_CRYSTAL 1
#define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000 #define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000
#define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000 #define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000
#define BASIS_INPUT_CRYSTAL_USB 12000000 #define BASIS_INPUT_CRYSTAL_USB 12000000
#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) #define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
#define CGU_PLL0_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
#define CGU_PLL0_BYPASS (*IFXMIPS_CGU_PLL0_CFG & (1 << 30)) #define CGU_PLL0_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
#define CGU_PLL0_SRC (*IFXMIPS_CGU_PLL0_CFG & (1 << 29)) #define CGU_PLL0_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
#define CGU_PLL0_CFG_DSMSEL (*IFXMIPS_CGU_PLL0_CFG & (1 << 28)) #define CGU_PLL0_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
#define CGU_PLL0_CFG_FRAC_EN (*IFXMIPS_CGU_PLL0_CFG & (1 << 27)) #define CGU_PLL0_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
#define CGU_PLL1_SRC (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
#define CGU_PLL1_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
#define CGU_PLL1_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
#define CGU_PLL1_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
#define CGU_PLL2_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
#define CGU_PLL2_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
#define CGU_SYS_FPI_SEL (1 << 6)
#define CGU_SYS_DDR_SEL 0x3
#define CGU_PLL0_SRC (1 << 29)
#define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17) #define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
#define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6) #define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
#define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2) #define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
#define CGU_PLL1_SRC (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
#define CGU_PLL1_BYPASS (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
#define CGU_PLL1_CFG_DSMSEL (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
#define CGU_PLL1_CFG_FRAC_EN (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
#define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17) #define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
#define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6) #define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
#define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2) #define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
#define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
#define CGU_PLL2_BYPASS (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
#define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17) #define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13) #define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
#define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6) #define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
#define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2) #define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
#define CGU_SYS_PPESEL GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
#define CGU_SYS_FPI_SEL (*IFXMIPS_CGU_SYS & (1 << 6))
#define CGU_SYS_CPU1SEL GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
#define CGU_SYS_CPU0SEL GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
#define CGU_SYS_DDR_SEL GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20) #define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
#define CGU_IF_CLK_USBSEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
#define CGU_IF_CLK_MIISEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
static unsigned int cgu_get_pll0_fdiv(void); static unsigned int cgu_get_pll0_fdiv(void);
unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
static inline unsigned int static inline unsigned int
get_input_clock(int pll) get_input_clock(int pll)
@ -78,7 +77,7 @@ get_input_clock(int pll)
switch(pll) switch(pll)
{ {
case 0: case 0:
if(CGU_PLL0_SRC) if(ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
return BASIS_INPUT_CRYSTAL_USB; return BASIS_INPUT_CRYSTAL_USB;
else if(CGU_PLL0_PHASE_DIVIDER_ENABLE) else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
return BASIC_INPUT_CLOCK_FREQUENCY_1; return BASIC_INPUT_CLOCK_FREQUENCY_1;
@ -169,134 +168,18 @@ cgu_get_pll0_fosc(void)
CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE); CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
} }
static inline unsigned int
cgu_get_pll0_fps(int phase)
{
register unsigned int fps = cgu_get_pll0_fosc();
switch(phase)
{
case 1:
/* 1.25 */
fps = ((fps << 2) + 2) / 5;
break;
case 2:
/* 1.5 */
fps = ((fps << 1) + 1) / 3;
break;
}
return fps;
}
static unsigned int static unsigned int
cgu_get_pll0_fdiv(void) cgu_get_pll0_fdiv(void)
{ {
register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
return (cgu_get_pll0_fosc() + (div >> 1)) / div; return (cgu_get_pll0_fosc() + (div >> 1)) / div;
} }
static inline unsigned int
cgu_get_pll1_fosc(void)
{
if(CGU_PLL1_BYPASS)
return get_input_clock(1);
else
return !CGU_PLL1_CFG_FRAC_EN
? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
: dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
}
static inline unsigned int
cgu_get_pll1_fps(void)
{
register unsigned int fps = cgu_get_pll1_fosc();
return ((fps << 1) + 1) / 3;
}
static inline unsigned int
cgu_get_pll1_fdiv(void)
{
return cgu_get_pll1_fosc();
}
static inline unsigned int
cgu_get_pll2_fosc(void)
{
u64 res, clock = get_input_clock(2);
if ( CGU_PLL2_BYPASS )
return get_input_clock(2);
res = (CGU_PLL2_CFG_PLLN + 1) * clock;
do_div(res, CGU_PLL2_CFG_PLLM + 1);
return res;
}
static inline unsigned int
cgu_get_pll2_fps(int phase)
{
register unsigned int fps = cgu_get_pll2_fosc();
switch ( phase )
{
case 1:
/* 1.125 */
fps = ((fps << 2) + 2) / 5; break;
case 2:
/* 1.25 */
fps = ((fps << 3) + 4) / 9;
}
return fps;
}
static inline unsigned int
cgu_get_pll2_fdiv(void)
{
register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
return (cgu_get_pll2_fosc() + (div >> 1)) / div;
}
unsigned int
cgu_get_mips_clock(int cpu)
{
register unsigned int ret = cgu_get_pll0_fosc();
register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
if(cpusel == 0)
return ret;
else if(cpusel == 2)
ret <<= 1;
switch(CGU_SYS_DDR_SEL)
{
default:
case 0:
return (ret + 1) / 2;
case 1:
return (ret * 2 + 2) / 5;
case 2:
return (ret + 1) / 3;
case 3:
return (ret + 2) / 4;
}
}
unsigned int
cgu_get_cpu_clock(void)
{
return cgu_get_mips_clock(0);
}
unsigned int unsigned int
cgu_get_io_region_clock(void) cgu_get_io_region_clock(void)
{ {
register unsigned int ret = cgu_get_pll0_fosc(); register unsigned int ret = cgu_get_pll0_fosc();
switch(ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL)
switch(CGU_SYS_DDR_SEL)
{ {
default: default:
case 0: case 0:
@ -314,112 +197,16 @@ unsigned int
cgu_get_fpi_bus_clock(int fpi) cgu_get_fpi_bus_clock(int fpi)
{ {
register unsigned int ret = cgu_get_io_region_clock(); register unsigned int ret = cgu_get_io_region_clock();
if((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
if((fpi == 2) && (CGU_SYS_FPI_SEL))
ret >>= 1; ret >>= 1;
return ret; return ret;
} }
unsigned int
cgu_get_pp32_clock(void)
{
switch(CGU_SYS_PPESEL)
{
default:
case 0:
return cgu_get_pll2_fps(1);
case 1:
return cgu_get_pll2_fps(2);
case 2:
return (cgu_get_pll2_fps(1) + 1) >> 1;
case 3:
return (cgu_get_pll2_fps(2) + 1) >> 1;
}
}
unsigned int
cgu_get_ethernet_clock(int mii)
{
switch(CGU_IF_CLK_MIISEL)
{
case 0:
return (cgu_get_pll2_fosc() + 3) / 12;
case 1:
return (cgu_get_pll2_fosc() + 3) / 6;
case 2:
return 50000000;
case 3:
return 25000000;
}
return 0;
}
unsigned int
cgu_get_usb_clock(void)
{
switch(CGU_IF_CLK_USBSEL)
{
case 0:
return (cgu_get_pll2_fosc() + 12) / 25;
case 1:
return 12000000;
case 2:
return 12000000 / 4;
case 3:
return 12000000;
}
return 0;
}
unsigned int
cgu_get_clockout(int clkout)
{
unsigned int fosc1 = cgu_get_pll1_fosc();
unsigned int fosc2 = cgu_get_pll2_fosc();
if(clkout > 3 || clkout < 0)
return 0;
switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
{
case 0: /* 32.768KHz */
case 15:
return (fosc1 + 6000) / 12000;
case 1: /* 1.536MHz */
return (fosc1 + 128) / 256;
case 2: /* 2.5MHz */
return (fosc2 + 60) / 120;
case 3: /* 12MHz */
case 5:
case 12:
return (fosc2 + 12) / 25;
case 4: /* 40MHz */
return (cgu_get_pll2_fps(2) + 3) / 6;
case 6: /* 24MHz */
return (cgu_get_pll2_fps(2) + 5) / 10;
case 7: /* 48MHz */
return (cgu_get_pll2_fps(2) + 2) / 5;
case 8: /* 25MHz */
case 14:
return (fosc2 + 6) / 12;
case 9: /* 50MHz */
case 13:
return (fosc2 + 3) / 6;
case 10:/* 30MHz */
return (fosc2 + 5) / 10;
case 11:/* 60MHz */
return (fosc2 + 2) / 5;
}
return 0;
}
void cgu_setup_pci_clk(int external_clock) void cgu_setup_pci_clk(int external_clock)
{ {
//set clock to 33Mhz //set clock to 33Mhz
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR); ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR); ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
// internal or external clock
if(external_clock) if(external_clock)
{ {
ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR); ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~ (1 << 16), IFXMIPS_CGU_IFCCR);
@ -430,26 +217,10 @@ void cgu_setup_pci_clk(int external_clock)
} }
} }
unsigned int
ifxmips_get_ddr_hz(void)
{
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
{
case 0:
return CLOCK_167M;
case 1:
return CLOCK_133M;
case 2:
return CLOCK_111M;
}
return CLOCK_83M;
}
EXPORT_SYMBOL(ifxmips_get_ddr_hz);
unsigned int unsigned int
ifxmips_get_cpu_hz(void) ifxmips_get_cpu_hz(void)
{ {
unsigned int ddr_clock = ifxmips_get_ddr_hz(); unsigned int ddr_clock = DDR_HZ;
switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) switch(ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
{ {
case 0: case 0:
@ -464,11 +235,9 @@ EXPORT_SYMBOL(ifxmips_get_cpu_hz);
unsigned int unsigned int
ifxmips_get_fpi_hz(void) ifxmips_get_fpi_hz(void)
{ {
unsigned int ddr_clock = ifxmips_get_ddr_hz(); unsigned int ddr_clock = DDR_HZ;
if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40) if(ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
return ddr_clock >> 1; return ddr_clock >> 1;
return ddr_clock; return ddr_clock;
} }
EXPORT_SYMBOL(ifxmips_get_fpi_hz); EXPORT_SYMBOL(ifxmips_get_fpi_hz);

1
target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
View File

@ -39,7 +39,6 @@
#include <asm/semaphore.h> #include <asm/semaphore.h>
#include <asm/uaccess.h> #include <asm/uaccess.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_ioctl.h>
#define MAX_PORTS 2 #define MAX_PORTS 2
#define PINS_PER_PORT 16 #define PINS_PER_PORT 16

3
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
View File

@ -18,6 +18,7 @@
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/module.h>
#include <linux/bootmem.h> #include <linux/bootmem.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
@ -83,11 +84,13 @@ unsigned int *prom_get_cp1_base(void)
{ {
return prom_cp1_base; return prom_cp1_base;
} }
EXPORT_SYMBOL(prom_get_cp1_base);
unsigned int prom_get_cp1_size(void) unsigned int prom_get_cp1_size(void)
{ {
return prom_cp1_size; return prom_cp1_size;
} }
EXPORT_SYMBOL(prom_get_cp1_size);
void __init void __init
prom_init(void) prom_init(void)

37
target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
View File

@ -27,6 +27,7 @@
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
#include <linux/mtd/cfi.h> #include <linux/mtd/cfi.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_prom.h>
#include <asm/ifxmips/ifxmips_ebu.h> #include <asm/ifxmips/ifxmips_ebu.h>
#include <linux/magic.h> #include <linux/magic.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
@ -90,14 +91,14 @@ ifxmips_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_
} }
static struct mtd_partition static struct mtd_partition
ifxmips_partitions[4] = { ifxmips_partitions[] = {
{ {
name:"U-Boot", name:"uboot",
offset:0x00000000, offset:0x00000000,
size:0x00020000, size:0x00020000,
}, },
{ {
name:"U-Boot-Env", name:"uboot_env",
offset:0x00020000, offset:0x00020000,
size:0x00010000, size:0x00010000,
}, },
@ -111,6 +112,11 @@ ifxmips_partitions[4] = {
offset:0x0, offset:0x0,
size:0x0, size:0x0,
}, },
{
name:"board_config",
offset:0x0,
size:0x0,
},
}; };
int int
@ -121,6 +127,18 @@ find_uImage_size(unsigned long start_offset){
return temp + 0x40; return temp + 0x40;
} }
int
find_brn_block(unsigned long start_offset){
unsigned char temp[9];
ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 8);
temp[8] = '\0';
printk(KERN_INFO "data in brn block %s\n", temp);
if(memcmp(temp, "BRN-BOOT", 8) == 0)
return 1;
else
return 0;
}
int int
detect_squashfs_partition(unsigned long start_offset){ detect_squashfs_partition(unsigned long start_offset){
unsigned long temp; unsigned long temp;
@ -170,12 +188,19 @@ ifxmips_mtd_probe(struct platform_device *dev)
uimage_size += 0x10000; uimage_size += 0x10000;
} }
parts = &ifxmips_partitions[0];
ifxmips_partitions[2].size = uimage_size; ifxmips_partitions[2].size = uimage_size;
ifxmips_partitions[3].offset = ifxmips_partitions[2].offset + ifxmips_partitions[2].size; ifxmips_partitions[3].offset = ifxmips_partitions[2].offset + ifxmips_partitions[2].size;
ifxmips_partitions[3].size = ((ifxmips_mtd->size >> 20) * 1024 * 1024) - ifxmips_partitions[3].offset; ifxmips_partitions[3].size = ((ifxmips_mtd->size >> 20) * 1024 * 1024) - ifxmips_partitions[3].offset;
if(ifxmips_has_brn_block())
parts = &ifxmips_partitions[0]; {
add_mtd_partitions(ifxmips_mtd, parts, 4); ifxmips_partitions[3].size -= ifxmips_mtd->erasesize;
ifxmips_partitions[4].offset = ifxmips_mtd->size - ifxmips_mtd->erasesize;
ifxmips_partitions[4].size = ifxmips_mtd->erasesize;
add_mtd_partitions(ifxmips_mtd, parts, 5);
} else {
add_mtd_partitions(ifxmips_mtd, parts, 4);
}
printk(KERN_INFO "ifxmips_mtd: added ifxmips flash with %dMB\n", ifxmips_mtd->size >> 20); printk(KERN_INFO "ifxmips_mtd: added ifxmips flash with %dMB\n", ifxmips_mtd->size >> 20);
return 0; return 0;

12
target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
View File

@ -36,10 +36,15 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/delay.h> #include <asm/delay.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_mii0.h>
#include <asm/ifxmips/ifxmips_dma.h> #include <asm/ifxmips/ifxmips_dma.h>
#include <asm/ifxmips/ifxmips_pmu.h> #include <asm/ifxmips/ifxmips_pmu.h>
struct ifxmips_mii_priv {
struct net_device_stats stats;
struct dma_device_info *dma_device;
struct sk_buff *skb;
};
static struct net_device *ifxmips_mii0_dev; static struct net_device *ifxmips_mii0_dev;
static unsigned char mac_addr[MAX_ADDR_LEN]; static unsigned char mac_addr[MAX_ADDR_LEN];
@ -63,6 +68,7 @@ ifxmips_read_mdio(u32 phy_addr, u32 phy_reg)
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET); ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){}; while(ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK; val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
@ -343,10 +349,10 @@ static int
ifxmips_mii_probe(struct platform_device *dev) ifxmips_mii_probe(struct platform_device *dev)
{ {
int result = 0; int result = 0;
struct ifxmips_mac *mac = (struct ifxmips_mac*)dev->dev.platform_data; unsigned char *mac = (unsigned char*)dev->dev.platform_data;
ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv)); ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv));
ifxmips_mii0_dev->init = ifxmips_mii_dev_init; ifxmips_mii0_dev->init = ifxmips_mii_dev_init;
memcpy(mac_addr, mac->mac, 6); memcpy(mac_addr, mac, 6);
strcpy(ifxmips_mii0_dev->name, "eth%d"); strcpy(ifxmips_mii0_dev->name, "eth%d");
ifxmips_mii_chip_init(REV_MII_MODE); ifxmips_mii_chip_init(REV_MII_MODE);
result = register_netdev(ifxmips_mii0_dev); result = register_netdev(ifxmips_mii0_dev);

13
target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
View File

@ -48,7 +48,6 @@
#include <asm/bitops.h> #include <asm/bitops.h>
#include <asm/ifxmips/ifxmips.h> #include <asm/ifxmips/ifxmips.h>
#include <asm/ifxmips/ifxmips_irq.h> #include <asm/ifxmips/ifxmips_irq.h>
#include <asm/ifxmips/ifxmips_serial.h>
#define PORT_IFXMIPSASC 111 #define PORT_IFXMIPSASC 111
@ -161,7 +160,7 @@ ifxmipsasc_tx_chars(struct uart_port *port)
} }
while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL) >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL)
{ {
if(port->x_char) if(port->x_char)
{ {
@ -248,8 +247,8 @@ ifxmipsasc_startup(struct uart_port *port)
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC); ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC); ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL); ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON); ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON); ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
wmb (); wmb ();
ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON); ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
@ -399,7 +398,7 @@ ifxmipsasc_type(struct uart_port *port)
{ {
if(port->type == PORT_IFXMIPSASC) if(port->type == PORT_IFXMIPSASC)
{ {
if(port->membase == IFXMIPS_ASC_BASE_ADDR) if(port->membase == (void*)IFXMIPS_ASC_BASE_ADDR)
return "asc0"; return "asc0";
else else
return "asc1"; return "asc1";
@ -501,7 +500,7 @@ ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
do { do {
fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF; >> ASCFSTAT_TXFFLOFF;
} while(fifocnt == IFXMIPSASC_TXFIFO_FULL); } while(fifocnt == TXFIFO_FULL);
if(s[i] == '\0') if(s[i] == '\0')
break; break;
@ -512,7 +511,7 @@ ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
do { do {
fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF; >> ASCFSTAT_TXFFLOFF;
} while(fifocnt == IFXMIPSASC_TXFIFO_FULL); } while(fifocnt == TXFIFO_FULL);
} }
ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
} }

42
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
View File

@ -15,7 +15,6 @@
* *
* Copyright (C) 2005 infineon * Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/ */
#ifndef _IFXMIPS_H__ #ifndef _IFXMIPS_H__
#define _IFXMIPS_H__ #define _IFXMIPS_H__
@ -71,8 +70,41 @@
#define ASCOPT_STOPB 0x8 #define ASCOPT_STOPB 0x8
#define ASCOPT_PARODD 0x0 #define ASCOPT_PARODD 0x0
#define ASCOPT_CREAD 0x20 #define ASCOPT_CREAD 0x20
#define ASCFSTAT_TXFFLMASK 0x3F00 #define TXFIFO_FL 1
#define ASCFSTAT_TXFFLOFF 8 #define RXFIFO_FL 1
#define TXFIFO_FULL 16
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_ODD 0x00000020
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_R 0x00008000
#define ASCCON_FEN 0x00020000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
@ -334,7 +366,7 @@
#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4)) #define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060)) #define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) #define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014)) #define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) #define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038)) #define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008)) #define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
@ -472,7 +504,7 @@
#define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058)) #define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
#define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C)) #define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) #define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) #define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) #define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)

36
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h
View File

@ -1,15 +1,29 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#ifndef _IFXMIPS_CGU_H__ #ifndef _IFXMIPS_CGU_H__
#define _IFXMIPS_CGU_H__ #define _IFXMIPS_CGU_H__
u32 cgu_get_mips_clock(int cpu);
u32 cgu_get_cpu_clock(void); unsigned int cgu_get_mips_clock(int cpu);
u32 cgu_get_io_region_clock(void); unsigned int cgu_get_io_region_clock(void);
u32 cgu_get_fpi_bus_clock(int fpi); unsigned int cgu_get_fpi_bus_clock(int fpi);
u32 cgu_get_pp32_clock(void);
u32 cgu_get_ethernet_clock(int mii);
u32 cgu_get_usb_clock(void);
u32 cgu_get_clockout(int clkout);
void cgu_setup_pci_clk(int internal_clock); void cgu_setup_pci_clk(int internal_clock);
u32 ifxmips_get_ddr_hz(void); unsigned int ifxmips_get_ddr_hz(void);
u32 ifxmips_get_cpu_hz(void); unsigned int ifxmips_get_fpi_hz(void);
u32 ifxmips_get_fpi_hz(void); unsigned int ifxmips_get_cpu_hz(void);
#endif #endif

2
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h
View File

@ -12,9 +12,7 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/ */
#ifndef _IFXMIPS_GPIO_H__ #ifndef _IFXMIPS_GPIO_H__
#define _IFXMIPS_GPIO_H__ #define _IFXMIPS_GPIO_H__

42
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ioctl.h
View File

@ -1,42 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_IOCTL_H__
#define _IFXMIPS_IOCTL_H__
/*------------ LED */
struct ifxmips_port_ioctl_parm
{
int port;
int pin;
int value;
};
#define IFXMIPS_PORT_IOC_MAGIC 0xbf
#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct ifxmips_port_ioctl_parm)
#endif

1
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h
View File

@ -15,7 +15,6 @@
* *
* Copyright (C) 2005 infineon * Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/ */
#ifndef _IFXMIPS_IRQ__ #ifndef _IFXMIPS_IRQ__
#define _IFXMIPS_IRQ__ #define _IFXMIPS_IRQ__

4
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
View File

@ -15,8 +15,12 @@
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/ */
#ifndef _IFXMIPS_LED_H__
#define _IFXMIPS_LED_H__
extern void ifxmips_led_set(unsigned int led); extern void ifxmips_led_set(unsigned int led);
extern void ifxmips_led_clear(unsigned int led); extern void ifxmips_led_clear(unsigned int led);
extern void ifxmips_led_blink_set(unsigned int led); extern void ifxmips_led_blink_set(unsigned int led);
extern void ifxmips_led_blink_clear(unsigned int led); extern void ifxmips_led_blink_clear(unsigned int led);
#endif

34
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mii0.h
View File

@ -1,34 +0,0 @@
#ifndef IFXMIPS_MII0_H
#define IFXMIPS_MII0_H
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#include <linux/netdevice.h>
struct ifxmips_mii_priv {
struct net_device_stats stats;
struct dma_device_info *dma_device;
struct sk_buff *skb;
};
struct ifxmips_mac {
unsigned char mac[6];
};
#endif

2021
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_orig.h
View File

File diff suppressed because it is too large Load Diff

1
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h
View File

@ -14,7 +14,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2007 John Crispin <blogic@openwrt.org> * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/ */
#ifndef _IFXMIPS_PMU_H__ #ifndef _IFXMIPS_PMU_H__
#define _IFXMIPS_PMU_H__ #define _IFXMIPS_PMU_H__

3
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h
View File

@ -14,14 +14,13 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
* *
* Copyright (C) 2008 John Crispin <blogic@openwrt.org> * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*
*/ */
#ifndef _IFXPROM_H__ #ifndef _IFXPROM_H__
#define _IFXPROM_H__ #define _IFXPROM_H__
extern void prom_printf(const char * fmt, ...); extern void prom_printf(const char * fmt, ...);
extern u32 *prom_get_cp1_base(void); extern u32 *prom_get_cp1_base(void);
extern u32 prom_get_cp1_size(void); extern u32 prom_get_cp1_size(void);
extern int ifxmips_has_brn_block(void);
#endif #endif

194
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_serial.h
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/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
#ifndef __IFXMIPS_ASC_H
#define __IFXMIPS_ASC_H
/******************************************************************************
**
** FILE NAME : serial.c
** PROJECT : IFXMips
** MODULES : ASC/UART
**
** DATE : 27 MAR 2006
** AUTHOR : Liu Peng
** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7)
** 23 OCT 2006 Xu Liang Add GPL header.
*******************************************************************************/
/* channel operating modes */
/*#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
*/
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define IFXMIPSASC_TXFIFO_FL 1
#define IFXMIPSASC_RXFIFO_FL 1
#define IFXMIPSASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
#define ASC_INTERRUPTS_CLEAR(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0000000f
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_8IRDA 0x1
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_M_7IRDA 0x3
#define ASCCON_WLSMASK 0x0000000c
#define ASCCON_WLSOFFSET 2
#define ASCCON_WLS_8BIT 0x0
#define ASCCON_WLS_7BIT 0x1
#define ASCCON_PEN 0x00000010
#define ASCCON_ODD 0x00000020
#define ASCCON_SP 0x00000040
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_ERRCLK 0x00000400
#define ASCCON_EMMASK 0x00001800
#define ASCCON_EMOFFSET 11
#define ASCCON_EM_ECHO_OFF 0x0
#define ASCCON_EM_ECHO_AB 0x1
#define ASCCON_EM_ECHO_ON 0x2
#define ASCCON_LB 0x00002000
#define ASCCON_ACO 0x00004000
#define ASCCON_R 0x00008000
#define ASCCON_PAL 0x00010000
#define ASCCON_FEN 0x00020000
#define ASCCON_RUEN 0x00040000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCCON_BEN 0x00200000
#define ASCCON_TXINV 0x01000000
#define ASCCON_RXINV 0x02000000
#define ASCCON_TXMSB 0x04000000
#define ASCCON_RXMSB 0x08000000
/* STATE register's bits and bitfields */
#define ASCSTATE_REN 0x00000001
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_RUE 0x00040000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_TOE 0x00100000
#define ASCSTATE_BE 0x00200000
#define ASCSTATE_TXBVMASK 0x07000000
#define ASCSTATE_TXBVOFFSET 24
#define ASCSTATE_TXEOM 0x08000000
#define ASCSTATE_RXBVMASK 0x70000000
#define ASCSTATE_RXBVOFFSET 28
#define ASCSTATE_RXEOM 0x80000000
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
/* WHBSTATE register's bits and bitfields */
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRRUE 0x00000010
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCWHBSTATE_CLRTOE 0x00000040
#define ASCWHBSTATE_CLRBE 0x00000080
#define ASCWHBSTATE_SETPE 0x00000100
#define ASCWHBSTATE_SETFE 0x00000200
#define ASCWHBSTATE_SETRUE 0x00000400
#define ASCWHBSTATE_SETROE 0x00000800
#define ASCWHBSTATE_SETTOE 0x00001000
#define ASCWHBSTATE_SETBE 0x00002000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_CLRABEN 0x0001
#define ASCWHBABCON_SETABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_CLRSCCDET 0x0040
#define ASCWHBABSTAT_SETSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFIFO1 0x00000400
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFIFO1 0x00000400
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#endif /* __IFXMIPS_ASC_H */