mirror of https://github.com/hak5/openwrt.git
move PCIe init to subsys init call
ARM Linux PCI/PCIe hardware intialization needs to occur before device_init as it does not support hotplug. I have modeled the cns3xxx PCIe init after other ARM platforms. Registering it early resolves resource issues occuring during bus enumeration that occur when a device driver is linked static in the kernel. Instead of passing in a bitmask to enable the 2 available ports, link detect is used to enable ports that have a valid link. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 34044lede-17.01
Imre Kaloz
parent
07a762c4c5
commit
3c12bad276
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@ -0,0 +1,156 @@
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -203,7 +203,6 @@ static void __init cns3420_init(void)
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NR_IRQS_CNS3XXX);
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cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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NR_IRQS_CNS3XXX + 32);
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- cns3xxx_pcie_init(0x3);
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pm_power_off = cns3xxx_power_off;
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}
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@@ -220,11 +219,21 @@ static struct map_desc cns3420_io_desc[]
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static void __init cns3420_map_io(void)
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{
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cns3xxx_common_init();
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+ cns3xxx_pcie_iotable_init();
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iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
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cns3420_early_serial_setup();
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}
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+static int __init cns3420vb_pcie_init(void)
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+{
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+ if (!machine_is_cns3420vb())
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+ return 0;
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+
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+ return cns3xxx_pcie_init();
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+}
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+subsys_initcall(cns3420vb_pcie_init);
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+
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MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
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.atag_offset = 0x100,
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.map_io = cns3420_map_io,
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -12,8 +12,8 @@
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#define __CNS3XXX_CORE_H
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extern struct sys_timer cns3xxx_timer;
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-extern int cns3xxx_pcie_init(u8 bitmap);
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-extern void cns3xxx_pcie_iotable_init(u8 bitmap);
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+extern void cns3xxx_pcie_iotable_init(void);
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+
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#ifdef CONFIG_CACHE_L2X0
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void __init cns3xxx_l2x0_init(void);
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@@ -23,6 +23,7 @@ static inline void cns3xxx_l2x0_init(voi
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void __init cns3xxx_common_init(void);
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void __init cns3xxx_init_irq(void);
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+int __init cns3xxx_pcie_init(void);
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void cns3xxx_power_off(void);
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void cns3xxx_restart(char, const char *);
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--- a/arch/arm/mach-cns3xxx/laguna.c
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+++ b/arch/arm/mach-cns3xxx/laguna.c
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@@ -729,7 +731,7 @@ static struct map_desc laguna_io_desc[]
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static void __init laguna_map_io(void)
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{
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cns3xxx_common_init();
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- cns3xxx_pcie_iotable_init(0x3);
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+ cns3xxx_pcie_iotable_init();
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iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
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laguna_early_serial_setup();
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}
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@@ -753,11 +755,19 @@ static int laguna_register_gpio(struct g
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return ret;
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}
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+static int __init laguna_pcie_init(void)
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+{
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+ if (!machine_is_gw2388())
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+ return 0;
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+
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+ return cns3xxx_pcie_init();
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+}
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+subsys_initcall(laguna_pcie_init);
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+
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static int __init laguna_model_setup(void)
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{
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u32 __iomem *mem;
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u32 reg;
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- u8 pcie_bitmap = 0;
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printk("Running on Gateworks Laguna %s\n", laguna_info.model);
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cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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@@ -779,14 +789,6 @@ static int __init laguna_model_setup(voi
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(laguna_info.config_bitmap & SATA1_LOAD))
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cns3xxx_ahci_init();
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- if (laguna_info.config_bitmap & (PCIE0_LOAD))
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- pcie_bitmap |= 0x1;
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-
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- if (laguna_info.config_bitmap & (PCIE1_LOAD))
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- pcie_bitmap |= 0x2;
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-
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- cns3xxx_pcie_init(pcie_bitmap);
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-
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if (laguna_info.config_bitmap & (USB0_LOAD)) {
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cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
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@@ -926,7 +928,6 @@ static int __init laguna_model_setup(voi
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}
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return 0;
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}
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-
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late_initcall(laguna_model_setup);
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MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
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--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -456,23 +456,18 @@ static int cns3xxx_pcie_abort_handler(un
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return 0;
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}
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-void __init cns3xxx_pcie_iotable_init(u8 bitmap)
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+
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+void __init cns3xxx_pcie_iotable_init()
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{
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- static int _iotable_init = 0;
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int i;
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- bitmap &= ~_iotable_init;
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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- if (!(bitmap & (1 << i)))
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- continue;
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-
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iotable_init(cns3xxx_pcie[i].cfg_bases,
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ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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}
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- _iotable_init |= bitmap;
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}
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-int __init cns3xxx_pcie_init(u8 bitmap)
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+int __init cns3xxx_pcie_init(void)
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{
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int i;
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@@ -482,14 +477,12 @@ int __init cns3xxx_pcie_init(u8 bitmap)
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hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
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"imprecise external abort");
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- cns3xxx_pcie_iotable_init(bitmap);
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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- if (!(bitmap & (1 << i)))
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- continue;
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-
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cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
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- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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- pci_common_init(&cns3xxx_pcie[i].hw_pci);
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+ if (cns3xxx_pcie[i].linked) {
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+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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+ pci_common_init(&cns3xxx_pcie[i].hw_pci);
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+ }
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}
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pci_assign_unassigned_resources();
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