mirror of https://github.com/hak5/openwrt.git
ramips: mmc: Fix init for MT7628AN
There is another thing about crc to do when initialize SD card on MT7628. This commit is to fix this init issue. Signed-off-by: LoveSy <shana@zju.edu.cn>openwrt-19.07
parent
b4d4e4ceb5
commit
3a8efaef00
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@ -234,6 +234,7 @@ enum {
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#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
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#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
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#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
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#define MSDC_IOCON_WDSPL (0x1 << 8) /* RW */
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#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
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#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
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#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
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@ -1796,6 +1796,9 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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MSDC_SMPL_FALLING);
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sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL,
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MSDC_SMPL_FALLING);
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/* sdxc: set sample crc by clock falling edge. Added by zhangzf */
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if (ralink_soc == MT762X_SOC_MT7628AN)
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sdr_set_field(MSDC_IOCON, MSDC_IOCON_WDSPL, MSDC_SMPL_FALLING);
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//} /* for tuning debug */
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} else { /* default value */
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sdr_write32(MSDC_IOCON, 0x00000000);
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@ -2205,7 +2208,7 @@ static int msdc_drv_probe(struct platform_device *pdev)
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struct msdc_host *host;
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struct msdc_hw *hw;
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int ret;
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u32 reg;
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u32 reg, reg1;
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// Set the pins for sdxc to sdxc mode
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//FIXME: this should be done by pinctl and not by the sd driver
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@ -2215,6 +2218,17 @@ static int msdc_drv_probe(struct platform_device *pdev)
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0x60)) & ~(0x3 << 18);
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if (ralink_soc == MT762X_SOC_MT7620A)
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reg |= 0x1 << 18;
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}
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else if (ralink_soc == MT762X_SOC_MT7628AN) {
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/* Fixed MT7628 SDXC init by zhangzf */
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reg &= ~((0x3 << 0)|(0x3 << 6)|(0x3 << 10)|(0x1 << 15)|(0x3 << 20)|(0x3 << 24));
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reg |= ((0x1 << 0)|(0x1 << 6)|(0x1 << 10)|(0x1 << 15)|(0x1 << 20)|(0x1 << 24));
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#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
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reg |= 0x3 << 26 | 0x3 << 28 | 0x3 << 30;
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#endif
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reg1 = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x1340));
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reg1 |= (0x1 << 11); //Normal mode(AP mode), SDXC CLK=PAD_GPIO0=GPIO11, driving = 8mA
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sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x1340), reg1);
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} else {
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reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c));
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reg |= 0x1e << 16;
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