mirror of https://github.com/hak5/openwrt.git
generic: backport support for MT7530 DSA port mirroring
Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>master
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ae6b4d3f86
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From 37feab6076aa816ed72fe836759a485353241916 Mon Sep 17 00:00:00 2001
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From: DENG Qingfang <dqfext@gmail.com>
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Date: Fri, 6 Mar 2020 20:35:35 +0800
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Subject: net: dsa: mt7530: add support for port mirroring
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Add support for configuring port mirroring through the cls_matchall
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classifier. We do a full ingress and/or egress capture towards a
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capture port.
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MT7530 supports one monitor port and multiple mirrored ports.
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Signed-off-by: DENG Qingfang <dqfext@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/mt7530.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++
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drivers/net/dsa/mt7530.h | 7 ++++++
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2 files changed, 67 insertions(+)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -1222,6 +1222,64 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int port,
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return 0;
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}
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+static int mt7530_port_mirror_add(struct dsa_switch *ds, int port,
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+ struct dsa_mall_mirror_tc_entry *mirror,
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+ bool ingress)
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+{
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+ struct mt7530_priv *priv = ds->priv;
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+ u32 val;
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+
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+ /* Check for existent entry */
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+ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
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+ return -EEXIST;
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+
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+ val = mt7530_read(priv, MT7530_MFC);
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+
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+ /* MT7530 only supports one monitor port */
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+ if (val & MIRROR_EN && MIRROR_PORT(val) != mirror->to_local_port)
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+ return -EEXIST;
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+
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+ val |= MIRROR_EN;
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+ val &= ~MIRROR_MASK;
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+ val |= mirror->to_local_port;
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+ mt7530_write(priv, MT7530_MFC, val);
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+
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+ val = mt7530_read(priv, MT7530_PCR_P(port));
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+ if (ingress) {
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+ val |= PORT_RX_MIR;
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+ priv->mirror_rx |= BIT(port);
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+ } else {
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+ val |= PORT_TX_MIR;
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+ priv->mirror_tx |= BIT(port);
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+ }
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+ mt7530_write(priv, MT7530_PCR_P(port), val);
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+
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+ return 0;
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+}
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+
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+static void mt7530_port_mirror_del(struct dsa_switch *ds, int port,
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+ struct dsa_mall_mirror_tc_entry *mirror)
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+{
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+ struct mt7530_priv *priv = ds->priv;
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+ u32 val;
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+
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+ val = mt7530_read(priv, MT7530_PCR_P(port));
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+ if (mirror->ingress) {
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+ val &= ~PORT_RX_MIR;
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+ priv->mirror_rx &= ~BIT(port);
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+ } else {
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+ val &= ~PORT_TX_MIR;
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+ priv->mirror_tx &= ~BIT(port);
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+ }
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+ mt7530_write(priv, MT7530_PCR_P(port), val);
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+
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+ if (!priv->mirror_rx && !priv->mirror_tx) {
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+ val = mt7530_read(priv, MT7530_MFC);
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+ val &= ~MIRROR_EN;
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+ mt7530_write(priv, MT7530_MFC, val);
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+ }
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+}
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+
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static enum dsa_tag_protocol
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mtk_get_tag_protocol(struct dsa_switch *ds, int port,
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enum dsa_tag_protocol mp)
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@@ -1613,6 +1671,8 @@ static const struct dsa_switch_ops mt7530_switch_ops = {
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.port_vlan_prepare = mt7530_port_vlan_prepare,
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.port_vlan_add = mt7530_port_vlan_add,
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.port_vlan_del = mt7530_port_vlan_del,
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+ .port_mirror_add = mt7530_port_mirror_add,
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+ .port_mirror_del = mt7530_port_mirror_del,
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.phylink_validate = mt7530_phylink_validate,
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.phylink_mac_link_state = mt7530_phylink_mac_link_state,
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.phylink_mac_config = mt7530_phylink_mac_config,
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -36,6 +36,9 @@ enum {
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#define CPU_EN BIT(7)
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#define CPU_PORT(x) ((x) << 4)
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#define CPU_MASK (0xf << 4)
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+#define MIRROR_EN BIT(3)
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+#define MIRROR_PORT(x) ((x) & 0x7)
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+#define MIRROR_MASK 0x7
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/* Registers for address table access */
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#define MT7530_ATA1 0x74
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@@ -141,6 +144,8 @@ enum mt7530_stp_state {
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/* Register for port control */
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#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
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+#define PORT_TX_MIR BIT(9)
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+#define PORT_RX_MIR BIT(8)
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#define PORT_VLAN(x) ((x) & 0x3)
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enum mt7530_port_mode {
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@@ -460,6 +465,8 @@ struct mt7530_priv {
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phy_interface_t p6_interface;
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phy_interface_t p5_interface;
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unsigned int p5_intf_sel;
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+ u8 mirror_rx;
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+ u8 mirror_tx;
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struct mt7530_port ports[MT7530_NUM_PORTS];
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/* protect among processes for registers access*/
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