mirror of https://github.com/hak5/openwrt.git
ipq806x: Add support for custom data mapping in bam_dma dmaengine
This change adds a new function to support for preparing DMA descriptor for custom data. Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>openwrt-18.06
Ram Chandra Jangir
John Crispin
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@ -0,0 +1,217 @@
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From 5a7ccdf845d64b385affdcffaf2defbe9848be15 Mon Sep 17 00:00:00 2001
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From: Ram Chandra Jangir <rjangir@codeaurora.org>
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Date: Thu, 20 Apr 2017 10:39:00 +0530
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Subject: [PATCH] dmaengine: qcom: bam_dma: Add custom data mapping
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Add a new function to support for preparing DMA descriptor
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for custom data.
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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---
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drivers/dma/qcom/bam_dma.c | 97 +++++++++++++++++++++++++++++++++++++---
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include/linux/dma/qcom_bam_dma.h | 14 ++++++
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include/linux/dmaengine.h | 14 ++++++
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3 files changed, 119 insertions(+), 6 deletions(-)
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diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
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index 03c4eb3..bde8d70 100644
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--- a/drivers/dma/qcom/bam_dma.c
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+++ b/drivers/dma/qcom/bam_dma.c
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@@ -49,6 +49,7 @@
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/pm_runtime.h>
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+#include <linux/dma/qcom_bam_dma.h>
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#include "../dmaengine.h"
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#include "../virt-dma.h"
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@@ -61,11 +62,6 @@ struct bam_desc_hw {
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#define BAM_DMA_AUTOSUSPEND_DELAY 100
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-#define DESC_FLAG_INT BIT(15)
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-#define DESC_FLAG_EOT BIT(14)
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-#define DESC_FLAG_EOB BIT(13)
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-#define DESC_FLAG_NWD BIT(12)
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-
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struct bam_async_desc {
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struct virt_dma_desc vd;
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@@ -670,6 +666,93 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
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}
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/**
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+ * bam_prep_dma_custom_mapping - Prep DMA descriptor from custom data
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+ *
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+ * @chan: dma channel
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+ * @data: custom data
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+ * @flags: DMA flags
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+ */
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+static struct dma_async_tx_descriptor *bam_prep_dma_custom_mapping(
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+ struct dma_chan *chan,
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+ void *data, unsigned long flags)
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+{
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+ struct bam_chan *bchan = to_bam_chan(chan);
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+ struct bam_device *bdev = bchan->bdev;
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+ struct bam_async_desc *async_desc;
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+ struct qcom_bam_custom_data *desc_data = data;
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+ u32 i;
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+ struct bam_desc_hw *desc;
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+ unsigned int num_alloc = 0;
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+
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+
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+ if (!is_slave_direction(desc_data->dir)) {
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+ dev_err(bdev->dev, "invalid dma direction\n");
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+ return NULL;
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+ }
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+
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+ /* calculate number of required entries */
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+ for (i = 0; i < desc_data->sgl_cnt; i++)
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+ num_alloc += DIV_ROUND_UP(
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+ sg_dma_len(&desc_data->bam_sgl[i].sgl), BAM_FIFO_SIZE);
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+
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+ /* allocate enough room to accommodate the number of entries */
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+ async_desc = kzalloc(sizeof(*async_desc) +
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+ (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
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+
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+ if (!async_desc)
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+ goto err_out;
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+
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+ if (flags & DMA_PREP_FENCE)
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+ async_desc->flags |= DESC_FLAG_NWD;
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+
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+ if (flags & DMA_PREP_INTERRUPT)
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+ async_desc->flags |= DESC_FLAG_EOT;
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+ else
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+ async_desc->flags |= DESC_FLAG_INT;
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+
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+ async_desc->num_desc = num_alloc;
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+ async_desc->curr_desc = async_desc->desc;
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+ async_desc->dir = desc_data->dir;
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+
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+ /* fill in temporary descriptors */
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+ desc = async_desc->desc;
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+ for (i = 0; i < desc_data->sgl_cnt; i++) {
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+ unsigned int remainder;
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+ unsigned int curr_offset = 0;
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+
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+ remainder = sg_dma_len(&desc_data->bam_sgl[i].sgl);
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+
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+ do {
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+ desc->addr = cpu_to_le32(
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+ sg_dma_address(&desc_data->bam_sgl[i].sgl) +
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+ curr_offset);
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+
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+ if (desc_data->bam_sgl[i].dma_flags)
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+ desc->flags |= cpu_to_le16(
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+ desc_data->bam_sgl[i].dma_flags);
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+
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+ if (remainder > BAM_FIFO_SIZE) {
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+ desc->size = cpu_to_le16(BAM_FIFO_SIZE);
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+ remainder -= BAM_FIFO_SIZE;
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+ curr_offset += BAM_FIFO_SIZE;
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+ } else {
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+ desc->size = cpu_to_le16(remainder);
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+ remainder = 0;
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+ }
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+
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+ async_desc->length += desc->size;
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+ desc++;
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+ } while (remainder > 0);
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+ }
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+
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+ return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
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+
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+err_out:
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+ kfree(async_desc);
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+ return NULL;
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+}
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+
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+/**
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* bam_dma_terminate_all - terminate all transactions on a channel
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* @bchan: bam dma channel
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*
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@@ -960,7 +1043,7 @@ static void bam_start_dma(struct bam_chan *bchan)
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/* set any special flags on the last descriptor */
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if (async_desc->num_desc == async_desc->xfer_len)
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- desc[async_desc->xfer_len - 1].flags =
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+ desc[async_desc->xfer_len - 1].flags |=
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cpu_to_le16(async_desc->flags);
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else
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desc[async_desc->xfer_len - 1].flags |=
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@@ -1237,6 +1320,8 @@ static int bam_dma_probe(struct platform_device *pdev)
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bdev->common.device_alloc_chan_resources = bam_alloc_chan;
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bdev->common.device_free_chan_resources = bam_free_chan;
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bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
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+ bdev->common.device_prep_dma_custom_mapping =
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+ bam_prep_dma_custom_mapping;
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bdev->common.device_config = bam_slave_config;
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bdev->common.device_pause = bam_pause;
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bdev->common.device_resume = bam_resume;
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diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_dma.h
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index 7e87a85..7113c77 100644
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--- a/include/linux/dma/qcom_bam_dma.h
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+++ b/include/linux/dma/qcom_bam_dma.h
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@@ -65,6 +65,19 @@ enum bam_command_type {
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};
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/*
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+ * QCOM BAM DMA custom data
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+ *
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+ * @sgl_cnt: number of sgl in bam_sgl
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+ * @dir: DMA data transfer direction
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+ * @bam_sgl: BAM SGL pointer
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+ */
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+struct qcom_bam_custom_data {
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+ u32 sgl_cnt;
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+ enum dma_transfer_direction dir;
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+ struct qcom_bam_sgl *bam_sgl;
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+};
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+
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+/*
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* qcom_bam_sg_init_table - Init QCOM BAM SGL
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* @bam_sgl: bam sgl
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* @nents: number of entries in bam sgl
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diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
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index cc535a4..627c125 100644
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--- a/include/linux/dmaengine.h
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+++ b/include/linux/dmaengine.h
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@@ -692,6 +692,8 @@ struct dma_filter {
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* be called after period_len bytes have been transferred.
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* @device_prep_interleaved_dma: Transfer expression in a generic way.
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* @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
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+ * @device_prep_dma_custom_mapping: prepares a dma operation from dma driver
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+ * specific custom data
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* @device_config: Pushes a new configuration to a channel, return 0 or an error
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* code
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* @device_pause: Pauses any transfer happening on a channel. Returns
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@@ -783,6 +785,9 @@ struct dma_device {
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struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
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struct dma_chan *chan, dma_addr_t dst, u64 data,
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unsigned long flags);
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+ struct dma_async_tx_descriptor *(*device_prep_dma_custom_mapping)(
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+ struct dma_chan *chan, void *data,
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+ unsigned long flags);
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int (*device_config)(struct dma_chan *chan,
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struct dma_slave_config *config);
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@@ -899,6 +904,15 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
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src_sg, src_nents, flags);
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}
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+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_custom_mapping(
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+ struct dma_chan *chan,
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+ void *data,
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+ unsigned long flags)
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+{
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+ return chan->device->device_prep_dma_custom_mapping(chan, data,
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+ flags);
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+}
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+
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/**
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* dmaengine_terminate_all() - Terminate all active DMA transfers
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* @chan: The channel for which to terminate the transfers
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--
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2.7.2
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