hak5
/
openwrt
mirror of https://github.com/hak5/openwrt.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

more danube 2 ifxmips transitions 

SVN-Revision: 9830
lede-17.01
John Crispin 2007-12-22 14:03:37 +00:00
parent 6db275d9cf
commit 32bd98f475
14 changed files with 0 additions and 4190 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

358
target/linux/ifxmips/files/include/asm-mips/danube/danube.h
View File

@ -1,358 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_H__
#define _IFXMIPS_H__
/*------------ GENERAL */
#define BOARD_SYSTEM_TYPE "IFXMIPS"
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xffffffff
/*------------ ASC1 */
#define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
/* FIFO status register */
#define IFXMIPS_ASC1_FSTAT ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
/* ASC1 transmit buffer */
#define IFXMIPS_ASC1_TBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
/* channel operating modes */
#define ASCOPT_CSIZE 0x3
#define ASCOPT_CS7 0x1
#define ASCOPT_CS8 0x2
#define ASCOPT_PARENB 0x4
#define ASCOPT_STOPB 0x8
#define ASCOPT_PARODD 0x0
#define ASCOPT_CREAD 0x20
/* hardware modified control register */
#define IFXMIPS_ASC1_WHBSTATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
/* receive buffer register */
#define IFXMIPS_ASC1_RBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
/* status register */
#define IFXMIPS_ASC1_STATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
/* interrupt control */
#define IFXMIPS_ASC1_IRNCR ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
#define ASC_IRNCR_TIR 0x4
#define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4
/* clock control */
#define IFXMIPS_ASC1_CLC ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
#define IFXMIPS_ASC1_CLC_DISS 0x2
/* port input select register */
#define IFXMIPS_ASC1_PISEL ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
/* tx fifo */
#define IFXMIPS_ASC1_TXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
/* rx fifo */
#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
/* control */
#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
/* timer reload */
#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
/* int enable */
#define IFXMIPS_ASC1_IRNREN ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
#define ASC_IRNREN_RX_BUF 0x8
#define ASC_IRNREN_TX_BUF 0x4
#define ASC_IRNREN_ERR 0x2
#define ASC_IRNREN_TX 0x1
/*------------ RCU */
#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
/* reset request */
#define IFXMIPS_RCU_REQ ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
#define IFXMIPS_RST_ALL 0x40000000
/*------------ MCD */
#define IFXMIPS_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
/* chip id */
#define IFXMIPS_MCD_CHIPID ((u32*)(IFXMIPS_MCD_BASE_ADDR + 0x0028))
/*------------ GPTU */
#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
/* clock control register */
#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
/* captur reload register */
#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
/* timer 6 control register */
#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
/*------------ EBU */
#define IFXMIPS_EBU_BASE_ADDR 0xBE105300
/* bus configuration register */
#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
/*------------ CGU */
#define IFXMIPS_CGU_BASE_ADDR 0xBF103000
/* clock mux */
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
#define CLOCK_111M 111111111
#define CLOCK_133M 133333333
#define CLOCK_167M 166666667
#define CLOCK_333M 333333333
/*------------ CGU */
#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
/*------------ ICU */
#define IFXMIPS_ICU_BASE_ADDR 0xBF880200
#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
/*------------ ETOP */
#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
#define IFXMIPS_PPE32_MEM_MAP (IFXMIPS_PPE32_BASE_ADDR + 0x10000 )
#define MII_MODE 1
#define REV_MII_MODE 2
/* mdio access */
#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1804))
#define MDIO_ACC_REQUEST 0x80000000
#define MDIO_ACC_READ 0x40000000
#define MDIO_ACC_ADDR_MASK 0x1f
#define MDIO_ACC_ADDR_OFFSET 0x15
#define MDIO_ACC_REG_MASK 0xff
#define MDIO_ACC_REG_OFFSET 0x10
#define MDIO_ACC_VAL_MASK 0xffff
/* configuration */
#define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
#define PPE32_MII_MASK 0xfffffffc
#define PPE32_MII_NORMAL 0x8
#define PPE32_MII_REVERSE 0xe
/* packet length */
#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
#define PPE32_PLEN_OVER 0x5ee
#define PPE32_PLEN_UNDER 0x400000
/* enet */
#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
#define PPE32_CGEN 0x800
/*------------ DMA */
#define IFXMIPS_DMA_BASE_ADDR 0xBE104100
#define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18))
#define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
#define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
#define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
#define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28))
#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24))
#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40))
#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44))
#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10))
#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14))
#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20))
/*------------ PCI */
#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004))
#define PCI_MASTER0_REQ_MASK_2BITS 8
#define PCI_MASTER1_REQ_MASK_2BITS 10
#define PCI_MASTER2_REQ_MASK_2BITS 12
#define INTERNAL_ARB_ENABLE_BIT 0
/*------------ WDT */
#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
#define IFXMIPS_BIU_WDT_CR_GEN (1 << 31)
#define IFXMIPS_BIU_WDT_CR_DSEN (1 << 30)
#define IFXMIPS_BIU_WDT_CR_LPEN (1 << 29)
#define IFXMIPS_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
#define IFXMIPS_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
#define IFXMIPS_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
#define IFXMIPS_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
#define IFXMIPS_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
#define IFXMIPS_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
/*------------ LED */
#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000))
#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004))
#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008))
#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C))
#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010))
#define LED_CON0_SWU (1 << 31)
#define LED_CON0_AD1 (1 << 25)
#define LED_CON0_AD0 (1 << 24)
#define IFXMIPS_LED_2HZ (0)
#define IFXMIPS_LED_4HZ (1 << 23)
#define IFXMIPS_LED_8HZ (2 << 23)
#define IFXMIPS_LED_10HZ (3 << 23)
#define IFXMIPS_LED_MASK (0xf << 23)
#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
#define IFXMIPS_LED_UPD_MASK (3 << 30)
#define IFXMIPS_LED_ADSL_SRC (3 << 24)
#define IFXMIPS_LED_GROUP0 (1 << 0)
#define IFXMIPS_LED_GROUP1 (1 << 1)
#define IFXMIPS_LED_GROUP2 (1 << 2)
#define IFXMIPS_LED_RISING 0
#define IFXMIPS_LED_FALLING (1 << 26)
#define IFXMIPS_LED_EDGE_MASK (1 << 26)
/*------------ GPIO */
#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
#define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
#define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
#define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
/*------------ SSC */
#define IFXMIPS_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
#endif

202
target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h
View File

@ -1,202 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_DMA_H__
#define _IFXMIPS_DMA_H__
#define RCV_INT 1
#define TX_BUF_FULL_INT 2
#define TRANSMIT_CPT_INT 4
#define IFXMIPS_DMA_CH_ON 1
#define IFXMIPS_DMA_CH_OFF 0
#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
enum attr_t{
TX = 0,
RX = 1,
RESERVED = 2,
DEFAULT = 3,
};
#define DMA_OWN 1
#define CPU_OWN 0
#define DMA_MAJOR 250
#define DMA_DESC_OWN_CPU 0x0
#define DMA_DESC_OWN_DMA 0x80000000
#define DMA_DESC_CPT_SET 0x40000000
#define DMA_DESC_SOP_SET 0x20000000
#define DMA_DESC_EOP_SET 0x10000000
#define MISCFG_MASK 0x40
#define RDERR_MASK 0x20
#define CHOFF_MASK 0x10
#define DESCPT_MASK 0x8
#define DUR_MASK 0x4
#define EOP_MASK 0x2
#define DMA_DROP_MASK (1<<31)
#define IFXMIPS_DMA_RX -1
#define IFXMIPS_DMA_TX 1
typedef struct dma_chan_map {
char dev_name[15];
enum attr_t dir;
int pri;
int irq;
int rel_chan_no;
} _dma_chan_map;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
typedef struct rx_desc{
u32 data_length:16;
volatile u32 reserved:7;
volatile u32 byte_offset:2;
volatile u32 Burst_length_offset:3;
volatile u32 EoP:1;
volatile u32 Res:1;
volatile u32 C:1;
volatile u32 OWN:1;
volatile u32 Data_Pointer;
/*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
}_rx_desc;
typedef struct tx_desc{
volatile u32 data_length:16;
volatile u32 reserved1:7;
volatile u32 byte_offset:5;
volatile u32 EoP:1;
volatile u32 SoP:1;
volatile u32 C:1;
volatile u32 OWN:1;
volatile u32 Data_Pointer;//fix me:should be 28 bits here
}_tx_desc;
#else //BIG
typedef struct rx_desc{
union
{
struct
{
volatile u32 OWN:1;
volatile u32 C:1;
volatile u32 SoP:1;
volatile u32 EoP:1;
volatile u32 Burst_length_offset:3;
volatile u32 byte_offset:2;
volatile u32 reserve:7;
volatile u32 data_length:16;
}field;
volatile u32 word;
}status;
volatile u32 Data_Pointer;
}_rx_desc;
typedef struct tx_desc{
union
{
struct
{
volatile u32 OWN:1;
volatile u32 C:1;
volatile u32 SoP:1;
volatile u32 EoP:1;
volatile u32 byte_offset:5;
volatile u32 reserved:7;
volatile u32 data_length:16;
}field;
volatile u32 word;
}status;
volatile u32 Data_Pointer;
}_tx_desc;
#endif //ENDIAN
typedef struct dma_channel_info{
/*relative channel number*/
int rel_chan_no;
/*class for this channel for QoS*/
int pri;
/*specify byte_offset*/
int byte_offset;
/*direction*/
int dir;
/*irq number*/
int irq;
/*descriptor parameter*/
int desc_base;
int desc_len;
int curr_desc;
int prev_desc;/*only used if it is a tx channel*/
/*weight setting for WFQ algorithm*/
int weight;
int default_weight;
int packet_size;
int burst_len;
/*on or off of this channel*/
int control;
/**optional information for the upper layer devices*/
#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
void* opt[64];
#else
void* opt[25];
#endif
/*Pointer to the peripheral device who is using this channel*/
void* dma_dev;
/*channel operations*/
void (*open)(struct dma_channel_info* pCh);
void (*close)(struct dma_channel_info* pCh);
void (*reset)(struct dma_channel_info* pCh);
void (*enable_irq)(struct dma_channel_info* pCh);
void (*disable_irq)(struct dma_channel_info* pCh);
}_dma_channel_info;
typedef struct dma_device_info{
/*device name of this peripheral*/
char device_name[15];
int reserved;
int tx_burst_len;
int rx_burst_len;
int default_weight;
int current_tx_chan;
int current_rx_chan;
int num_tx_chan;
int num_rx_chan;
int max_rx_chan_num;
int max_tx_chan_num;
_dma_channel_info* tx_chan[20];
_dma_channel_info* rx_chan[20];
/*functions, optional*/
u8* (*buffer_alloc)(int len,int* offset, void** opt);
void (*buffer_free)(u8* dataptr, void* opt);
int (*intr_handler)(struct dma_device_info* info, int status);
void * priv; /* used by peripheral driver only */
}_dma_device_info;
_dma_device_info* dma_device_reserve(char* dev_name);
void dma_device_release(_dma_device_info* dev);
void dma_device_register(_dma_device_info* info);
void dma_device_unregister(_dma_device_info* info);
int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);
#endif

42
target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h
View File

@ -1,42 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_GPIO_H__
#define _IFXMIPS_GPIO_H__
extern int ifxmips_port_reserve_pin (unsigned int port, unsigned int pin);
extern int ifxmips_port_free_pin (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_open_drain (unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_open_drain (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_pudsel (unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_puden (unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_puden (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_stoff (unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_stoff (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_dir_out (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_dir_in (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_output (unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_output (unsigned int port, unsigned int pin);
extern int ifxmips_port_get_input (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_altsel0 (unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_altsel0 (unsigned int port, unsigned int pin);
extern int ifxmips_port_set_altsel1 (unsigned int port, unsigned int pin);
extern int ifxmips_port_clear_altsel1 (unsigned int port, unsigned int pin);
#endif

42
target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h
View File

@ -1,42 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_IOCTL_H__
#define _IFXMIPS_IOCTL_H__
/*------------ LED */
struct ifxmips_port_ioctl_parm
{
int port;
int pin;
int value;
};
#define IFXMIPS_PORT_IOC_MAGIC 0xbf
#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct ifxmips_port_ioctl_parm)
#endif

66
target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
View File

@ -1,66 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_IRQ__
#define _IFXMIPS_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define IFXMIPSASC1_TIR (INT_NUM_IM3_IRL0 + 7)
#define IFXMIPSASC1_RIR (INT_NUM_IM3_IRL0 + 9)
#define IFXMIPSASC1_EIR (INT_NUM_IM3_IRL0 + 10)
#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
#define MIPS_CPU_TIMER_IRQ 7
#define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0)
#define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
#define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
#define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
#define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
#define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
#define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
#define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
#define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
#define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
#define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
#define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
#define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
#define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
#define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
#define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
#define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
#define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
#endif

254
target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h
View File

@ -1,254 +0,0 @@
#ifndef IFXMIPS_SW_H
#define IFXMIPS_SW_H
/******************************************************************************
**
** FILE NAME : ifxmips_sw.h
** PROJECT : IFXMips
** MODULES : ETH Interface (MII0)
**
** DATE : 11 AUG 2005
** AUTHOR : Wu Qi Ming
** DESCRIPTION : ETH Interface (MII0) Driver Header File
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 11 AUG 2005 Wu Qi Ming Initiate Version
** 23 OCT 2006 Xu Liang Add GPL header.
*******************************************************************************/
#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE
#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1
#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2
#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3
#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4
#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5
#define SET_ETH_REG SIOCDEVPRIVATE+6
#define VLAN_TOOLS SIOCDEVPRIVATE+7
#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8
#define SET_VLAN_COS SIOCDEVPRIVATE+9
#define SET_DSCP_COS SIOCDEVPRIVATE+10
#define ENABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+11
#define DISABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+12
#define VLAN_CLASS_FIRST SIOCDEVPRIVATE+13
#define VLAN_CLASS_SECOND SIOCDEVPRIVATE+14
#define ENABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+15
#define DISABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+16
#define PASS_UNICAST_PACKETS SIOCDEVPRIVATE+17
#define FILTER_UNICAST_PACKETS SIOCDEVPRIVATE+18
#define KEEP_BROADCAST_PACKETS SIOCDEVPRIVATE+19
#define DROP_BROADCAST_PACKETS SIOCDEVPRIVATE+20
#define KEEP_MULTICAST_PACKETS SIOCDEVPRIVATE+21
#define DROP_MULTICAST_PACKETS SIOCDEVPRIVATE+22
/*===mac table commands==*/
#define RESET_MAC_TABLE 0
#define READ_MAC_ENTRY 1
#define WRITE_MAC_ENTRY 2
#define ADD_MAC_ENTRY 3
/*====vlan commands===*/
#define CHANGE_VLAN_CTRL 0
#define READ_VLAN_ENTRY 1
#define UPDATE_VLAN_ENTRY 2
#define CLEAR_VLAN_ENTRY 3
#define RESET_VLAN_TABLE 4
#define ADD_VLAN_ENTRY 5
/*
** MDIO constants.
*/
#define MDIO_BASE_STATUS_REG 0x1
#define MDIO_BASE_CONTROL_REG 0x0
#define MDIO_PHY_ID_HIGH_REG 0x2
#define MDIO_PHY_ID_LOW_REG 0x3
#define MDIO_BC_NEGOTIATE 0x0200
#define MDIO_BC_FULL_DUPLEX_MASK 0x0100
#define MDIO_BC_AUTO_NEG_MASK 0x1000
#define MDIO_BC_SPEED_SELECT_MASK 0x2000
#define MDIO_STATUS_100_FD 0x4000
#define MDIO_STATUS_100_HD 0x2000
#define MDIO_STATUS_10_FD 0x1000
#define MDIO_STATUS_10_HD 0x0800
#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800
#define MDIO_ADVERTISMENT_REG 0x4
#define MDIO_ADVERT_100_FD 0x100
#define MDIO_ADVERT_100_HD 0x080
#define MDIO_ADVERT_10_FD 0x040
#define MDIO_ADVERT_10_HD 0x020
#define MDIO_LINK_UP_MASK 0x4
#define MDIO_START 0x1
#define MDIO_READ 0x2
#define MDIO_WRITE 0x1
#define MDIO_PREAMBLE 0xfffffffful
#define PHY_RESET 0x8000
#define AUTO_NEGOTIATION_ENABLE 0X1000
#define AUTO_NEGOTIATION_COMPLETE 0x20
#define RESTART_AUTO_NEGOTIATION 0X200
/*ETOP_MDIO_CFG MASKS*/
#define SMRST_MASK 0X2000
#define PHYA1_MASK 0X1F00
#define PHYA0_MASK 0XF8
#define UMM1_MASK 0X4
#define UMM0_MASK 0X2
/*ETOP_MDIO_ACCESS MASKS*/
#define MDIO_RA_MASK 0X80000000
#define MDIO_RW_MASK 0X40000000
/*ENET_MAC_CFG MASKS*/
#define BP_MASK 1<<12
#define CGEN_MASK 1<<11
#define IFG_MASK 0x3F<<5
#define IPAUS_MASK 1<<4
#define EPAUS_MASK 1<<3
#define DUPLEX_MASK 1<<2
#define SPEED_MASK 0x2
#define LINK_MASK 1
/*ENETS_CoS_CFG MASKS*/
#define VLAN_MASK 2
#define DSCP_MASK 1
/*ENET_CFG MASKS*/
#define VL2_MASK 1<<29
#define FTUC_MASK 1<<25
#define DPBC_MASK 1<<24
#define DPMC_MASK 1<<23
#define PHY0_ADDR 0
#define PHY1_ADDR 1
#define P1M 0
#define IFXMIPS_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define OK 0;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
typedef struct mac_table_entry{
u64 mac_address:48;
u64 p0:1;
u64 p1:1;
u64 p2:1;
u64 cr:1;
u64 ma_st:3;
u64 res:9;
}_mac_table_entry;
typedef struct IFX_Switch_VLanTableEntry{
u32 vlan_id:12;
u32 mp0:1;
u32 mp1:1;
u32 mp2:1;
u32 v:1;
u32 res:16;
}_IFX_Switch_VLanTableEntry;
typedef struct mac_table_req{
int cmd;
int index;
u32 data;
u64 entry_value;
}_mac_table_req;
#else //not CONFIG_CPU_LITTLE_ENDIAN
typedef struct mac_table_entry{
u64 mac_address:48;
u64 p0:1;
u64 p1:1;
u64 p2:1;
u64 cr:1;
u64 ma_st:3;
u64 res:9;
}_mac_table_entry;
typedef struct IFX_Switch_VLanTableEntry{
u32 vlan_id:12;
u32 mp0:1;
u32 mp1:1;
u32 mp2:1;
u32 v:1;
u32 res:16;
}_IFX_Switch_VLanTableEntry;
typedef struct mac_table_req{
int cmd;
int index;
u32 data;
u64 entry_value;
}_mac_table_req;
#endif //CONFIG_CPU_LITTLE_ENDIAN
typedef struct vlan_cos_req{
int pri;
int cos_value;
}_vlan_cos_req;
typedef struct dscp_cos_req{
int dscp;
int cos_value;
}_dscp_cos_req;
typedef struct vlan_req{
int cmd;
int index;
u32 data;
u32 entry_value;
}_vlan_req;
typedef struct data_req{
int index;
u32 value;
}_data_req;
enum duplex
{
half,
full,
autoneg
};
struct switch_priv {
struct net_device_stats stats;
int rx_packetlen;
u8 *rx_packetdata;
int rx_status;
int tx_packetlen;
#ifdef CONFIG_NET_HW_FLOWCONTROL
int fc_bit;
#endif //CONFIG_NET_HW_FLOWCONTROL
u8 *tx_packetdata;
int tx_status;
struct dma_device_info *dma_device;
struct sk_buff *skb;
spinlock_t lock;
int mdio_phy_addr;
int current_speed;
int current_speed_selection;
int rx_queue_len;
int full_duplex;
enum duplex current_duplex;
};
#endif //IFXMIPS_SW_H

2021
target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h
View File

File diff suppressed because it is too large Load Diff

31
target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h
View File

@ -1,31 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_PMU_H__
#define _IFXMIPS_PMU_H__
#define IFXMIPS_PMU_PWDCR_DMA 0x20
#define IFXMIPS_PMU_PWDCR_LED 0x800
#define IFXMIPS_PMU_PWDCR_GPT 0x1000
#define IFXMIPS_PMU_PWDCR_PPE 0x2000
#define IFXMIPS_PMU_PWDCR_FPI 0x4000
void ifxmips_pmu_enable (unsigned int module);
void ifxmips_pmu_disable (unsigned int module);
#endif

194
target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h
View File

@ -1,194 +0,0 @@
/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
#ifndef __IFXMIPS_ASC_H
#define __IFXMIPS_ASC_H
/******************************************************************************
**
** FILE NAME : serial.c
** PROJECT : IFXMips
** MODULES : ASC/UART
**
** DATE : 27 MAR 2006
** AUTHOR : Liu Peng
** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7)
** 23 OCT 2006 Xu Liang Add GPL header.
*******************************************************************************/
/* channel operating modes */
/*#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
*/
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define IFXMIPSASC_TXFIFO_FL 1
#define IFXMIPSASC_RXFIFO_FL 1
#define IFXMIPSASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
#define ASC_INTERRUPTS_CLEAR(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0000000f
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_8IRDA 0x1
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_M_7IRDA 0x3
#define ASCCON_WLSMASK 0x0000000c
#define ASCCON_WLSOFFSET 2
#define ASCCON_WLS_8BIT 0x0
#define ASCCON_WLS_7BIT 0x1
#define ASCCON_PEN 0x00000010
#define ASCCON_ODD 0x00000020
#define ASCCON_SP 0x00000040
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_ERRCLK 0x00000400
#define ASCCON_EMMASK 0x00001800
#define ASCCON_EMOFFSET 11
#define ASCCON_EM_ECHO_OFF 0x0
#define ASCCON_EM_ECHO_AB 0x1
#define ASCCON_EM_ECHO_ON 0x2
#define ASCCON_LB 0x00002000
#define ASCCON_ACO 0x00004000
#define ASCCON_R 0x00008000
#define ASCCON_PAL 0x00010000
#define ASCCON_FEN 0x00020000
#define ASCCON_RUEN 0x00040000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCCON_BEN 0x00200000
#define ASCCON_TXINV 0x01000000
#define ASCCON_RXINV 0x02000000
#define ASCCON_TXMSB 0x04000000
#define ASCCON_RXMSB 0x08000000
/* STATE register's bits and bitfields */
#define ASCSTATE_REN 0x00000001
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_RUE 0x00040000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_TOE 0x00100000
#define ASCSTATE_BE 0x00200000
#define ASCSTATE_TXBVMASK 0x07000000
#define ASCSTATE_TXBVOFFSET 24
#define ASCSTATE_TXEOM 0x08000000
#define ASCSTATE_RXBVMASK 0x70000000
#define ASCSTATE_RXBVOFFSET 28
#define ASCSTATE_RXEOM 0x80000000
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
/* WHBSTATE register's bits and bitfields */
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRRUE 0x00000010
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCWHBSTATE_CLRTOE 0x00000040
#define ASCWHBSTATE_CLRBE 0x00000080
#define ASCWHBSTATE_SETPE 0x00000100
#define ASCWHBSTATE_SETFE 0x00000200
#define ASCWHBSTATE_SETRUE 0x00000400
#define ASCWHBSTATE_SETROE 0x00000800
#define ASCWHBSTATE_SETTOE 0x00001000
#define ASCWHBSTATE_SETBE 0x00002000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_CLRABEN 0x0001
#define ASCWHBABCON_SETABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_CLRSCCDET 0x0040
#define ASCWHBABSTAT_SETSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFIFO1 0x00000400
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFIFO1 0x00000400
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#endif /* __IFXMIPS_ASC_H */

48
target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h
View File

@ -1,48 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef IFXMIPS_WDT_H
#define IFXMIPS_WDT_H
/* IFXMips wdt ioctl control */
#define IFXMIPS_WDT_IOC_MAGIC 0xc0
#define IFXMIPS_WDT_IOC_START _IOW(IFXMIPS_WDT_IOC_MAGIC, 0, int)
#define IFXMIPS_WDT_IOC_STOP _IO(IFXMIPS_WDT_IOC_MAGIC, 1)
#define IFXMIPS_WDT_IOC_PING _IO(IFXMIPS_WDT_IOC_MAGIC, 2)
#define IFXMIPS_WDT_IOC_SET_PWL _IOW(IFXMIPS_WDT_IOC_MAGIC, 3, int)
#define IFXMIPS_WDT_IOC_SET_DSEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 4, int)
#define IFXMIPS_WDT_IOC_SET_LPEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 5, int)
#define IFXMIPS_WDT_IOC_GET_STATUS _IOR(IFXMIPS_WDT_IOC_MAGIC, 6, int)
#define IFXMIPS_WDT_IOC_SET_CLKDIV _IOW(IFXMIPS_WDT_IOC_MAGIC, 7, int)
/* password 1 and 2 */
#define IFXMIPS_WDT_PW1 0x000000BE
#define IFXMIPS_WDT_PW2 0x000000DC
#define IFXMIPS_WDT_CLKDIV0_VAL 1
#define IFXMIPS_WDT_CLKDIV1_VAL 64
#define IFXMIPS_WDT_CLKDIV2_VAL 4096
#define IFXMIPS_WDT_CLKDIV3_VAL 262144
#define IFXMIPS_WDT_CLKDIV0 0
#define IFXMIPS_WDT_CLKDIV1 1
#define IFXMIPS_WDT_CLKDIV2 2
#define IFXMIPS_WDT_CLKDIV3 3
#endif

119
target/linux/ifxmips/files/include/asm-mips/danube/ifx_peripheral_definitions.h
View File

@ -1,119 +0,0 @@
//*************************************************************************
//* Summary of definitions which are used in each peripheral *
//*************************************************************************
#ifndef peripheral_definitions_h
#define peripheral_definitions_h
////#include "cpu.h"
//
///* These files have to be included by each peripheral */
//#include <sysdefs.h>
//#include <excep.h>
//#include <cpusubsys.h>
//#include <sys_api.h>
//#include <mips.h>
//#include "SRAM_address_map.h"
//
///* common header files for all CPU's */
//#include "iiu.h"
//#include "bcu.h"
//#include "FPI_address_map.h"
//#include "direct_interrupts.h"
/////////////////////////////////////////////////////////////////////////
//extern int _clz();
//extern void _nop();
//extern void _sleep();
//extern void sys_enable_int();
typedef unsigned char UINT8;
typedef signed char INT8;
typedef unsigned short UINT16;
typedef signed short INT16;
typedef unsigned int UINT32;
typedef signed int INT32;
typedef unsigned long long UINT64;
typedef signed long long INT64;
#define REG8( addr ) (*(volatile UINT8 *) (addr))
#define REG16( addr ) (*(volatile UINT16 *)(addr))
#define REG32( addr ) (*(volatile UINT32 *)(addr))
#define REG64( addr ) (*(volatile UINT64 *)(addr))
/* define routine to set FPI access in Supervisor Mode */
#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
/* Supervisor mode ends, following functions will be done in User mode */
#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
/* Supervisor mode ends, following functions will be done in User mode */
#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
/* Supervisor mode ends, following functions will be done in User mode */
#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
/* enable all Interrupts in IIU */
//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
///* get all high priority interrupt bits in IIU */
//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
///* signal ends of interrupt to IIU */
//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
///* force IIU interrupt register */
//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
///* get all bits of interrupt register */
//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
/* insert a NOP instruction */
#define NOP _nop()
/* CPU goes to power down mode until interrupt occurs */
#define IFX_CPU_SLEEP _sleep()
/* enable all interrupts to CPU */
#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
/* get all low priority interrupt bits in peripheral */
#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
/* clear low priority interrupt bit in peripheral */
#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
/* write FPI bus */
#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
/* read FPI bus */
#define READ_FPI_BYTE(addr) REG8(addr)
#define READ_FPI_16BIT(addr) REG16(addr)
#define READ_FPI_32BIT(addr) REG32(addr)
/* write peripheral register */
#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
#ifdef CONFIG_CPU_LITTLE_ENDIAN
#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
#else //not CONFIG_CPU_LITTLE_ENDIAN
#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
#endif //CONFIG_CPU_LITTLE_ENDIAN
/* read peripheral register */
#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
/* read/modify(or)/write peripheral register */
#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
/* read/modify(and)/write peripheral register */
#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
/* CPU-independent mnemonic constants */
/* CLC register bits */
#define IFX_CLC_ENABLE 0x00000000
#define IFX_CLC_DISABLE 0x00000001
#define IFX_CLC_DISABLE_STATUS 0x00000002
#define IFX_CLC_SUSPEND_ENABLE 0x00000004
#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
#define IFX_CLC_RUN_DIVIDER_OFFSET 8
#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
/* number of cycles to wait for interrupt service routine to be called */
#define WAIT_CYCLES 50
#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */

258
target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc.h
View File

@ -1,258 +0,0 @@
/*
* ifx_ssc.h defines some data sructures used in ifx_ssc.c
*
* Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
*
*
*/
#ifndef __IFX_SSC_H
#define __IFX_SSC_H
#ifdef __KERNEL__
#include <asm/ifxmips/ifx_ssc_defines.h>
#endif //__KERNEL__
#define PORT_CNT 1 // assume default value
/* symbolic constants to be used in SSC routines */
// ### TO DO: bad performance
#define IFX_SSC_TXFIFO_ITL 1
#define IFX_SSC_RXFIFO_ITL 1
struct ifx_ssc_statistics {
unsigned int abortErr; /* abort error */
unsigned int modeErr; /* master/slave mode error */
unsigned int txOvErr; /* TX Overflow error */
unsigned int txUnErr; /* TX Underrun error */
unsigned int rxOvErr; /* RX Overflow error */
unsigned int rxUnErr; /* RX Underrun error */
unsigned int rxBytes;
unsigned int txBytes;
};
struct ifx_ssc_hwopts {
unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */
unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */
unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */
unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */
unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */
unsigned int echoMode:1; /* Echo mode */
unsigned int loopBack:1; /* Loopback mode */
unsigned int idleValue:1; /* Idle value */
unsigned int clockPolarity:1; /* Idle clock is high or low */
unsigned int clockPhase:1; /* Tx on trailing or leading edge */
unsigned int headingControl:1; /* LSB first or MSB first */
unsigned int dataWidth:6; /* from 2 up to 32 bits */
unsigned int masterSelect:1; /* Master or Slave mode */
unsigned int modeRxTx:2; /* rx/tx mode */
unsigned int gpoCs:8; /* choose outputs to use for chip select */
unsigned int gpoInv:8; /* invert GPO outputs */
};
struct ifx_ssc_frm_opts {
bool FrameEnable; // SFCON.SFEN
unsigned int DataLength; // SFCON.DLEN
unsigned int PauseLength; // SFCON.PLEN
unsigned int IdleData; // SFCON.IDAT
unsigned int IdleClock; // SFCON.ICLK
bool StopAfterPause; // SFCON.STOP
};
struct ifx_ssc_frm_status {
bool DataBusy; // SFSTAT.DBSY
bool PauseBusy; // SFSTAT.PBSY
unsigned int DataCount; // SFSTAT.DCNT
unsigned int PauseCount; // SFSTAT.PCNT
bool EnIntAfterData; // SFCON.IBEN
bool EnIntAfterPause; // SFCON.IAEN
};
typedef struct {
char *buf;
size_t len;
} ifx_ssc_buf_item_t;
// data structures for batch execution
typedef union {
struct {
bool save_options;
} init;
ifx_ssc_buf_item_t read;
ifx_ssc_buf_item_t write;
ifx_ssc_buf_item_t rd_wr;
unsigned int set_baudrate;
struct ifx_ssc_frm_opts set_frm;
unsigned int set_gpo;
struct ifx_ssc_hwopts set_hwopts;
} ifx_ssc_batch_cmd_param;
struct ifx_ssc_batch_list {
unsigned int cmd;
ifx_ssc_batch_cmd_param cmd_param;
struct ifx_ssc_batch_list *next;
};
#ifdef __KERNEL__
#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
struct ifx_ssc_port {
unsigned long mapbase;
struct ifx_ssc_hwopts opts;
struct ifx_ssc_statistics stats;
struct ifx_ssc_frm_status frm_status;
struct ifx_ssc_frm_opts frm_opts;
/* wait queue for ifx_ssc_read() */
wait_queue_head_t rwait, pwait;
int port_nr;
char port_is_open; /* exclusive open - boolean */
// int no_of_bits; /* number of _valid_ bits */
// int elem_size; /* shift for element (no of bytes)*/
/* buffer and pointers to the read/write position */
char *rxbuf; /* buffer for RX */
char *rxbuf_end; /* buffer end pointer for RX */
volatile char *rxbuf_ptr; /* buffer write pointer for RX */
char *txbuf; /* buffer for TX */
char *txbuf_end; /* buffer end pointer for TX */
volatile char *txbuf_ptr; /* buffer read pointer for TX */
unsigned int baud;
/* each channel has its own interrupts */
/* (transmit/receive/error/frame) */
unsigned int txirq, rxirq, errirq, frmirq;
};
/* default values for SSC configuration */
// values of CON
#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
// other values
#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
#ifdef CONFIG_USE_EMULATOR
#define IFX_SSC_DEF_BAUDRATE 10000
#else
#define IFX_SSC_DEF_BAUDRATE 2000000
#endif
#define IFX_SSC_DEF_RMC 0x10
#define IFX_SSC_DEF_TXFIFO_FL 8
#define IFX_SSC_DEF_RXFIFO_FL 1
#if 1 //TODO
#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */
#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
#else
#error "what is ur Chip Select???"
#endif
#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
#if 0
#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
#endif
#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
IFX_SSC_R_BIT | IFX_SSC_E_BIT
#endif /* __KERNEL__ */
// batch execution commands
#define IFX_SSC_BATCH_CMD_INIT 1
#define IFX_SSC_BATCH_CMD_READ 2
#define IFX_SSC_BATCH_CMD_WRITE 3
#define IFX_SSC_BATCH_CMD_RD_WR 4
#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
#define IFX_SSC_BATCH_CMD_SET_FRM 7
#define IFX_SSC_BATCH_CMD_SET_GPO 8
#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
//#define IFX_SSC_BATCH_CMD_
//#define IFX_SSC_BATCH_CMD_
#define IFX_SSC_BATCH_CMD_END_EXEC 0
/* Macros to configure SSC hardware */
/* headingControl: */
#define IFX_SSC_LSB_FIRST 0
#define IFX_SSC_MSB_FIRST 1
/* dataWidth: */
#define IFX_SSC_MIN_DATA_WIDTH 2
#define IFX_SSC_MAX_DATA_WIDTH 32
/* master/slave mode select */
#define IFX_SSC_MASTER_MODE 1
#define IFX_SSC_SLAVE_MODE 0
/* rx/tx mode */
// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
#define IFX_SSC_MODE_RXTX 0
#define IFX_SSC_MODE_RX 1
#define IFX_SSC_MODE_TX 2
#define IFX_SSC_MODE_OFF 3
#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
/* GPO values */
#define IFX_SSC_MAX_GPO_OUT 7
#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
/***********************/
/* defines for ioctl's */
/***********************/
#define IFX_SSC_IOCTL_MAGIC 'S'
/* read out the statistics */
#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
/* clear the statistics */
#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
/* set the baudrate */
#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
/* get the current baudrate */
#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
/* set hardware options */
#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
/* get the current hardware options */
#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
/* set transmission mode */
#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
/* get the current transmission mode */
#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
/* abort transmission */
#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
/* set general purpose outputs */
#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
/* clear general purpose outputs */
#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
/* get general purpose outputs */
#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
/*** serial framing ***/
/* get status of serial framing */
#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
/* get counter reload values and control bits */
#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
/* set counter reload values and control bits */
#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
/*** batch execution ***/
/* do batch execution */
#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
#ifdef __KERNEL__
// routines from ifx_ssc.c
// ### TO DO
/* kernel interface for read and write */
ssize_t ifx_ssc_kread (int, char *, size_t);
ssize_t ifx_ssc_kwrite (int, const char *, size_t);
#ifdef CONFIG_IFX_VP_KERNEL_TEST
void ifx_ssc_tc (void);
#endif // CONFIG_IFX_VP_KERNEL_TEST
#endif //__KERNEL__
#endif // __IFX_SSC_H

547
target/linux/ifxmips/files/include/asm-mips/danube/ifx_ssc_defines.h
View File

@ -1,547 +0,0 @@
#ifndef IFX_SSC_DEFINES_H
#define IFX_SSC_DEFINES_H
#include "ifx_peripheral_definitions.h"
/* maximum SSC FIFO size */
#define IFX_SSC_MAX_FIFO_SIZE 32
/* register map of SSC */
/* address of the Clock Control Register of the SSC */
#define IFX_SSC_CLC 0x00000000
/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
bit 1 is hardware modified*/
#define IFX_SSC_CLC_readmask 0x00FFFFEF
#define IFX_SSC_CLC_writemask 0x00FFFF3D
#define IFX_SSC_CLC_hwmask 0x00000002
#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
/* address of Port Input Select Register of the SSC */
#define IFX_SSC_PISEL 0x00000004
/* IFX_SSC_PISEL register is significant in lowest three bits only */
#define IFX_SSC_PISEL_readmask 0x00000007
#define IFX_SSC_PISEL_writemask 0x00000007
#define IFX_SSC_PISEL_hwmask 0x00000000
#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
/* address of Identification Register of the SSC */
#define IFX_SSC_ID 0x00000008
/* IFX_SSC_ID register is significant in no bit */
#define IFX_SSC_ID_readmask 0x0000FF3F
#define IFX_SSC_ID_writemask 0x00000000
#define IFX_SSC_ID_hwmask 0x00000000
#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
/* address of the Control Register of the SSC */
#define IFX_SSC_CON 0x00000010
/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
#define IFX_SSC_CON_readmask 0x01DF1FFF
#define IFX_SSC_CON_writemask 0x01DF1FFF
#define IFX_SSC_CON_hwmask 0x00000000
#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
/* address of the Status Register of the SSC */
#define IFX_SSC_STATE 0x00000014
/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
all bits except 1:0 are hardware modified */
#define IFX_SSC_STATE_readmask 0x771F3F87
#define IFX_SSC_STATE_writemask 0x00000000
#define IFX_SSC_STATE_hwmask 0x771F3F84
#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
/* address of the Write Hardware Modified Control Register Bits of the SSC */
#define IFX_SSC_WHBSTATE 0x00000018
/* IFX_SSC_WHBSTATE register is write only */
#define IFX_SSC_WHBSTATE_readmask 0x00000000
#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
#define IFX_SSC_WHBSTATE_hwmask 0x00000000
#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
/* address of the Baudrate Timer Reload Register of the SSC */
#define IFX_SSC_BR 0x00000040
/* IFX_SSC_BR register is significant in bit 15 downto 0*/
#define IFX_SSC_BR_readmask 0x0000FFFF
#define IFX_SSC_BR_writemask 0x0000FFFF
#define IFX_SSC_BR_hwmask 0x00000000
#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
/* address of the Baudrate Timer Status Register of the SSC */
#define IFX_SSC_BRSTAT 0x00000044
/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
#define IFX_SSC_BRSTAT_readmask 0x0000FFFF
#define IFX_SSC_BRSTAT_writemask 0x00000000
#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
/* address of the Transmitter Buffer Register of the SSC */
#define IFX_SSC_TB 0x00000020
/* IFX_SSC_TB register is significant in bit 31 downto 0*/
#define IFX_SSC_TB_readmask 0xFFFFFFFF
#define IFX_SSC_TB_writemask 0xFFFFFFFF
#define IFX_SSC_TB_hwmask 0x00000000
#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
/* address of the Reciver Buffer Register of the SSC */
#define IFX_SSC_RB 0x00000024
/* IFX_SSC_RB register is significant in no bits*/
#define IFX_SSC_RB_readmask 0xFFFFFFFF
#define IFX_SSC_RB_writemask 0x00000000
#define IFX_SSC_RB_hwmask 0xFFFFFFFF
#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
/* address of the Receive FIFO Control Register of the SSC */
#define IFX_SSC_RXFCON 0x00000030
/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
#define IFX_SSC_RXFCON_readmask 0x00003F03
#define IFX_SSC_RXFCON_writemask 0x00003F03
#define IFX_SSC_RXFCON_hwmask 0x00000000
#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
/* address of the Transmit FIFO Control Register of the SSC */
#define IFX_SSC_TXFCON 0x00000034
/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
#define IFX_SSC_TXFCON_readmask 0x00003F03
#define IFX_SSC_TXFCON_writemask 0x00003F03
#define IFX_SSC_TXFCON_hwmask 0x00000000
#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
/* address of the FIFO Status Register of the SSC */
#define IFX_SSC_FSTAT 0x00000038
/* IFX_SSC_FSTAT register is significant in no bit*/
#define IFX_SSC_FSTAT_readmask 0x00003F3F
#define IFX_SSC_FSTAT_writemask 0x00000000
#define IFX_SSC_FSTAT_hwmask 0x00003F3F
#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
/* address of the Data Frame Control register of the SSC */
#define IFX_SSC_SFCON 0x00000060
#define IFX_SSC_SFCON_readmask 0xFFDFFFFD
#define IFX_SSC_SFCON_writemask 0xFFDFFFFD
#define IFX_SSC_SFCON_hwmask 0x00000000
#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
/* address of the Data Frame Status register of the SSC */
#define IFX_SSC_SFSTAT 0x00000064
#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
#define IFX_SSC_SFSTAT_writemask 0x00000000
#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
/* address of the General Purpose Output Control register of the SSC */
#define IFX_SSC_GPOCON 0x00000070
#define IFX_SSC_GPOCON_readmask 0x0000FFFF
#define IFX_SSC_GPOCON_writemask 0x0000FFFF
#define IFX_SSC_GPOCON_hwmask 0x00000000
#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
/* address of the General Purpose Output Status register of the SSC */
#define IFX_SSC_GPOSTAT 0x00000074
#define IFX_SSC_GPOSTAT_readmask 0x000000FF
#define IFX_SSC_GPOSTAT_writemask 0x00000000
#define IFX_SSC_GPOSTAT_hwmask 0x00000000
#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
/* address of the Force GPO Status register of the SSC */
#define IFX_SSC_WHBGPOSTAT 0x00000078
#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
/* address of the Receive Request Register of the SSC */
#define IFX_SSC_RXREQ 0x00000080
#define IFX_SSC_RXREQ_readmask 0x0000FFFF
#define IFX_SSC_RXREQ_writemask 0x0000FFFF
#define IFX_SSC_RXREQ_hwmask 0x00000000
#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
/* address of the Receive Count Register of the SSC */
#define IFX_SSC_RXCNT 0x00000084
#define IFX_SSC_RXCNT_readmask 0x0000FFFF
#define IFX_SSC_RXCNT_writemask 0x00000000
#define IFX_SSC_RXCNT_hwmask 0x0000FFFF
#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
/* address of the DMA Configuration Register of the SSC */
#define IFX_SSC_DMACON 0x000000EC
#define IFX_SSC_DMACON_readmask 0x0000FFFF
#define IFX_SSC_DMACON_writemask 0x00000000
#define IFX_SSC_DMACON_hwmask 0x0000FFFF
#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
//------------------------------------------------------
// interrupt register for enabling interrupts, mask register of irq_reg
#define IFX_SSC_IRN_EN 0xF4
// read/write
#define IFX_SSC_IRN_EN_readmask 0x0000000F
#define IFX_SSC_IRN_EN_writemask 0x0000000F
#define IFX_SSC_IRN_EN_hwmask 0x00000000
#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
// interrupt register for accessing interrupts
#define IFX_SSC_IRN_CR 0xF8
// read/write
#define IFX_SSC_IRN_CR_readmask 0x0000000F
#define IFX_SSC_IRN_CR_writemask 0x0000000F
#define IFX_SSC_IRN_CR_hwmask 0x0000000F
#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
// interrupt register for stimulating interrupts
#define IFX_SSC_IRN_ICR 0xFC
// read/write
#define IFX_SSC_IRN_ICR_readmask 0x0000000F
#define IFX_SSC_IRN_ICR_writemask 0x0000000F
#define IFX_SSC_IRN_ICR_hwmask 0x00000000
#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
//---------------------------------------------------------------------
// Number of IRQs and bitposition of IRQ
#define IFX_SSC_NUM_IRQ 4
#define IFX_SSC_T_BIT 0x00000001
#define IFX_SSC_R_BIT 0x00000002
#define IFX_SSC_E_BIT 0x00000004
#define IFX_SSC_F_BIT 0x00000008
/* bit masks for SSC registers */
/* ID register */
#define IFX_SSC_PERID_REV_MASK 0x0000001F
#define IFX_SSC_PERID_CFG_MASK 0x00000020
#define IFX_SSC_PERID_ID_MASK 0x0000FF00
#define IFX_SSC_PERID_REV_OFFSET 0
#define IFX_SSC_PERID_CFG_OFFSET 5
#define IFX_SSC_PERID_ID_OFFSET 8
#define IFX_SSC_PERID_ID 0x45
#define IFX_SSC_PERID_DMA_ON 0x00000020
#define IFX_SSC_PERID_RXFS_MASK 0x003F0000
#define IFX_SSC_PERID_RXFS_OFFSET 16
#define IFX_SSC_PERID_TXFS_MASK 0x3F000000
#define IFX_SSC_PERID_TXFS_OFFSET 24
/* PISEL register */
#define IFX_SSC_PISEL_MASTER_IN_A 0x0000
#define IFX_SSC_PISEL_MASTER_IN_B 0x0001
#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
/* IFX_SSC_CON register */
#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
#define IFX_SSC_CON_IDLE_HIGH 0x00800000
#define IFX_SSC_CON_IDLE_LOW 0x00000000
#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
#define IFX_SSC_CON_NO_LOOPBACK 0x00000000
#define IFX_SSC_CON_HALF_DUPLEX 0x00000080
#define IFX_SSC_CON_FULL_DUPLEX 0x00000000
#define IFX_SSC_CON_CLOCK_FALL 0x00000040
#define IFX_SSC_CON_CLOCK_RISE 0x00000000
#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
#define IFX_SSC_CON_MSB_FIRST 0x00000010
#define IFX_SSC_CON_LSB_FIRST 0x00000000
#define IFX_SSC_CON_ENABLE_CSB 0x00000008
#define IFX_SSC_CON_DISABLE_CSB 0x00000000
#define IFX_SSC_CON_INVERT_CSB 0x00000004
#define IFX_SSC_CON_TRUE_CSB 0x00000000
#define IFX_SSC_CON_RX_OFF 0x00000002
#define IFX_SSC_CON_RX_ON 0x00000000
#define IFX_SSC_CON_TX_OFF 0x00000001
#define IFX_SSC_CON_TX_ON 0x00000000
/* IFX_SSC_STATE register */
#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
#define IFX_SSC_STATE_BUSY 0x00002000
#define IFX_SSC_STATE_RX_UFL 0x00001000
#define IFX_SSC_STATE_TX_UFL 0x00000800
#define IFX_SSC_STATE_ABORT_ERR 0x00000400
#define IFX_SSC_STATE_RX_OFL 0x00000200
#define IFX_SSC_STATE_TX_OFL 0x00000100
#define IFX_SSC_STATE_MODE_ERR 0x00000080
#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
#define IFX_SSC_STATE_IS_MASTER 0x00000002
#define IFX_SSC_STATE_IS_ENABLED 0x00000001
/* WHBSTATE register */
#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
/* BR register */
#define IFX_SSC_BR_BAUDRATE_OFFSET 0
#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
/* BR_STAT register */
#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
/* TB register */
#define IFX_SSC_TB_DATA_OFFSET 0
#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
/* RB register */
#define IFX_SSC_RB_DATA_OFFSET 0
#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
/* RXFCON and TXFCON registers */
#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
#define IFX_SSC_XFCON_ITL_MASK 0x00003F00
#define IFX_SSC_XFCON_ITL_OFFSET 8
/* FSTAT register */
#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
/* GPOCON register */
#define IFX_SSC_GPOCON_INVOUT0_POS 0
#define IFX_SSC_GPOCON_INV_OUT0 0x00000001
#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
#define IFX_SSC_GPOCON_INVOUT1_POS 1
#define IFX_SSC_GPOCON_INV_OUT1 0x00000002
#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
#define IFX_SSC_GPOCON_INVOUT2_POS 2
#define IFX_SSC_GPOCON_INV_OUT2 0x00000003
#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
#define IFX_SSC_GPOCON_INVOUT3_POS 3
#define IFX_SSC_GPOCON_INV_OUT3 0x00000008
#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
#define IFX_SSC_GPOCON_INVOUT4_POS 4
#define IFX_SSC_GPOCON_INV_OUT4 0x00000010
#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
#define IFX_SSC_GPOCON_INVOUT5_POS 5
#define IFX_SSC_GPOCON_INV_OUT5 0x00000020
#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
#define IFX_SSC_GPOCON_INVOUT6_POS 6
#define IFX_SSC_GPOCON_INV_OUT6 0x00000040
#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
#define IFX_SSC_GPOCON_INVOUT7_POS 7
#define IFX_SSC_GPOCON_INV_OUT7 0x00000080
#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
#define IFX_SSC_GPOCON_ISCSB0_POS 8
#define IFX_SSC_GPOCON_IS_CSB0 0x00000100
#define IFX_SSC_GPOCON_IS_GPO0 0x00000000
#define IFX_SSC_GPOCON_ISCSB1_POS 9
#define IFX_SSC_GPOCON_IS_CSB1 0x00000200
#define IFX_SSC_GPOCON_IS_GPO1 0x00000000
#define IFX_SSC_GPOCON_ISCSB2_POS 10
#define IFX_SSC_GPOCON_IS_CSB2 0x00000400
#define IFX_SSC_GPOCON_IS_GPO2 0x00000000
#define IFX_SSC_GPOCON_ISCSB3_POS 11
#define IFX_SSC_GPOCON_IS_CSB3 0x00000800
#define IFX_SSC_GPOCON_IS_GPO3 0x00000000
#define IFX_SSC_GPOCON_ISCSB4_POS 12
#define IFX_SSC_GPOCON_IS_CSB4 0x00001000
#define IFX_SSC_GPOCON_IS_GPO4 0x00000000
#define IFX_SSC_GPOCON_ISCSB5_POS 13
#define IFX_SSC_GPOCON_IS_CSB5 0x00002000
#define IFX_SSC_GPOCON_IS_GPO5 0x00000000
#define IFX_SSC_GPOCON_ISCSB6_POS 14
#define IFX_SSC_GPOCON_IS_CSB6 0x00004000
#define IFX_SSC_GPOCON_IS_GPO6 0x00000000
#define IFX_SSC_GPOCON_ISCSB7_POS 15
#define IFX_SSC_GPOCON_IS_CSB7 0x00008000
#define IFX_SSC_GPOCON_IS_GPO7 0x00000000
#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
/* GPOSTAT register */
#define IFX_SSC_GPOSTAT_OUT0 0x00000001
#define IFX_SSC_GPOSTAT_OUT1 0x00000002
#define IFX_SSC_GPOSTAT_OUT2 0x00000004
#define IFX_SSC_GPOSTAT_OUT3 0x00000008
#define IFX_SSC_GPOSTAT_OUT4 0x00000010
#define IFX_SSC_GPOSTAT_OUT5 0x00000020
#define IFX_SSC_GPOSTAT_OUT6 0x00000040
#define IFX_SSC_GPOSTAT_OUT7 0x00000080
#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
/* WHBGPOSTAT register */
#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
/* SFCON register */
#define IFX_SSC_SFCON_SF_ENABLE 0x00000001
#define IFX_SSC_SFCON_SF_DISABLE 0x00000000
#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
/* SFSTAT register */
#define IFX_SSC_SFSTAT_IN_DATA 0x00000001
#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
/* RXREQ register */
#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
/* RXCNT register */
#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
#define IFX_SSC_RXCNT_TODO_OFFSET 0
/* DMACON register */
#define IFX_SSC_DMACON_RXON 0x00000001
#define IFX_SSC_DMACON_RXOFF 0x00000000
#define IFX_SSC_DMACON_TXON 0x00000002
#define IFX_SSC_DMACON_TXOFF 0x00000000
#define IFX_SSC_DMACON_DMAON 0x00000003
#define IFX_SSC_DMACON_DMAOFF 0x00000000
#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
#define IFX_SSC_DMACON_CLASS_OFFSET 2
/* register access macros */
#define ifx_ssc_fstat_received_words(status) (status & 0x003F)
#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
#endif

8
target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h
View File

@ -1,8 +0,0 @@
#ifndef __IFXMIPS_IRQ_H
#define __IFXMIPS_IRQ_H
#define NR_IRQS 256
#include_next <irq.h>
#endif