mirror of https://github.com/hak5/openwrt.git
layerscape: add LS1021AIOT board support
The LS1021A-IoT gateway reference design based on the QorIQ LS1021A processor is a purpose-built, small footprint hardware platform with a wide array of high-speed connectivity and low-speed serial interfaces to support secure delivery of IoT services for home, business or other commercial location. - Combines standards-based, open source software with a feature-rich IoT gateway design to establish a common, open framework for secured IoT service delivery and management. - Provides a wide assortment of high-speed and serial-based connectivity in a compact, highly secure design. - High efficiency through the use of the Arm-based QorIQ LS1021A embedded processor. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com>openwrt-19.07
parent
0a827ebd2f
commit
328530c6e7
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@ -92,6 +92,15 @@ define U-Boot/ls1021atwr-sdboot
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ENV_SIZE:=0x20000
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endef
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define U-Boot/ls1021aiot-sdboot
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NAME:=NXP LS1021AIOT SD Card Boot
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BUILD_SUBTARGET:=armv7
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UBOOT_CONFIG:=ls1021aiot_sdcard
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UBOOT_IMAGE:=u-boot-with-spl-pbl.bin
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ENV_SIZE:=0x2000
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endef
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UBOOT_TARGETS := \
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ls1012ardb \
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ls1012afrwy \
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@ -103,7 +112,8 @@ UBOOT_TARGETS := \
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ls1088ardb-sdboot \
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ls2088ardb \
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ls1021atwr \
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ls1021atwr-sdboot
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ls1021atwr-sdboot \
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ls1021aiot-sdboot
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define Build/InstallDev
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$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
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@ -0,0 +1,8 @@
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fdtaddr=0x8f000000
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loadaddr=0x81000000
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fdt_high=0xffffffff
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initrd_high=0xffffffff
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sd_boot=mmc read ${fdtaddr} 7800 800;mmc read ${loadaddr} 8000 8000;bootm ${loadaddr} - ${fdtaddr}
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bootargs=root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
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bootcmd=echo starting openwrt ...;run sd_boot
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bootdelay=3
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@ -11,8 +11,8 @@ Layerscape Quick Start
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LS1012ARDB LS1012AFRWY LS1043ARDB LS1046ARDB
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* ARMv7
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LS1021ATWR
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(SD card boot support on LS1021ATWR)
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LS1021ATWR LS1021AIOT
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(SD card boot support on LS1021ATWR/LS1021AIOT)
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2. Build
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@ -45,3 +45,19 @@ define Device/ls1021atwr-sdboot
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append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
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endef
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TARGET_DEVICES += ls1021atwr-sdboot
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define Device/ls1021aiot-sdboot
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DEVICE_TITLE := LS1021AIOT (SD Card Boot)
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DEVICE_DTS := ls1021a-iot
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FILESYSTEMS := ext4
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IMAGES := sdcard.img
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IMAGE/sdcard.img := \
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ls-clean | \
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ls-append-sdhead $(1) | pad-to 4K | \
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ls-append $(1)-uboot.bin | pad-to 1M | \
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ls-append $(1)-uboot-env.bin | pad-to 15M | \
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ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
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append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
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append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
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endef
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TARGET_DEVICES += ls1021aiot-sdboot
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@ -0,0 +1,289 @@
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From bb1a53f1bcb3f4c5983955a1d419c0e4e2531043 Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Fri, 26 Oct 2018 16:00:37 +0800
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Subject: [PATCH 06/40] arm: dts: ls1021a: Add LS1021A-IOT board support
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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---
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arch/arm/boot/dts/Makefile | 3 +-
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arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++
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2 files changed, 264 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -496,7 +496,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
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imx7s-warp.dtb
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dtb-$(CONFIG_SOC_LS1021A) += \
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ls1021a-qds.dtb \
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- ls1021a-twr.dtb
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+ ls1021a-twr.dtb \
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+ ls1021a-iot.dtb
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dtb-$(CONFIG_SOC_VF610) += \
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vf500-colibri-eval-v3.dtb \
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vf610-colibri-eval-v3.dtb \
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--- /dev/null
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+++ b/arch/arm/boot/dts/ls1021a-iot.dts
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@@ -0,0 +1,262 @@
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+/*
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+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+/dts-v1/;
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+#include "ls1021a.dtsi"
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+
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+/ {
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+ model = "LS1021A IOT Board";
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+
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+ sys_mclk: clock-mclk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <24576000>;
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+ };
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+
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+ regulators {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ reg_3p3v: regulator@0 {
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+ compatible = "regulator-fixed";
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+ reg = <0>;
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+ regulator-name = "3P3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_2p5v: regulator@1 {
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+ compatible = "regulator-fixed";
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+ reg = <1>;
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+ regulator-name = "2P5V";
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+ regulator-min-microvolt = <2500000>;
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+ regulator-max-microvolt = <2500000>;
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+ regulator-always-on;
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+ };
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+ };
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+
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+ sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,widgets =
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+ "Microphone", "Microphone Jack",
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+ "Headphone", "Headphone Jack",
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+ "Speaker", "Speaker Ext",
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+ "Line", "Line In Jack";
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+ simple-audio-card,routing =
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+ "MIC_IN", "Microphone Jack",
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+ "Microphone Jack", "Mic Bias",
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+ "LINE_IN", "Line In Jack",
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+ "Headphone Jack", "HP_OUT",
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+ "Speaker Ext", "LINE_OUT";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&sai2>;
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+ frame-master;
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+ bitclock-master;
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+ };
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+
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+ simple-audio-card,codec {
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+ sound-dai = <&codec>;
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+ frame-master;
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+ bitclock-master;
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+ };
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+ };
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+
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+ firmware {
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+ optee {
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+ compatible = "linaro,optee-tz";
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+ method = "smc";
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+ };
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+ };
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+};
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+
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+&enet0 {
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+ tbi-handle = <&tbi1>;
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+ phy-handle = <&phy1>;
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+ phy-connection-type = "sgmii";
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+ status = "okay";
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+};
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+
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+&enet1 {
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+ tbi-handle = <&tbi1>;
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+ phy-handle = <&phy3>;
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+ phy-connection-type = "sgmii";
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+ status = "okay";
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+};
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+
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+&enet2 {
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+ fixed-link = <0 1 1000 0 0>;
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+ phy-connection-type = "rgmii-id";
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+ status = "okay";
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+};
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+
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+&can0{
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+ status = "disabled";
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+};
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+
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+&can1{
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+ status = "disabled";
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+};
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+
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+&can2{
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+ status = "disabled";
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+};
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+
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+&can3{
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+ status = "okay";
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+};
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+
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+&esdhc{
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ max1239@35 {
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+ compatible = "maxim,max1239";
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+ reg = <0x35>;
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+ #io-channel-cells = <1>;
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+ };
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+
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+ codec: sgtl5000@2a {
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+ #sound-dai-cells=<0x0>;
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+ compatible = "fsl,sgtl5000";
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+ reg = <0x2a>;
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+ VDDA-supply = <®_3p3v>;
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+ VDDIO-supply = <®_2p5v>;
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+ clocks = <&sys_mclk 1>;
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+ };
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+
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+ pca9555: pca9555@23 {
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+ compatible = "nxp,pca9555";
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+ /*pinctrl-names = "default";*/
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+ /*interrupt-parent = <&gpio2>;
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+ interrupts = <19 0x2>;*/
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ reg = <0x23>;
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+ };
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+
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+ ina220@44 {
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+ compatible = "ti,ina220";
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+ reg = <0x44>;
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+ shunt-resistor = <1000>;
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+ };
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+
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+ ina220@45 {
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+ compatible = "ti,ina220";
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+ reg = <0x45>;
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+ shunt-resistor = <1000>;
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+ };
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+
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+ lm75b@48 {
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+ compatible = "nxp,lm75a";
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+ reg = <0x48>;
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+ };
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+
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+ adt7461a@4c {
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+ compatible = "adt7461a";
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+ reg = <0x4c>;
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+ };
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+
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+ hdmi: sii9022a@39 {
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+ compatible = "fsl,sii902x";
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+ reg = <0x39>;
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+ interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
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+ };
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+};
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+
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+&i2c1 {
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+ status = "disabled";
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+};
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+
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+&ifc {
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+ status = "disabled";
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+};
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+
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+&lpuart0 {
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+ status = "okay";
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+};
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+
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+&mdio0 {
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+ phy0: ethernet-phy@0 {
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+ reg = <0x0>;
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+ };
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+ phy1: ethernet-phy@1 {
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+ reg = <0x1>;
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+ };
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+ phy2: ethernet-phy@2 {
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+ reg = <0x2>;
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+ };
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+ phy3: ethernet-phy@3 {
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+ reg = <0x3>;
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+ };
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+ tbi1: tbi-phy@1f {
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+ reg = <0x1f>;
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+ device_type = "tbi-phy";
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+ };
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+};
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+
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+&qspi {
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+ num-cs = <2>;
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+ status = "okay";
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+
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+ qflash0: s25fl128s@0 {
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+ compatible = "spansion,s25fl129p1";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ };
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+};
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+
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+&sai2 {
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+ status = "okay";
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ status = "okay";
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+};
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+
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+&dcu {
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+ display = <&display>;
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+ status = "okay";
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+
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+ display: display@0 {
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+ bits-per-pixel = <24>;
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+
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+ display-timings {
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+ native-mode = <&timing0>;
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+
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+ timing0: mode0 {
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+ clock-frequency = <25000000>;
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+ hactive = <640>;
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+ vactive = <480>;
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+ hback-porch = <80>;
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+ hfront-porch = <80>;
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+ vback-porch = <16>;
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+ vfront-porch = <16>;
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+ hsync-len = <12>;
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+ vsync-len = <2>;
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+ hsync-active = <1>;
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+ vsync-active = <1>;
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+ };
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+ };
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+ };
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+};
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