mirror of https://github.com/hak5/openwrt.git
parent
1a0a584ea6
commit
26df9231fa
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@ -0,0 +1,34 @@
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--- a/arch/mips/kernel/cpu-probe.c
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+++ b/arch/mips/kernel/cpu-probe.c
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@@ -934,8 +934,8 @@ static inline void cpu_probe_broadcom(st
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c->options |= MIPS_CPU_ULRI;
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break;
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case PRID_IMP_BMIPS4KC:
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- c->cputype = CPU_4KC;
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- __cpu_name[cpu] = "MIPS 4Kc";
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+ c->cputype = CPU_BMIPS4KC;
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+ __cpu_name[cpu] = "Broadcom BMIPS4Kc";
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break;
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}
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}
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--- a/arch/mips/include/asm/cpu.h
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+++ b/arch/mips/include/asm/cpu.h
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@@ -227,7 +227,7 @@ enum cpu_type_enum {
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*/
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
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CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
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- CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
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+ CPU_BMIPS4380, CPU_BMIPS4KC, CPU_BMIPS5000, CPU_JZRISC,
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/*
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* MIPS64 class processors
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -342,6 +342,7 @@ static void __cpuinit build_tlb_write_en
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case CPU_BMIPS3300:
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case CPU_BMIPS4350:
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case CPU_BMIPS4380:
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+ case CPU_BMIPS4KC:
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case CPU_BMIPS5000:
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case CPU_LOONGSON2:
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case CPU_R5500:
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@ -1,193 +0,0 @@
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -10,9 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpu.h>
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-#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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-#include <asm/mipsregs.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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@@ -298,24 +296,26 @@ void __init bcm63xx_cpu_init(void)
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expected_cpu_id = 0;
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switch (c->cputype) {
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- case CPU_BMIPS3300:
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- if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
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- expected_cpu_id = BCM6348_CPU_ID;
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- bcm63xx_regs_base = bcm96348_regs_base;
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- bcm63xx_irqs = bcm96348_irqs;
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- } else {
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- __cpu_name[cpu] = "Broadcom BCM6338";
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- expected_cpu_id = BCM6338_CPU_ID;
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- bcm63xx_regs_base = bcm96338_regs_base;
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- bcm63xx_irqs = bcm96338_irqs;
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- }
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+ /*
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+ * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
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+ */
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+ case CPU_BCM3302:
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+ __cpu_name[cpu] = "Broadcom BCM6338";
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+ expected_cpu_id = BCM6338_CPU_ID;
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+ bcm63xx_regs_base = bcm96338_regs_base;
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+ bcm63xx_irqs = bcm96338_irqs;
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break;
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- case CPU_BMIPS32:
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+ case CPU_BCM6345:
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expected_cpu_id = BCM6345_CPU_ID;
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bcm63xx_regs_base = bcm96345_regs_base;
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bcm63xx_irqs = bcm96345_irqs;
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break;
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- case CPU_BMIPS4350:
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+ case CPU_BCM6348:
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+ expected_cpu_id = BCM6348_CPU_ID;
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+ bcm63xx_regs_base = bcm96348_regs_base;
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+ bcm63xx_irqs = bcm96348_irqs;
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+ break;
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+ case CPU_BCM6358:
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expected_cpu_id = BCM6358_CPU_ID;
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bcm63xx_regs_base = bcm96358_regs_base;
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bcm63xx_irqs = bcm96358_irqs;
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--- a/arch/mips/include/asm/cpu.h
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+++ b/arch/mips/include/asm/cpu.h
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@@ -111,16 +111,14 @@
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* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
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*/
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-#define PRID_IMP_BMIPS4KC 0x4000
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-#define PRID_IMP_BMIPS32 0x8000
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-#define PRID_IMP_BMIPS3300 0x9000
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-#define PRID_IMP_BMIPS3300_ALT 0x9100
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-#define PRID_IMP_BMIPS3300_BUG 0x0000
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-#define PRID_IMP_BMIPS43XX 0xa000
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-#define PRID_IMP_BMIPS5000 0x5a00
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-
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-#define PRID_REV_BMIPS4380_LO 0x0040
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-#define PRID_REV_BMIPS4380_HI 0x006f
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+#define PRID_IMP_BCM4710 0x4000
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+#define PRID_IMP_BCM3302 0x9000
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+#define PRID_IMP_BCM6338 0x9000
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+#define PRID_IMP_BCM6345 0x8000
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+#define PRID_IMP_BCM6348 0x9100
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+#define PRID_IMP_BCM4350 0xA000
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+#define PRID_REV_BCM6358 0x0010
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+#define PRID_REV_BCM6368 0x0030
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
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@@ -226,8 +224,9 @@ enum cpu_type_enum {
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* MIPS32 class processors
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*/
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
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- CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
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- CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
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+ CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
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+ CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
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+ CPU_JZRISC,
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/*
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* MIPS64 class processors
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--- a/arch/mips/kernel/cpu-probe.c
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+++ b/arch/mips/kernel/cpu-probe.c
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@@ -183,10 +183,10 @@ void __init check_wait(void)
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case CPU_5KC:
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case CPU_25KF:
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case CPU_PR4450:
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- case CPU_BMIPS3300:
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- case CPU_BMIPS4350:
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- case CPU_BMIPS4380:
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- case CPU_BMIPS5000:
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+ case CPU_BCM3302:
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+ case CPU_BCM6338:
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+ case CPU_BCM6348:
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+ case CPU_BCM6358:
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case CPU_CAVIUM_OCTEON:
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case CPU_CAVIUM_OCTEON_PLUS:
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case CPU_CAVIUM_OCTEON2:
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@@ -905,37 +905,33 @@ static inline void cpu_probe_broadcom(st
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{
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decode_configs(c);
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switch (c->processor_id & 0xff00) {
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- case PRID_IMP_BMIPS32:
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- c->cputype = CPU_BMIPS32;
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- __cpu_name[cpu] = "Broadcom BMIPS32";
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- break;
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- case PRID_IMP_BMIPS3300:
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- case PRID_IMP_BMIPS3300_ALT:
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- case PRID_IMP_BMIPS3300_BUG:
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- c->cputype = CPU_BMIPS3300;
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- __cpu_name[cpu] = "Broadcom BMIPS3300";
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- break;
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- case PRID_IMP_BMIPS43XX: {
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- int rev = c->processor_id & 0xff;
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-
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- if (rev >= PRID_REV_BMIPS4380_LO &&
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- rev <= PRID_REV_BMIPS4380_HI) {
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- c->cputype = CPU_BMIPS4380;
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- __cpu_name[cpu] = "Broadcom BMIPS4380";
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- } else {
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- c->cputype = CPU_BMIPS4350;
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- __cpu_name[cpu] = "Broadcom BMIPS4350";
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- }
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- break;
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- }
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- case PRID_IMP_BMIPS5000:
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- c->cputype = CPU_BMIPS5000;
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- __cpu_name[cpu] = "Broadcom BMIPS5000";
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- c->options |= MIPS_CPU_ULRI;
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+ case PRID_IMP_BCM3302:
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+ /* same as PRID_IMP_BCM6338 */
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+ c->cputype = CPU_BCM3302;
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+ __cpu_name[cpu] = "Broadcom BCM3302";
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+ break;
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+ case PRID_IMP_BCM4710:
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+ c->cputype = CPU_BCM4710;
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+ __cpu_name[cpu] = "Broadcom BCM4710";
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+ break;
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+ case PRID_IMP_BCM6345:
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+ c->cputype = CPU_BCM6345;
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+ __cpu_name[cpu] = "Broadcom BCM6345";
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+ break;
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+ case PRID_IMP_BCM6348:
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+ c->cputype = CPU_BCM6348;
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+ __cpu_name[cpu] = "Broadcom BCM6348";
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break;
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- case PRID_IMP_BMIPS4KC:
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- c->cputype = CPU_4KC;
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- __cpu_name[cpu] = "MIPS 4Kc";
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+ case PRID_IMP_BCM4350:
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+ switch (c->processor_id & 0xf0) {
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+ case PRID_REV_BCM6358:
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+ c->cputype = CPU_BCM6358;
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+ __cpu_name[cpu] = "Broadcom BCM6358";
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+ break;
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+ default:
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+ c->cputype = CPU_UNKNOWN;
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+ break;
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+ }
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break;
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}
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}
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -338,12 +338,13 @@ static void __cpuinit build_tlb_write_en
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case CPU_4KSC:
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case CPU_20KC:
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case CPU_25KF:
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- case CPU_BMIPS32:
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- case CPU_BMIPS3300:
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- case CPU_BMIPS4350:
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- case CPU_BMIPS4380:
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- case CPU_BMIPS5000:
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+ case CPU_BCM3302:
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+ case CPU_BCM4710:
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case CPU_LOONGSON2:
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+ case CPU_BCM6338:
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+ case CPU_BCM6345:
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+ case CPU_BCM6348:
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+ case CPU_BCM6358:
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case CPU_R5500:
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if (m4kc_tlbp_war())
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uasm_i_nop(p);
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@ -299,7 +299,7 @@
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* silly idea of putting something else there ...
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*/
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switch (current_cpu_type()) {
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+ case CPU_BCM3302:
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+ case CPU_BMIPS3300:
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+ {
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+ u32 cm;
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+ cm = read_c0_diag();
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM47XX
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+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ if (current_cpu_data.cputype == CPU_BMIPS4KC && (current_cpu_data.processor_id & 0xff) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ } else
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