mirror of https://github.com/hak5/openwrt.git
sunxi: H3: add device tree changes for H3 Ethernet
This adds the device tree changes needed to make the GMAC stmmac driver working for the Allwinner H3 SoCs. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>openwrt-18.06
Hauke Mehrtens
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25abd71efb
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From d91d3daf5de90e0118227d8ddcb7bb4ff40c1b91 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:37 +0200
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Subject: arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module
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This patch add the dt node for the syscon register present on the
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Allwinner H3/H5
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Only two register are present in this syscon and the only one useful is
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the one dedicated to EMAC clock..
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -140,6 +140,12 @@
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#size-cells = <1>;
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ranges;
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+ syscon: syscon@1c00000 {
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+ compatible = "allwinner,sun8i-h3-system-controller",
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+ "syscon";
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+ reg = <0x01c00000 0x1000>;
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+ };
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+
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun8i-h3-dma";
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reg = <0x01c02000 0x1000>;
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@ -0,0 +1,67 @@
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From 0eba511a3cac29d6338b22b5b727f40cf8d163df Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:38 +0200
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Subject: arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver
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The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
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speed.
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This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree.
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SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 34 ++++++++++++++++++++++++++++++++++
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1 file changed, 34 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -333,6 +333,14 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ emac_rgmii_pins: emac0 {
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+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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+ "PD5", "PD7", "PD8", "PD9", "PD10",
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+ "PD12", "PD13", "PD15", "PD16", "PD17";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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i2c0_pins: i2c0 {
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allwinner,pins = "PA11", "PA12";
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allwinner,function = "i2c0";
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@@ -431,6 +439,32 @@
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clocks = <&osc24M>;
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};
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+ emac: ethernet@1c30000 {
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+ compatible = "allwinner,sun8i-h3-emac";
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+ syscon = <&syscon>;
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+ reg = <0x01c30000 0x104>;
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+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+ resets = <&ccu RST_BUS_EMAC>;
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+ reset-names = "stmmaceth";
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+ clocks = <&ccu CLK_BUS_EMAC>;
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+ clock-names = "stmmaceth";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+
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+ mdio: mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ int_mii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ clocks = <&ccu CLK_BUS_EPHY>;
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+ resets = <&ccu RST_BUS_EPHY>;
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+ };
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+ };
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+ };
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+
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wdt0: watchdog@01c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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@ -0,0 +1,40 @@
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From a9992f2dd1890112643a93d621ff5a4c97c55d53 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:42 +0200
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Subject: arm: sun8i: orangepi-2: Enable dwmac-sun8i
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The dwmac-sun8i hardware is present on the Orange PI 2.
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It uses the internal PHY.
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This patch create the needed emac node.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
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@@ -55,6 +55,7 @@
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aliases {
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serial0 = &uart0;
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/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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+ ethernet0 = &emac;
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ethernet1 = &rtl8189;
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};
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@@ -109,6 +110,13 @@
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status = "okay";
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};
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+&emac {
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+ phy-handle = <&int_mii_phy>;
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+ phy-mode = "mii";
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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&ir {
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pinctrl-names = "default";
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pinctrl-0 = <&ir_pins_a>;
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@ -0,0 +1,64 @@
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From 1dcd0095019aca7533eaeed9475d995a4eb30137 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Mon, 5 Jun 2017 21:21:26 +0200
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Subject: ARM: sun8i: orangepi-plus: Enable dwmac-sun8i
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The dwmac-sun8i hardware is present on the Orange PI plus.
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It uses an external PHY rtl8211e via RGMII.
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This patch create the needed regulator, emac and phy nodes.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 32 ++++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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@@ -47,6 +47,20 @@
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model = "Xunlong Orange Pi Plus / Plus 2";
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compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
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+ aliases {
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+ ethernet0 = &emac;
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+ };
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+
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+ reg_gmac_3v3: gmac-3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "gmac-3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <100000>;
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+ enable-active-high;
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+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
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+ };
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+
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reg_usb3_vbus: usb3-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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@@ -64,6 +78,24 @@
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status = "okay";
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};
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emac_rgmii_pins>;
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+ phy-supply = <®_gmac_3v3>;
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-mode = "rgmii";
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+
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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+&mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+ };
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+};
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+
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_8bit_pins>;
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@ -0,0 +1,26 @@
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From 072b6e3692532b6281bf781ded1c7a986ac17471 Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Thu, 6 Jul 2017 10:53:34 +0200
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Subject: ARM: dts: sunxi: h3/h5: Correct emac register size
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The datasheet said that emac register size is 0x10000 not 0x104
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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[wens@csie.org: Fixed commit subject prefix]
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -442,7 +442,7 @@
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emac: ethernet@1c30000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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- reg = <0x01c30000 0x104>;
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+ reg = <0x01c30000 0x10000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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