mediatek: sync patches and add more ethernet stability fixes

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 49265
lede-17.01
blogic 2016-04-29 11:34:31 +00:00 committed by Jo-Philipp Wich
parent dd16b7748d
commit 23596ca527
95 changed files with 436 additions and 608 deletions

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@ -3035,6 +3035,8 @@ CONFIG_PROC_SYSCTL=y
# CONFIG_PWM_FSL_FTM is not set
# CONFIG_PWM_PCA9685 is not set
# CONFIG_QCA7000 is not set
# CONFIG_QCOM_SPMI_IADC is not set
# CONFIG_QCOM_SPMI_VADC is not set
# CONFIG_QED is not set
# CONFIG_QLA3XXX is not set
# CONFIG_QLCNIC is not set
@ -3822,6 +3824,7 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set
# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set
# CONFIG_SND_SOC_INTEL_SST is not set
# CONFIG_SND_SOC_MEDIATEK is not set
# CONFIG_SND_SOC_MPC5200_AC97 is not set
# CONFIG_SND_SOC_MPC5200_I2S is not set
# CONFIG_SND_SOC_PCM1681 is not set

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@ -10,6 +10,9 @@ mediatek_board_detect() {
machine=$(cat /proc/device-tree/model)
case "$machine" in
"MediaTek MT7623 evaluation board")
name="mt7623_evb"
;;
"MediaTek MT7623 eMMC evaluation board")
name="eMMC"
;;

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@ -1,430 +0,0 @@
# CONFIG_AIO is not set
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APM_EMULATION is not set
# CONFIG_ARCH_ALPINE is not set
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MT7623=y
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_ARM=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
# CONFIG_ARM_CRYPTO is not set
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
# CONFIG_ARM_LPAE is not set
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_AVERAGE=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLEANCACHE=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLKSRC_OF=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="earlyprintk console=ttyS0,115200"
CONFIG_COMMON_CLK=y
CONFIG_COMPACTION=y
CONFIG_COREDUMP=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_HAS_ASID=y
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_XZ=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_GPIO=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
# CONFIG_DEBUG_MT6589_UART0 is not set
CONFIG_DEBUG_MT8127_UART0=y
# CONFIG_DEBUG_MT8135_UART3 is not set
CONFIG_DEBUG_PREEMPT=y
CONFIG_DEBUG_UART_8250=y
# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
CONFIG_DEBUG_UART_8250_SHIFT=2
# CONFIG_DEBUG_UART_8250_WORD is not set
CONFIG_DEBUG_UART_PHYS=0x11004000
CONFIG_DEBUG_UART_VIRT=0xf1004000
CONFIG_DEBUG_UNCOMPRESS=y
# CONFIG_DEBUG_USER is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DEVMEM=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DTC=y
# CONFIG_DW_DMAC_PCI is not set
CONFIG_EARLY_PRINTK=y
CONFIG_ELF_CORE=y
CONFIG_ESW_DOUBLE_VLAN_TAG=y
CONFIG_FREEZER=y
CONFIG_GE1_RGMII_AN=y
# CONFIG_GE1_RGMII_FORCE_1000 is not set
# CONFIG_GE1_RGMII_NONE is not set
# CONFIG_GE1_TRGMII_FORCE_2000 is not set
# CONFIG_GE1_TRGMII_FORCE_2600 is not set
CONFIG_GE2_INTERNAL_GPHY=y
# CONFIG_GE2_MII_AN is not set
# CONFIG_GE2_MII_FORCE_100 is not set
# CONFIG_GE2_RGMII_AN is not set
# CONFIG_GE2_RGMII_FORCE_1000 is not set
# CONFIG_GE2_RVMII_FORCE_100 is not set
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GE_RGMII_INTERNAL_P0_AN=y
CONFIG_GIGAPHY=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_DEVRES=y
CONFIG_GPIO_SYSFS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_BPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_SMP=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_UID16=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HOTPLUG_CPU=y
# CONFIG_HSU_DMA_PCI is not set
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
# CONFIG_HW_SFQ is not set
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IOMMU_HELPER=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_KALLSYMS=y
CONFIG_LAN_WAN_SUPPORT=y
# CONFIG_LEDS_REGULATOR is not set
CONFIG_LIBFDT=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_LOCK_SPIN_ON_OWNER=y
# CONFIG_LZ4_COMPRESS is not set
# CONFIG_LZ4_DECOMPRESS is not set
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MACH_MT6589 is not set
# CONFIG_MACH_MT6592 is not set
CONFIG_MACH_MT7623=y
CONFIG_MACH_MT8127=y
# CONFIG_MACH_MT8135 is not set
CONFIG_MAC_TO_GIGAPHY_MODE_ADDR=0x1F
CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2=0
CONFIG_MAGIC_SYSRQ=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MDIO_GPIO=y
CONFIG_MEDIATEK_WATCHDOG=y
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MT6323 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_SCPSYS=y
# CONFIG_MTK_SMB_HOOK is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
CONFIG_MULTI_IRQ_HANDLER=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
# CONFIG_NEON is not set
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NLS=y
CONFIG_NO_BOOTMEM=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_ADDRESS_PCI=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
# CONFIG_PCIE_IPROC is not set
# CONFIG_PCI_DOMAINS_GENERIC is not set
CONFIG_PCI_MSI=y
CONFIG_PDMA_NEW=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_AMD is not set
# CONFIG_PINCTRL_MT6397 is not set
CONFIG_PINCTRL_MT7623=y
CONFIG_PINCTRL_MT8127=y
# CONFIG_PINCTRL_MT8135 is not set
CONFIG_PINCTRL_MTK_COMMON=y
CONFIG_PM=y
CONFIG_PM_CLK=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_BRCMSTB is not set
# CONFIG_POWER_RESET_GPIO is not set
# CONFIG_POWER_RESET_GPIO_RESTART is not set
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_SYSCON is not set
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
CONFIG_POWER_SUPPLY=y
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_RCU=y
CONFIG_PRINTK_TIME=y
CONFIG_RAETH=y
CONFIG_RAETH_CHECKSUM_OFFLOAD=y
# CONFIG_RAETH_DVT is not set
CONFIG_RAETH_GMAC2=y
# CONFIG_RAETH_HW_LRO is not set
# CONFIG_RAETH_HW_VLAN_TX is not set
# CONFIG_RAETH_LRO is not set
# CONFIG_RAETH_NAPI is not set
CONFIG_RAETH_QDMA=y
CONFIG_RAETH_QDMATX_QDMARX=y
CONFIG_RAETH_SCATTER_GATHER_RX_DMA=y
# CONFIG_RAETH_SKB_RECYCLE_2K is not set
# CONFIG_RAETH_SPECIAL_TAG is not set
# CONFIG_RAETH_TSO is not set
CONFIG_RA_NAT_NONE=y
# CONFIG_RA_NETWORK_TASKLET_BH is not set
CONFIG_RA_NETWORK_WORKQUEUE_BH=y
# CONFIG_RCU_BOOST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_EXPEDITE_BOOT is not set
CONFIG_RCU_STALL_COMMON=y
CONFIG_RD_GZIP=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_ABX80X is not set
# CONFIG_RTC_DRV_CMOS is not set
CONFIG_RT_3052_ESW=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_SCHED_HRTICK=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_DMA is not set
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SLUB_CPU_PARTIAL=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MT65XX=y
CONFIG_SPMI=y
CONFIG_SRCU=y
CONFIG_STOP_MACHINE=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_SWCONFIG=y
CONFIG_SWIOTLB=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_USER_SPACE is not set
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
# CONFIG_THUMB2_KERNEL is not set
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_STATS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UID16=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_MT65XX_USB3_PHY=y
CONFIG_USB_PHY=y
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MTK=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USE_OF=y
# CONFIG_VDSO is not set
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_WAN_AT_P0=y
# CONFIG_WAN_AT_P4 is not set
CONFIG_WATCHDOG_CORE=y
# CONFIG_XEN is not set
CONFIG_XPS=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA_FLAG=0

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@ -92,7 +92,6 @@ CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
# CONFIG_CPU_THERMAL is not set
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
@ -297,10 +296,9 @@ CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_MT81xx_NOR=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_MTK=y
CONFIG_MTD_NAND_MTKSDG1=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=y
@ -454,11 +452,6 @@ CONFIG_SWCONFIG=y
CONFIG_SWIOTLB=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
# CONFIG_THUMB2_KERNEL is not set
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_STATS=y

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@ -1,7 +1,7 @@
From c30a296646a42302065ba452abe95b0b4b550883 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 27 Jul 2014 09:38:50 +0100
Subject: [PATCH 01/90] NET: multi phy support
Subject: [PATCH 01/91] NET: multi phy support
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 2c93328ed05061a50e3bd4111379dbcf6946d3ac Mon Sep 17 00:00:00 2001
From: James Liao <jamesjj.liao@mediatek.com>
Date: Wed, 30 Dec 2015 14:41:43 +0800
Subject: [PATCH 02/90] soc: mediatek: Separate scpsys driver common code
Subject: [PATCH 02/91] soc: mediatek: Separate scpsys driver common code
Separate scpsys driver common code to mtk-scpsys.c, and move MT8173
platform code to mtk-scpsys-mt8173.c.

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@ -1,7 +1,7 @@
From c359272f86805259c5801385d60fdeea9d629cf9 Mon Sep 17 00:00:00 2001
From: James Liao <jamesjj.liao@mediatek.com>
Date: Wed, 30 Dec 2015 14:41:44 +0800
Subject: [PATCH 03/90] soc: mediatek: Init MT8173 scpsys driver earlier
Subject: [PATCH 03/91] soc: mediatek: Init MT8173 scpsys driver earlier
Some power domain comsumers may init before module_init.
So the power domain provider (scpsys) need to be initialized

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@ -1,7 +1,7 @@
From f371844374fff273f817d6c43f679606417af59e Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Wed, 30 Dec 2015 14:41:45 +0800
Subject: [PATCH 04/90] soc: mediatek: Add MT2701 power dt-bindings
Subject: [PATCH 04/91] soc: mediatek: Add MT2701 power dt-bindings
Add power dt-bindings for MT2701.

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@ -1,7 +1,7 @@
From c6711565985f359d7d3c05f01f081e4c216902de Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Wed, 30 Dec 2015 14:41:46 +0800
Subject: [PATCH 05/90] soc: mediatek: Add MT2701/MT7623 scpsys driver
Subject: [PATCH 05/91] soc: mediatek: Add MT2701/MT7623 scpsys driver
Add scpsys driver for MT2701 and MT7623.

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@ -1,7 +1,7 @@
From 0c39bcd17fa6ce723f56ad3756b4bb36c4690342 Mon Sep 17 00:00:00 2001
From: James Liao <jamesjj.liao@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:17 +0800
Subject: [PATCH 06/90] clk: mediatek: Refine the makefile to support multiple
Subject: [PATCH 06/91] clk: mediatek: Refine the makefile to support multiple
clock drivers
Add a Kconfig to define clock configuration for each SoC, and

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@ -1,7 +1,7 @@
From d7e96f87f66c571e9f4171ecd89c656fbd2de89b Mon Sep 17 00:00:00 2001
From: James Liao <jamesjj.liao@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:18 +0800
Subject: [PATCH 07/90] dt-bindings: ARM: Mediatek: Document bindings for
Subject: [PATCH 07/91] dt-bindings: ARM: Mediatek: Document bindings for
MT2701
This patch adds the binding documentation for apmixedsys, bdpsys,

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@ -1,7 +1,7 @@
From 2fcbc15da2f13164e0851b9c7fae290249f0b44d Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:19 +0800
Subject: [PATCH 08/90] clk: mediatek: Add dt-bindings for MT2701 clocks
Subject: [PATCH 08/91] clk: mediatek: Add dt-bindings for MT2701 clocks
Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

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@ -1,7 +1,7 @@
From f2c07eaa2df52f9acac9ffc3457d3d81079dd723 Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:20 +0800
Subject: [PATCH 09/90] clk: mediatek: Add MT2701 clock support
Subject: [PATCH 09/91] clk: mediatek: Add MT2701 clock support
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

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@ -1,7 +1,7 @@
From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:21 +0800
Subject: [PATCH 10/90] reset: mediatek: mt2701 reset controller dt-binding
Subject: [PATCH 10/91] reset: mediatek: mt2701 reset controller dt-binding
file
Dt-binding file about reset controller is used to provide

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@ -1,7 +1,7 @@
From b86d3303db25a8296e4c3de46ee1470f60f71b0c Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:22 +0800
Subject: [PATCH 11/90] reset: mediatek: mt2701 reset driver
Subject: [PATCH 11/91] reset: mediatek: mt2701 reset driver
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are

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@ -1,7 +1,7 @@
From 3b5df542d52b13a1b20d25311fa4c4029a3b83af Mon Sep 17 00:00:00 2001
From: Erin Lo <erin.lo@mediatek.com>
Date: Mon, 28 Dec 2015 15:09:02 +0800
Subject: [PATCH 12/90] ARM: mediatek: Add MT2701 config options for mediatek
Subject: [PATCH 12/91] ARM: mediatek: Add MT2701 config options for mediatek
SoCs.
The upcoming MTK pinctrl driver have a big pin table for each SoC

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@ -1,7 +1,7 @@
From 1a254735cad9db5c8605c972b0f16b3929dc0d6e Mon Sep 17 00:00:00 2001
From: Biao Huang <biao.huang@mediatek.com>
Date: Mon, 28 Dec 2015 15:09:03 +0800
Subject: [PATCH 13/90] dt-bindings: mediatek: Modify pinctrl bindings for
Subject: [PATCH 13/91] dt-bindings: mediatek: Modify pinctrl bindings for
mt2701
Signed-off-by: Biao Huang <biao.huang@mediatek.com>

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@ -1,7 +1,7 @@
From 416720ba33d4fd7d3166c17be7c13651cc08d408 Mon Sep 17 00:00:00 2001
From: Biao Huang <biao.huang@mediatek.com>
Date: Mon, 28 Dec 2015 15:09:04 +0800
Subject: [PATCH 14/90] pinctrl: dt bindings: Add pinfunc header file for
Subject: [PATCH 14/91] pinctrl: dt bindings: Add pinfunc header file for
mt2701
Add pinfunc header file, mt2701 related dts will include it

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@ -1,7 +1,7 @@
From ddc72b659b3642d0496dee4e1ee39416ca008053 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Jan 2016 23:42:06 +0100
Subject: [PATCH 15/90] dt-bindings: mediatek: Modify pinctrl bindings for
Subject: [PATCH 15/91] dt-bindings: mediatek: Modify pinctrl bindings for
mt7623
Signed-off-by: John Crispin <blogic@openwrt.org>

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@ -1,7 +1,7 @@
From 1255eaacd6cc9d1fa6bb33185380efed22008baf Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 27 Jun 2015 13:13:05 +0200
Subject: [PATCH 16/90] pinctrl: dt bindings: Add pinctrl file for mt7623
Subject: [PATCH 16/91] pinctrl: dt bindings: Add pinctrl file for mt7623
Add the driver and header files required to make pinctrl work on MediaTek
MT7623.

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@ -1,7 +1,7 @@
From 294cf90337d70ad74edf147180bbeef837298bd0 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 6 Jan 2016 20:06:49 +0100
Subject: [PATCH 17/90] clk: add hifsys reset
Subject: [PATCH 17/91] clk: add hifsys reset
Hi,

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@ -1,7 +1,7 @@
From 84d37aeef94deae3ce87e677f6016a5d980429e8 Mon Sep 17 00:00:00 2001
From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
Date: Tue, 17 Nov 2015 17:18:39 +0800
Subject: [PATCH 18/90] dt-bindings: Add a binding for Mediatek xHCI host
Subject: [PATCH 18/91] dt-bindings: Add a binding for Mediatek xHCI host
controller
add a DT binding documentation of xHCI host controller for the

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@ -1,7 +1,7 @@
From 651d8fff94718c7e48b8a40d7774878eb8ed62ee Mon Sep 17 00:00:00 2001
From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
Date: Tue, 17 Nov 2015 17:18:40 +0800
Subject: [PATCH 19/90] xhci: mediatek: support MTK xHCI host controller
Subject: [PATCH 19/91] xhci: mediatek: support MTK xHCI host controller
There some vendor quirks for MTK xhci host controller:
1. It defines some extra SW scheduling parameters for HW

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@ -1,7 +1,7 @@
From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
Date: Tue, 17 Nov 2015 17:18:41 +0800
Subject: [PATCH 20/90] arm64: dts: mediatek: add xHCI & usb phy for mt8173
Subject: [PATCH 20/91] arm64: dts: mediatek: add xHCI & usb phy for mt8173
add xHCI and phy drivers for MT8173-EVB

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@ -1,7 +1,7 @@
From 162deec293400cb132161606629654acaec7cb4b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 5 Jan 2016 12:13:54 +0100
Subject: [PATCH 21/90] Document: DT: Add bindings for mediatek MT7623 SoC
Subject: [PATCH 21/91] Document: DT: Add bindings for mediatek MT7623 SoC
Platform
This adds a DT binding documentation for the MT7623 SoC from Mediatek.

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@ -1,7 +1,7 @@
From fa5d94d6b4b314f751b1c32bb5a87a80b866d05e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 5 Jan 2016 16:52:31 +0100
Subject: [PATCH 22/90] soc: mediatek: add compat string for mt7623 to scpsys
Subject: [PATCH 22/91] soc: mediatek: add compat string for mt7623 to scpsys
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,18 +1,18 @@
From 5536a546755527a862cb2494814c5244d3d8e30a Mon Sep 17 00:00:00 2001
From 83ef9fb21a896ac03c3a78bc3ae0b21f3b0a43a3 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 5 Jan 2016 12:16:17 +0100
Subject: [PATCH 23/90] ARM: dts: mediatek: add MT7623 basic support
Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
This adds basic chip support for Mediatek MT7623.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/mt7623-evb.dts | 474 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7623.dtsi | 583 +++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7623-evb.dts | 474 +++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7623.dtsi | 593 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 4 +
arch/arm/mach-mediatek/mediatek.c | 1 +
5 files changed, 1063 insertions(+)
5 files changed, 1073 insertions(+)
create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
create mode 100644 arch/arm/boot/dts/mt7623.dtsi
@ -510,10 +510,10 @@ index 0000000..70b92a4
+};
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
new file mode 100644
index 0000000..0536b2c
index 0000000..80c1ab8
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -0,0 +1,583 @@
@@ -0,0 +1,593 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic@openwrt.org>
@ -850,15 +850,25 @@ index 0000000..0536b2c
+ status = "disabled";
+ };
+
+ nand: nfi@1100d000 {
+ nandc: nfi@1100d000 {
+ compatible = "mediatek,mt2701-nfc";
+ reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI>,
+ <&pericfg CLK_PERI_NFI_PAD>;
+ clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
+ // nand-on-flash-bbt;
+ clock-names = "nfi_clk", "pad_clk";
+ status = "disabled";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ bch: ecc@1100e000 {
+ compatible = "mediatek,mt2701-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+

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@ -1,7 +1,7 @@
From 0afae16fffe2cf547fad21279c120bedf19e9b8e Mon Sep 17 00:00:00 2001
From 427a938858630fe4cec1b3829624676a4106d236 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 6 Jan 2016 21:55:10 +0100
Subject: [PATCH 24/90] dt-bindings: add MediaTek PCIe binding documentation
Subject: [PATCH 24/91] dt-bindings: add MediaTek PCIe binding documentation
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 4e9a4574e833ee42d646de2dc3b0cb912360e6c5 Mon Sep 17 00:00:00 2001
From 5571cc63036daf0e0a05f07b0137fee86d58acb0 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 5 Jan 2016 20:20:04 +0100
Subject: [PATCH 25/90] PCI: mediatek: add support for PCIe found on
Subject: [PATCH 25/91] PCI: mediatek: add support for PCIe found on
MT7623/MT2701
Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports

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@ -1,7 +1,7 @@
From e56caadcf189eafcd2c7a9e22f22c0b67e89df75 Mon Sep 17 00:00:00 2001
From a366216a08408949eca2d7823273da6826d3c483 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 21 Feb 2016 13:52:12 +0100
Subject: [PATCH 26/90] scpsys: various fixes
Subject: [PATCH 26/91] scpsys: various fixes
---
drivers/clk/mediatek/clk-mt2701.c | 2 ++

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@ -1,7 +1,7 @@
From 036862011a5d13e8c54d9d0f9fe838fea986df89 Mon Sep 17 00:00:00 2001
From 4d02177361d13355d98a38830c69bb9add3c109c Mon Sep 17 00:00:00 2001
From: Henry Chen <henryc.chen@mediatek.com>
Date: Mon, 4 Jan 2016 20:02:52 +0800
Subject: [PATCH 27/90] soc: mediatek: PMIC wrap: Clear the vldclr if state
Subject: [PATCH 27/91] soc: mediatek: PMIC wrap: Clear the vldclr if state
machine stay on FSM_VLDCLR state.
Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout,

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@ -1,7 +1,7 @@
From a7b6aff661303f2c67e3f8d03b152fd6a0a19ac2 Mon Sep 17 00:00:00 2001
From e4a5c39f75a11ecb78d1243b19b929af54f888fa Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 5 Jan 2016 17:24:28 +0100
Subject: [PATCH 28/90] ARM: mediatek: add MT7623 smp bringup code
Subject: [PATCH 28/91] ARM: mediatek: add MT7623 smp bringup code
Add support for booting secondary CPUs on MT7623.

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@ -1,7 +1,7 @@
From 4fbf092b199a344abe60528732c712ec3b22aa67 Mon Sep 17 00:00:00 2001
From b4a6293df00036129d26a7f06bfb220ba5a73c42 Mon Sep 17 00:00:00 2001
From: Henry Chen <henryc.chen@mediatek.com>
Date: Thu, 21 Jan 2016 19:04:00 +0800
Subject: [PATCH 29/90] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
Subject: [PATCH 29/91] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
WDT_SRC_EN
Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout

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@ -1,7 +1,7 @@
From 4203a164bbf1785b649bc8d7a94ede53a33ad92a Mon Sep 17 00:00:00 2001
From 0befbd007b72ba2b14c65558d3bb72ea885496f6 Mon Sep 17 00:00:00 2001
From: Louis Yu <louis.yu@mediatek.com>
Date: Thu, 7 Jan 2016 20:09:43 +0800
Subject: [PATCH 30/90] ARM: mediatek: add mt2701 smp bringup code
Subject: [PATCH 30/91] ARM: mediatek: add mt2701 smp bringup code
Add support for booting secondary CPUs on mt2701.

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@ -1,7 +1,7 @@
From 55308931b04c0353fd1f3367fb018af5bb643a9a Mon Sep 17 00:00:00 2001
From 9367fb14e1be8dd174f8d63ec83f7ee2d90ae733 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 13:12:19 +0100
Subject: [PATCH 31/90] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
Subject: [PATCH 31/91] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
the PMIC wrapper doc
Signed-off-by: John Crispin <blogic@openwrt.org>

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@ -1,7 +1,7 @@
From e2b8f38b1a794b7a0912d0bbaa1454055b5cbac2 Mon Sep 17 00:00:00 2001
From 7b7d59b4219c30e1b9601300348f1431fdab7081 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 06:42:01 +0100
Subject: [PATCH 32/90] soc: mediatek: PMIC wrap: don't duplicate the wrapper
Subject: [PATCH 32/91] soc: mediatek: PMIC wrap: don't duplicate the wrapper
data
As we add support for more devices struct pmic_wrapper_type will grow and

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@ -1,7 +1,7 @@
From 4265837216132e2b1c04b23e77281c1a4feb6ca8 Mon Sep 17 00:00:00 2001
From 35d879d80437cc6ed811538903e115dbcda777ac Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 05:27:17 +0100
Subject: [PATCH 33/90] soc: mediatek: PMIC wrap: add wrapper callbacks for
Subject: [PATCH 33/91] soc: mediatek: PMIC wrap: add wrapper callbacks for
init_reg_clock
Split init_reg_clock up into SoC specific callbacks. The patch also

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@ -1,7 +1,7 @@
From b164dff8be266b531574e89a27eb3ce9e0b4e40a Mon Sep 17 00:00:00 2001
From d82889cec95358b917fcf29fc3214980deb138b9 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 10:12:00 +0100
Subject: [PATCH 34/90] soc: mediatek: PMIC wrap: split SoC specific init into
Subject: [PATCH 34/91] soc: mediatek: PMIC wrap: split SoC specific init into
callback
This patch moves the SoC specific wrapper init code into separate callback

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@ -1,7 +1,7 @@
From 7046dc2a485b2b2ec993d7c933820c8ae2b45718 Mon Sep 17 00:00:00 2001
From 613acba0068461948e6b5283df03d7c1e1583a40 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 10:14:39 +0100
Subject: [PATCH 35/90] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
Subject: [PATCH 35/91] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
different bitmask for MT2701/7623
MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN.

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@ -1,7 +1,7 @@
From 506b811d75ec94b10eda673f8677ef507f870077 Mon Sep 17 00:00:00 2001
From 1186088ab86b7286e1920dcbfbbbf2627a0daeda Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 10:21:42 +0100
Subject: [PATCH 36/90] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
Subject: [PATCH 36/91] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
bitmask for MT2701/7623
Different SoCs will use different bitmask for the SPI_WRITE command. This

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@ -1,7 +1,7 @@
From df7e52743b8159b2cc58fce14841135de84ec81a Mon Sep 17 00:00:00 2001
From 95f72db32afd545b88eaa04802736f1f84242a9f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 10:48:35 +0100
Subject: [PATCH 37/90] soc: mediatek: PMIC wrap: move wdt_src into the
Subject: [PATCH 37/91] soc: mediatek: PMIC wrap: move wdt_src into the
pmic_wrapper_type struct
Different SoCs will use different bitmask for the wdt_src. This patch

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@ -1,7 +1,7 @@
From e16393b2c78cc95ec124a46e8da8cfb2af333f00 Mon Sep 17 00:00:00 2001
From bb19fd13b1ed629873ea144b22c4764aa4baa5ef Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 10:54:18 +0100
Subject: [PATCH 38/90] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
Subject: [PATCH 38/91] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
pwrap_is_mt8173()
With more SoCs being added the list of helper functions like these would

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@ -1,7 +1,7 @@
From 6dc9d9e08025ebc758981ea0396a41f95f669715 Mon Sep 17 00:00:00 2001
From daa4d054bb0557799c8b324d7aa5f0a3a4a7b078 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 09:55:08 +0100
Subject: [PATCH 39/90] soc: mediatek: PMIC wrap: add a slave specific struct
Subject: [PATCH 39/91] soc: mediatek: PMIC wrap: add a slave specific struct
This patch adds a new struct pwrap_slv_type that we use to store the slave
specific data. The patch adds 2 new helper functions to access the dew

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@ -1,7 +1,7 @@
From 2ff8338c16c86856fc6e3f636cf0df9a2562bc95 Mon Sep 17 00:00:00 2001
From 15143b59a26a06e890e2ba3c9944b3f751ce39bd Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 11:40:43 +0100
Subject: [PATCH 40/90] soc: mediatek: PMIC wrap: add mt6323 slave support
Subject: [PATCH 40/91] soc: mediatek: PMIC wrap: add mt6323 slave support
Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623
EVB. The only function that we need to touch is pwrap_init_cipher().

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@ -1,7 +1,7 @@
From ec6ad56b62c6cd769b5a35e7009518d99bbbb7b6 Mon Sep 17 00:00:00 2001
From 2f5df30a7b913069c8fce22dc702e0d7c76ef361 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Jan 2016 12:09:14 +0100
Subject: [PATCH 41/90] soc: mediatek: PMIC wrap: add MT2701/7623 support
Subject: [PATCH 41/91] soc: mediatek: PMIC wrap: add MT2701/7623 support
Add the registers, callbacks and data structures required to make the
wrapper work on MT2701 and MT7623.

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@ -1,7 +1,7 @@
From 51deb5b355f0a26cc5f2a5e4a83e904f5c4c34df Mon Sep 17 00:00:00 2001
From edc6e6a2f10f7b7fc94dc6147c86520e5a439d16 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 10 Jan 2016 17:12:37 +0100
Subject: [PATCH 42/90] dt-bindings: mfd: Add bindings for the MediaTek MT6323
Subject: [PATCH 42/91] dt-bindings: mfd: Add bindings for the MediaTek MT6323
PMIC
Signed-off-by: John Crispin <blogic@openwrt.org>

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@ -1,7 +1,7 @@
From 3989b27c0a7cc16d29de14e1cb509b8ee82f7449 Mon Sep 17 00:00:00 2001
From f97549172878651725a719a4fc4b610613fe5843 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 8 Jan 2016 08:33:17 +0100
Subject: [PATCH 43/90] mfd: mt6397: int_con and int_status may vary in
Subject: [PATCH 43/91] mfd: mt6397: int_con and int_status may vary in
location
MT6323 has the INT_CON and INT_STATUS located at a different position.

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@ -1,7 +1,7 @@
From bd51286bc2a310bc1ba2297e97e862bbdb102183 Mon Sep 17 00:00:00 2001
From 5fbdf1ebc267561781ce812793cd35e63fa39614 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 8 Jan 2016 08:41:52 +0100
Subject: [PATCH 44/90] mfd: mt6397: add support for different Slave types
Subject: [PATCH 44/91] mfd: mt6397: add support for different Slave types
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 52dde352cc7a558eab85458c3f7ab90dc652f761 Mon Sep 17 00:00:00 2001
From 2a1c7879d8c3eac4313abc011adbefbc50fd5f92 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 8 Jan 2016 04:09:43 +0100
Subject: [PATCH 45/90] mfd: mt6397: add MT6323 support to MT6397 driver
Subject: [PATCH 45/91] mfd: mt6397: add MT6323 support to MT6397 driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 8113b9e7b599162ae4abf6bc940210ce2f826099 Mon Sep 17 00:00:00 2001
From 34177561c62ed881c862f9ece652ca1ca5994796 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 10 Jan 2016 17:31:46 +0100
Subject: [PATCH 46/90] regulator: Add document for MT6323 regulator
Subject: [PATCH 46/91] regulator: Add document for MT6323 regulator
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: devicetree@vger.kernel.org

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@ -1,7 +1,7 @@
From 257b7279661d1d6fca41e053bcfb4368b238f049 Mon Sep 17 00:00:00 2001
From 2a33aa927dece6ac6d10caff48897c8ac6a66c1b Mon Sep 17 00:00:00 2001
From: Chen Zhong <chen.zhong@mediatek.com>
Date: Fri, 8 Jan 2016 04:17:37 +0100
Subject: [PATCH 47/90] regulator: mt6323: Add support for MT6323 regulator
Subject: [PATCH 47/91] regulator: mt6323: Add support for MT6323 regulator
The MT6323 is a regulator found on boards based on MediaTek MT7623 and
probably other SoCs. It is a so called pmic and connects as a slave to

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@ -1,7 +1,7 @@
From 1e759a179923236660f7f2070fd52e9d2cc09b22 Mon Sep 17 00:00:00 2001
From caa2186644606dad07a603905ebabb8068828ebf Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 2 Mar 2016 07:18:52 +0100
Subject: [PATCH 48/90] net-next: mediatek: document MediaTek SoC ethernet
Subject: [PATCH 48/91] net-next: mediatek: document MediaTek SoC ethernet
binding
This adds the binding documentation for the MediaTek Ethernet

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@ -1,7 +1,7 @@
From 15f1cb9603c22910f1cd6a8c63fd279a6d5acfd4 Mon Sep 17 00:00:00 2001
From 412449bacdb46b548fd08af19148019e2e979294 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 2 Mar 2016 04:27:10 +0100
Subject: [PATCH 49/90] net-next: mediatek: add support for MT7623 ethernet
Subject: [PATCH 49/91] net-next: mediatek: add support for MT7623 ethernet
Add ethernet support for MediaTek SoCs from the MT7623 family. These have
dual GMAC. Depending on the exact version, there might be a built-in

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@ -1,7 +1,7 @@
From 80d88cdd398bf0c33ca5e655ded3bb62339b9565 Mon Sep 17 00:00:00 2001
From 8bc8e78ddec2c93d7fe3487dfdfeedd382e3b96f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 2 Mar 2016 04:32:43 +0100
Subject: [PATCH 50/90] net-next: mediatek: add Kconfig and Makefile
Subject: [PATCH 50/91] net-next: mediatek: add Kconfig and Makefile
This patch adds the Makefile and Kconfig required to make the driver build.

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@ -1,7 +1,7 @@
From 859c0e3dfcc227b6f3fd324ef2ea5fa22cfc7f17 Mon Sep 17 00:00:00 2001
From d9b93fb0d4021694a2b7e47981cd9de67e83aa05 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 2 Mar 2016 04:34:04 +0100
Subject: [PATCH 51/90] net-next: mediatek: add an entry to MAINTAINERS
Subject: [PATCH 51/91] net-next: mediatek: add an entry to MAINTAINERS
Add myself and Felix as the Maintainers for the MediaTek ethernet driver.

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@ -1,7 +1,7 @@
From 3126b17c9123daf9f96f513d53f08c06f4d08a7c Mon Sep 17 00:00:00 2001
From 69a0df9dd942799651a7ec06b3cfe7fc43b2e32a Mon Sep 17 00:00:00 2001
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
Date: Mon, 16 Nov 2015 14:37:35 +0100
Subject: [PATCH 52/90] mtd: nand: add an mtd_to_nand() helper
Subject: [PATCH 52/91] mtd: nand: add an mtd_to_nand() helper
Some drivers are retrieving the nand_chip pointer using the container_of
macro on a struct wrapping both the nand_chip and the mtd_info struct while

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@ -1,7 +1,7 @@
From 5175e1d27c52c0958b2d1cb4391a611444aaf432 Mon Sep 17 00:00:00 2001
From 833645b92150d74642829c24c0ca1fbbdeccfb5c Mon Sep 17 00:00:00 2001
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
Date: Tue, 1 Dec 2015 12:03:07 +0100
Subject: [PATCH 53/90] mtd: nand: add nand_to_mtd() helper
Subject: [PATCH 53/91] mtd: nand: add nand_to_mtd() helper
Add a new helper to retrieve the MTD device attached to a NAND chip.

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@ -1,7 +1,7 @@
From ad8a96526816abfa75b19998bbf41857f9bae6cc Mon Sep 17 00:00:00 2001
From af8437ee10a6304da30ca479480102b464b39c82 Mon Sep 17 00:00:00 2001
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
Date: Thu, 10 Dec 2015 09:00:39 +0100
Subject: [PATCH 54/90] mtd: nand: add helpers to access ->priv
Subject: [PATCH 54/91] mtd: nand: add helpers to access ->priv
Add two helpers to access the field reserved for private controller data.
This makes it clearer what this field is reserved for and ease future

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@ -1,7 +1,7 @@
From addd0678f84712ac6f70b8e6cda84e11c5d348f4 Mon Sep 17 00:00:00 2001
From f18fcf4468ffdce17747f3d331f998a7e9264142 Mon Sep 17 00:00:00 2001
From: Boris BREZILLON <boris.brezillon@free-electrons.com>
Date: Tue, 1 Dec 2015 12:03:06 +0100
Subject: [PATCH 55/90] mtd: nand: embed an mtd_info structure into nand_chip
Subject: [PATCH 55/91] mtd: nand: embed an mtd_info structure into nand_chip
Currently all NAND controller drivers are providing both the mtd_info and
nand_chip struct and then let the NAND subsystem to initialize a few

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@ -1,7 +1,7 @@
From 6b4858de63badb90d820a1d343528d8575f3f28c Mon Sep 17 00:00:00 2001
From 59d8570d4b61af8544fc295d5e83ab7c28294bb8 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 22 Mar 2016 03:52:07 +0100
Subject: [PATCH 56/90] mtd: add get/set of_node/flash_node helpers
Subject: [PATCH 56/91] mtd: add get/set of_node/flash_node helpers
We are going to begin using the mtd->dev.of_node field for MTD device
nodes, so let's add helpers for it. Also, we'll be making some

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@ -1,7 +1,7 @@
From 47589c3a100ae3dd0081866fd60ef31a67ba7fa9 Mon Sep 17 00:00:00 2001
From 0fe612b501f1d56d76b2858d2ae779c1e766d064 Mon Sep 17 00:00:00 2001
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Date: Wed, 2 Mar 2016 12:00:11 -0500
Subject: [PATCH 57/90] mtd: mediatek: device tree docs for MTK Smart Device
Subject: [PATCH 57/91] mtd: mediatek: device tree docs for MTK Smart Device
Gen1 NAND
This patch adds documentation support for Smart Device Gen1 type of

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@ -1,7 +1,7 @@
From a97e38f34b59d18d9ca3626c2611c63cc6c6b48a Mon Sep 17 00:00:00 2001
From 24db36ad20239841b897efb41442841ebf5d2f78 Mon Sep 17 00:00:00 2001
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Date: Wed, 2 Mar 2016 12:00:12 -0500
Subject: [PATCH 58/90] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
Subject: [PATCH 58/91] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
This patch adds support for mediatek's SDG1 NFC nand controller
embedded in SoC 2701.

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@ -1,7 +1,7 @@
From bb79410956e03e7c775c38338c5826f8591378a9 Mon Sep 17 00:00:00 2001
From 96bddff914c0cee1b16d809220e84b470b433122 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 31 Mar 2016 02:28:08 +0200
Subject: [PATCH 59/90] mtd: nand: backport fixes
Subject: [PATCH 59/91] mtd: nand: backport fixes
---
drivers/mtd/nand/mtksdg1_nand.c | 9 ++++++++-

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@ -1,7 +1,7 @@
From e31a6402c10f50bf45fd073fbfd622f16bfca031 Mon Sep 17 00:00:00 2001
From cbcbd319d905cdcf4a71003b5634137fee03855b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Apr 2016 07:18:35 +0200
Subject: [PATCH 60/90] clk: dont disable unused clocks
Subject: [PATCH 60/91] clk: dont disable unused clocks
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 8304c8eb6b43d29fd5794bece27faaa7b7a59a2b Mon Sep 17 00:00:00 2001
From 6610fdbea393a4a8ed956b2aaf7012bea3a5069e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 31 Mar 2016 06:46:51 +0200
Subject: [PATCH 61/90] clk: mediatek: enable critical clocks
Subject: [PATCH 61/91] clk: mediatek: enable critical clocks
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From c906caf00335b78ae1275eea4bfceca5273f3154 Mon Sep 17 00:00:00 2001
From 2ed6efcef399d15910ff60eef72b4cf8e5265c47 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 31 Mar 2016 02:26:37 +0200
Subject: [PATCH 62/90] clk: mediatek: Export CPU mux clocks for CPU frequency
Subject: [PATCH 62/91] clk: mediatek: Export CPU mux clocks for CPU frequency
control
This patch adds CPU mux clocks which are used by Mediatek cpufreq driver

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@ -1,7 +1,7 @@
From a430fa942b3ff0e51f472e53110b7f6b16290295 Mon Sep 17 00:00:00 2001
From 668d2c777a41440daa55435c2a217e61c23e4a30 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 30 Mar 2016 23:48:53 +0200
Subject: [PATCH 63/90] cpufreq: mediatek: add driver
Subject: [PATCH 63/91] cpufreq: mediatek: add driver
Signed-off-by: John Crispin <john@phrozen.org>
---

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@ -1,7 +1,7 @@
From cf070892e774e76e1bd969020d8e7f31af1d2e3d Mon Sep 17 00:00:00 2001
From 6eeadfb48dc5e73dae115fc0be9416e3d5fed84d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 31 Mar 2016 06:07:01 +0200
Subject: [PATCH 64/90] arm: mediatek: make a7 timer work Signed-off-by: John
Subject: [PATCH 64/91] arm: mediatek: make a7 timer work Signed-off-by: John
Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 56b33ebf188a59d8307c3b748eccf8cda1062981 Mon Sep 17 00:00:00 2001
From 0b88e5873b97ab20566b51134123fda7050d4d08 Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Tue, 15 Mar 2016 10:18:49 +0300
Subject: [PATCH 65/90] net: mediatek: checking for IS_ERR() instead of NULL
Subject: [PATCH 65/91] net: mediatek: checking for IS_ERR() instead of NULL
of_phy_connect() returns NULL on error, it never returns error pointers.

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@ -1,7 +1,7 @@
From 223a164816ee104df9fbd01c0c52587bd8d7d758 Mon Sep 17 00:00:00 2001
From 489994e9cb0d9f762c31e2af9205188ae8f3b013 Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@oracle.com>
Date: Tue, 15 Mar 2016 10:19:04 +0300
Subject: [PATCH 66/90] net: mediatek: unlock on error in mtk_tx_map()
Subject: [PATCH 66/91] net: mediatek: unlock on error in mtk_tx_map()
There was a missing unlock on the error path.

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@ -1,7 +1,7 @@
From d57c2d08cdceba377a35f69ceb807ae58f4bdbb2 Mon Sep 17 00:00:00 2001
From ac345476b98f3856bbf3938e114d4be799f8bd69 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 14 Mar 2016 15:07:10 +0100
Subject: [PATCH 67/90] net: mediatek: use dma_addr_t correctly
Subject: [PATCH 67/91] net: mediatek: use dma_addr_t correctly
dma_alloc_coherent() expects a dma_addr_t pointer as its argument,
not an 'unsigned int', and gcc correctly warns about broken

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@ -1,7 +1,7 @@
From 6cf7d8453b9ef0a1e51144969141a92dade6b540 Mon Sep 17 00:00:00 2001
From 8b6bb80616460eda2e70e358c5fb70c0f4d4d02f Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 14 Mar 2016 15:07:11 +0100
Subject: [PATCH 68/90] net: mediatek: remove incorrect dma_mask assignment
Subject: [PATCH 68/91] net: mediatek: remove incorrect dma_mask assignment
Device drivers should not mess with the DMA mask directly,
but instead call dma_set_mask() etc if needed.

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@ -1,7 +1,7 @@
From 592d94e0e580341fdcce975a97bebb90e71b38fc Mon Sep 17 00:00:00 2001
From cd7ea7dae994beea798115f4c34c96f45cc028d1 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 14 Mar 2016 15:07:12 +0100
Subject: [PATCH 69/90] net: mediatek: check device_reset return code
Subject: [PATCH 69/91] net: mediatek: check device_reset return code
The device_reset() function may fail, so we have to check
its return value, e.g. to make deferred probing work correctly.

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@ -1,7 +1,7 @@
From d59c125296df424b8e7c5c4900e1b8084b6dd3ba Mon Sep 17 00:00:00 2001
From 5fac03871435c52f7f9b7f34aefb2774089d32f9 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 30 Mar 2016 03:18:17 +0200
Subject: [PATCH 70/90] net: mediatek: watchdog_timeo was not set
Subject: [PATCH 70/91] net: mediatek: watchdog_timeo was not set
The original commit failed to set watchdog_timeo. This patch sets
watchdog_timeo to HZ.

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@ -1,7 +1,7 @@
From b6f1b24448de1d294f9668b14bf02391ff6bef5c Mon Sep 17 00:00:00 2001
From ca0d5851de3763fe309d3083693f1a438c6e98c9 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 22 Mar 2016 04:42:27 +0100
Subject: [PATCH 71/90] net: mediatek: mtk_cal_txd_req() returns bad value
Subject: [PATCH 71/91] net: mediatek: mtk_cal_txd_req() returns bad value
The code used to also support the PDMA engine, which had 2 packet pointers
per descriptor. Because of this we have to divide the result by 2 and round

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@ -1,7 +1,7 @@
From dd061dc7eacb22853981978fa94205292444fa49 Mon Sep 17 00:00:00 2001
From 51dc0a2114c3d6e51bf2acde415fccdec031e480 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 25 Mar 2016 04:24:27 +0100
Subject: [PATCH 72/90] net: mediatek: remove superflous reset call
Subject: [PATCH 72/91] net: mediatek: remove superflous reset call
HW reset is triggered int he mtk_hw_init() function. There is no need to
reset the core during probe.

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@ -1,7 +1,7 @@
From 283001c04f395f32e55345632d8129f5395cde33 Mon Sep 17 00:00:00 2001
From 868eb5a3d0217e1ecdc2f628c6dc4fcd18562a71 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 29 Mar 2016 16:41:07 +0200
Subject: [PATCH 73/90] net: mediatek: fix stop and wakeup of queue
Subject: [PATCH 73/91] net: mediatek: fix stop and wakeup of queue
The driver supports 2 MACs. Both run on the same DMA ring. If we go
above/below the TX rings thershold value, we always need to wake/stop

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@ -1,7 +1,7 @@
From 46e02ea6c0468ce01b6e370a20f01a7f7311af34 Mon Sep 17 00:00:00 2001
From 300ca8c6b5dcee2593f22d5bf8f13bb4da8c19c5 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 29 Mar 2016 17:00:47 +0200
Subject: [PATCH 74/90] net: mediatek: fix mtk_pending_work
Subject: [PATCH 74/91] net: mediatek: fix mtk_pending_work
The driver supports 2 MACs. Both run on the same DMA ring. If we hit a TX
timeout we need to stop both netdevs before retarting them again. If we

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@ -1,7 +1,7 @@
From 25e46afc7324196c89dfb6f83a9c518942e23b33 Mon Sep 17 00:00:00 2001
From 506c56fe0c3986c13fbca474ee91b061fbc850ca Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 29 Mar 2016 17:20:01 +0200
Subject: [PATCH 75/90] net: mediatek: fix TX locking
Subject: [PATCH 75/91] net: mediatek: fix TX locking
Inside the TX path there is a lock inside the tx_map function. This is
however too late. The patch moves the lock to the start of the xmit

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@ -1,7 +1,7 @@
From 8830adaea03aafc1e35f739e436dc36af7c54428 Mon Sep 17 00:00:00 2001
From d42de6ec9325c29d0f59c5df74a5cbceb00ddd9d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 29 Mar 2016 17:24:24 +0200
Subject: [PATCH 76/90] net: mediatek: move the pending_work struct to the
Subject: [PATCH 76/91] net: mediatek: move the pending_work struct to the
device generic struct
The worker always touches both netdevs. It is ethernet core and not MAC

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@ -1,7 +1,7 @@
From 6a6f264e82649f8d9933271f2e9b08af94daad50 Mon Sep 17 00:00:00 2001
From 2675e2a40d78c55fc2d578ec71cc990170cacc42 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Apr 2016 17:36:23 +0200
Subject: [PATCH 77/90] net: mediatek: do not set the QID field in the TX DMA
Subject: [PATCH 77/91] net: mediatek: do not set the QID field in the TX DMA
descriptors
The QID field gets set to the mac id. This made the DMA linked list queue

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@ -1,7 +1,7 @@
From 9dd4e96d415d1e1910ec42058729380cddb22f9d Mon Sep 17 00:00:00 2001
From 289e6b23aa394126f50048f673ac266686bbf65e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 29 Mar 2016 14:32:07 +0200
Subject: [PATCH 78/90] net: mediatek: update the IRQ part of the binding
Subject: [PATCH 78/91] net: mediatek: update the IRQ part of the binding
document
The current binding document only describes a single interrupt. Update the

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@ -1,7 +1,7 @@
From d449af97701c1da5b373df5a7675b93b9a2067bf Mon Sep 17 00:00:00 2001
From f26f228f312fafc090d21036b682bd1062bb731f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 23 Apr 2016 11:57:21 +0200
Subject: [PATCH 79/90] net-next: mediatek: fix BQL support
Subject: [PATCH 79/91] net-next: mediatek: fix BQL support
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 121287dee1454be0ebc0e5b8c7b5b85e16570551 Mon Sep 17 00:00:00 2001
From 6918f290a9019425043dbedf7b39bc82a69e23a6 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 22 Apr 2016 11:05:23 +0200
Subject: [PATCH 80/90] net-next: mediatek: fix gigabit and flow control
Subject: [PATCH 80/91] net-next: mediatek: fix gigabit and flow control
advertisement
The current code will not setup the PHYs advertisement features correctly.

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@ -1,7 +1,7 @@
From dbf02af61ecac8b8a2d651128379e54244f0c68a Mon Sep 17 00:00:00 2001
From b5ecc24a027dea24f3ff798f87f65dd42015b342 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 22 Apr 2016 11:06:03 +0200
Subject: [PATCH 81/90] net-next: mediatek: add fixed-phy support
Subject: [PATCH 81/91] net-next: mediatek: add fixed-phy support
The MT7623 SoC has a builtin gigabit switch. If we want to use it, GMAC1
needs to be configured using a fixed link speed and flow control settings.

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@ -1,7 +1,7 @@
From 3f7e90b7acf147dbbe6bb140c510fc1eb97279ef Mon Sep 17 00:00:00 2001
From bbd92ed51c48a4586f149767841a5495cbc5a979 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 22 Apr 2016 11:08:43 +0200
Subject: [PATCH 82/90] net-next: mediatek: add RX delay support
Subject: [PATCH 82/91] net-next: mediatek: add RX delay support
If an external Gigabit PHY is connected to either of the MACs we need to
tell the to use a RX delay. Not doing so will result in heavy packet loss

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@ -1,7 +1,7 @@
From 436659829b38d5babc2d590676f5b74bfc17568a Mon Sep 17 00:00:00 2001
From d20b45f50d6b3352aa7be76eb7a28cffcfe379da Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 23 Apr 2016 09:06:05 +0200
Subject: [PATCH 83/90] net-next: mediatek: add missing return code check
Subject: [PATCH 83/91] net-next: mediatek: add missing return code check
The code fails to check if the scratch memory was properly allocated. Add
this check and return with an error if the allocation failed.

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@ -1,7 +1,7 @@
From 77c5d1b00214c9e42b9bd5f0f7fc0ec14807d117 Mon Sep 17 00:00:00 2001
From 2d22628561299e1c7d71e16262131127de3c4216 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 23 Apr 2016 09:18:28 +0200
Subject: [PATCH 84/90] net-next: mediatek: fix missing free of scratch memory
Subject: [PATCH 84/91] net-next: mediatek: fix missing free of scratch memory
Scratch memory gets allocated in mtk_init_fq_dma() but the corresponding
code to free it is missing inside mtk_dma_free() causing a memory leak.

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@ -1,7 +1,7 @@
From 7f0fb178cd514ea88aea611b0c92829be50bc8f6 Mon Sep 17 00:00:00 2001
From 7ae20e15e06eed22f343a566b22dce258f7b8704 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 23 Apr 2016 09:25:00 +0200
Subject: [PATCH 85/90] net-next: mediatek: invalid buffer lookup in
Subject: [PATCH 85/91] net-next: mediatek: invalid buffer lookup in
mtk_tx_map()
The lookup of the tx_buffer in the error path inside mtk_tx_map() uses the

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@ -1,7 +1,7 @@
From 84376b626114ba6f33f86602379790743d4c4f85 Mon Sep 17 00:00:00 2001
From d74187cab7927d3496c01c97051d9c539067ad1b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 23 Apr 2016 09:28:25 +0200
Subject: [PATCH 86/90] net-next: mediatek: dropped rx packets are not being
Subject: [PATCH 86/91] net-next: mediatek: dropped rx packets are not being
counted properly
There are 2 places inside mtk_poll_rx where rx_dropped is not being

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@ -1,7 +1,7 @@
From f74d752da12c1b63bf2bbfa220aab5e2dd644157 Mon Sep 17 00:00:00 2001
From 4ff9304355036d4a00bdf0e47e869fc770ba1cc5 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 20 Apr 2016 16:18:07 +0200
Subject: [PATCH 87/90] net-next: mediatek: add IRQ locking
Subject: [PATCH 87/91] net-next: mediatek: add IRQ locking
The code that enables and disables IRQs is missing proper locking. After
adding the IRQ separation patch and routing the putting the RX and TX IRQs

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@ -1,7 +1,7 @@
From 781eb70655d4f25af51aafcc010851918d49b2d7 Mon Sep 17 00:00:00 2001
From 41b4500871ab5b1ef27c6fb49ffd8aac8c7e5009 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 23 Mar 2016 18:31:48 +0100
Subject: [PATCH 88/90] net-next: mediatek: add support for IRQ grouping
Subject: [PATCH 88/91] net-next: mediatek: add support for IRQ grouping
The ethernet core has 3 IRQs. using the IRQ grouping registers we are able
to separate TX and RX IRQs, which allows us to service them on separate

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@ -1,7 +1,7 @@
From bb14507c0624e088da231b6b20fd6add032e9226 Mon Sep 17 00:00:00 2001
From 46f10e3c9c25668efb85babe9ac5e37d019c2794 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 11 Apr 2016 03:11:54 +0200
Subject: [PATCH 89/90] net: mediatek add gsw/mt7530 driver
Subject: [PATCH 89/91] net: mediatek add gsw/mt7530 driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---

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@ -1,7 +1,7 @@
From 9ad385f5a3d79d40938bfc265dc69821f6ecb5b8 Mon Sep 17 00:00:00 2001
From 7d2bdde21bc72eb41878890149f2b9d05fc3af6e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 11 Apr 2016 06:00:23 +0200
Subject: [PATCH 90/90] net: mediatek: v4.4 backports
Subject: [PATCH 90/91] net: mediatek: v4.4 backports
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 23 ++++++++++++++---------

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@ -0,0 +1,249 @@
From 34e10b96d5ccb99fb78251051bc5652b09359983 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 28 Apr 2016 07:58:22 +0200
Subject: [PATCH 91/91] net-next: mediatek WIP
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 89 ++++++++++++---------------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +-
2 files changed, 44 insertions(+), 50 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 5d33053..2e05920 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -326,7 +326,7 @@ static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
val = mtk_r32(eth, MTK_QDMA_INT_MASK);
mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
/* flush write */
- mtk_r32(eth, MTK_QDMA_INT_MASK);
+// mtk_r32(eth, MTK_QDMA_INT_MASK);
spin_unlock_irqrestore(&eth->irq_lock, flags);
}
@@ -339,7 +339,7 @@ static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
val = mtk_r32(eth, MTK_QDMA_INT_MASK);
mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
/* flush write */
- mtk_r32(eth, MTK_QDMA_INT_MASK);
+// mtk_r32(eth, MTK_QDMA_INT_MASK);
spin_unlock_irqrestore(&eth->irq_lock, flags);
}
@@ -710,10 +710,26 @@ static inline int mtk_cal_txd_req(struct sk_buff *skb)
return nfrags;
}
+static int mtk_queue_stopped(struct mtk_eth *eth)
+{
+ int i;
+
+ for (i = 0; i < MTK_MAC_COUNT; i++) {
+ if (!eth->netdev[i])
+ continue;
+ if (netif_queue_stopped(eth->netdev[i]))
+ return 1;
+ }
+
+ return 0;
+}
+
static void mtk_wake_queue(struct mtk_eth *eth)
{
int i;
+ printk("%s:%s[%d]w\n", __FILE__, __func__, __LINE__);
+
for (i = 0; i < MTK_MAC_COUNT; i++) {
if (!eth->netdev[i])
continue;
@@ -725,6 +741,7 @@ static void mtk_stop_queue(struct mtk_eth *eth)
{
int i;
+ printk("%s:%s[%d]s\n", __FILE__, __func__, __LINE__);
for (i = 0; i < MTK_MAC_COUNT; i++) {
if (!eth->netdev[i])
continue;
@@ -775,12 +792,9 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
goto drop;
- if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
+ if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
mtk_stop_queue(eth);
- if (unlikely(atomic_read(&ring->free_count) >
- ring->thresh))
- mtk_wake_queue(eth);
- }
+
spin_unlock_irqrestore(&eth->page_lock, flags);
return NETDEV_TX_OK;
@@ -927,7 +941,6 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget)
}
mtk_tx_unmap(eth->dev, tx_buf);
- ring->last_free->txd2 = next_cpu;
ring->last_free = desc;
atomic_inc(&ring->free_count);
@@ -945,11 +958,8 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget)
netdev_completed_queue(eth->netdev[i], done, bytes);
}
- /* read hw index again make sure no new tx packet */
- if (cpu == dma && cpu == mtk_r32(eth, MTK_QTX_DRX_PTR))
- mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
-
- if (atomic_read(&ring->free_count) > ring->thresh)
+ if (mtk_queue_stopped(eth) &&
+ (atomic_read(&ring->free_count) > ring->thresh))
mtk_wake_queue(eth);
return done;
@@ -973,10 +983,11 @@ static int mtk_napi_tx(struct napi_struct *napi, int budget)
int tx_done = 0;
mtk_handle_status_irq(eth);
-
- status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
+ mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
tx_done = mtk_poll_tx(eth, budget);
+
if (unlikely(netif_msg_intr(eth))) {
+ status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
dev_info(eth->dev,
"done tx %d, intr 0x%08x/0x%x\n",
@@ -1002,9 +1013,12 @@ static int mtk_napi_rx(struct napi_struct *napi, int budget)
u32 status, mask;
int rx_done = 0;
- status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
+ mtk_handle_status_irq(eth);
+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
rx_done = mtk_poll_rx(napi, budget, eth);
+
if (unlikely(netif_msg_intr(eth))) {
+ status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
dev_info(eth->dev,
"done rx %d, intr 0x%08x/0x%x\n",
@@ -1052,9 +1066,8 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
ring->next_free = &ring->dma[0];
- ring->last_free = &ring->dma[MTK_DMA_SIZE - 2];
- ring->thresh = max((unsigned long)MTK_DMA_SIZE >> 2,
- MAX_SKB_FRAGS);
+ ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
+ ring->thresh = MAX_SKB_FRAGS;
/* make sure that all changes to the dma ring are flushed before we
* continue
@@ -1259,21 +1272,11 @@ static void mtk_tx_timeout(struct net_device *dev)
static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
{
struct mtk_eth *eth = _eth;
- u32 status;
-
- status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
- status &= ~MTK_TX_DONE_INT;
-
- if (unlikely(!status))
- return IRQ_NONE;
- if (status & MTK_RX_DONE_INT) {
- if (likely(napi_schedule_prep(&eth->rx_napi))) {
- mtk_irq_disable(eth, MTK_RX_DONE_INT);
- __napi_schedule(&eth->rx_napi);
- }
+ if (likely(napi_schedule_prep(&eth->rx_napi))) {
+ __napi_schedule(&eth->rx_napi);
+ mtk_irq_disable(eth, MTK_RX_DONE_INT);
}
- mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
return IRQ_HANDLED;
}
@@ -1281,21 +1284,11 @@ static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
{
struct mtk_eth *eth = _eth;
- u32 status;
-
- status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
- status &= ~MTK_RX_DONE_INT;
-
- if (unlikely(!status))
- return IRQ_NONE;
- if (status & MTK_TX_DONE_INT) {
- if (likely(napi_schedule_prep(&eth->tx_napi))) {
- mtk_irq_disable(eth, MTK_TX_DONE_INT);
- __napi_schedule(&eth->tx_napi);
- }
+ if (likely(napi_schedule_prep(&eth->tx_napi))) {
+ __napi_schedule(&eth->tx_napi);
+ mtk_irq_disable(eth, MTK_TX_DONE_INT);
}
- mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
return IRQ_HANDLED;
}
@@ -1326,7 +1319,7 @@ static int mtk_start_dma(struct mtk_eth *eth)
mtk_w32(eth,
MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
- MTK_RX_BT_32DWORDS,
+ MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
MTK_QDMA_GLO_CFG);
return 0;
@@ -1440,7 +1433,7 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
/* disable delay and normal interrupt */
mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
- mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
+ mtk_irq_disable(eth, ~0);
mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
mtk_w32(eth, 0, MTK_RST_GL);
@@ -1765,7 +1758,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
SET_NETDEV_DEV(eth->netdev[id], eth->dev);
- eth->netdev[id]->watchdog_timeo = HZ;
+ eth->netdev[id]->watchdog_timeo = 4 * HZ;
eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
eth->netdev[id]->base_addr = (unsigned long)eth->base;
eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 5093518..6b22445 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -18,9 +18,9 @@
#define MTK_QDMA_PAGE_SIZE 2048
#define MTK_MAX_RX_LENGTH 1536
#define MTK_TX_DMA_BUF_LEN 0x3fff
-#define MTK_DMA_SIZE 256
-#define MTK_NAPI_WEIGHT 64
#define MTK_MAC_COUNT 2
+#define MTK_DMA_SIZE (256 * MTK_MAC_COUNT)
+#define MTK_NAPI_WEIGHT (64 * MTK_MAC_COUNT)
#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
#define MTK_DMA_DUMMY_DESC 0xffffffff
@@ -95,6 +95,7 @@
#define MTK_QDMA_GLO_CFG 0x1A04
#define MTK_RX_2B_OFFSET BIT(31)
#define MTK_RX_BT_32DWORDS (3 << 11)
+#define MTK_NDP_CO_PRO BIT(10)
#define MTK_TX_WB_DDONE BIT(6)
#define MTK_DMA_SIZE_16DWORDS (2 << 4)
#define MTK_RX_DMA_BUSY BIT(3)
--
1.7.10.4