mirror of https://github.com/hak5/openwrt.git
ar8216: Remove read/write/rmw member functions from ar8xxx_priv
Remove read/write/rmw member functions from ar8xxx_priv There seems to be no real benefit of the ar8xxx_priv member functions read/write/rmw as one implementation exists for each of them only. Especially ar8xxx_mii_rmw is assigned to priv->rmw first and then mapped to ar8xxx_rmw. Rename the ar8xxx_mii_.. functions to ar8xxx_.. and use them directly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> SVN-Revision: 43742lede-17.01
Felix Fietkau
parent
45a494b808
commit
2289c7a010
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@ -141,10 +141,6 @@ struct ar8xxx_priv {
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struct mii_bus *mii_bus;
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struct phy_device *phy;
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u32 (*read)(struct ar8xxx_priv *priv, int reg);
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void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
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u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
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int (*get_port_link)(unsigned port);
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const struct net_device_ops *ndo_old;
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@ -430,7 +426,7 @@ mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
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}
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static u32
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ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
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ar8xxx_read(struct ar8xxx_priv *priv, int reg)
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{
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struct mii_bus *bus = priv->mii_bus;
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u16 r1, r2, page;
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@ -450,7 +446,7 @@ ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
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}
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static void
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ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
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ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
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{
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struct mii_bus *bus = priv->mii_bus;
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u16 r1, r2, page;
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@ -467,7 +463,7 @@ ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
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}
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static u32
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ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
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ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
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{
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struct mii_bus *bus = priv->mii_bus;
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u16 r1, r2, page;
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@ -513,16 +509,10 @@ ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
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mutex_unlock(&bus->mdio_lock);
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}
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static inline u32
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ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
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{
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return priv->rmw(priv, reg, mask, val);
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}
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static inline void
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ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
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{
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priv->rmw(priv, reg, 0, val);
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ar8xxx_rmw(priv, reg, 0, val);
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}
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static int
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@ -534,7 +524,7 @@ ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
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for (i = 0; i < timeout; i++) {
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u32 t;
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t = priv->read(priv, reg);
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t = ar8xxx_read(priv, reg);
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if ((t & mask) == val)
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return 0;
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@ -598,11 +588,11 @@ ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
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u64 t;
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mib = &priv->chip->mib_decs[i];
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t = priv->read(priv, base + mib->offset);
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t = ar8xxx_read(priv, base + mib->offset);
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if (mib->size == 2) {
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u64 hi;
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hi = priv->read(priv, base + mib->offset + 4);
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hi = ar8xxx_read(priv, base + mib->offset + 4);
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t |= hi << 32;
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}
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@ -738,7 +728,7 @@ ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
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u32 t = 0;
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while (1) {
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t = priv->read(priv, reg);
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t = ar8xxx_read(priv, reg);
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if ((t & mask) == val)
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return 0;
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@ -761,10 +751,10 @@ ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
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if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
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val &= AR8216_VTUDATA_MEMBER;
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val |= AR8216_VTUDATA_VALID;
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priv->write(priv, AR8216_REG_VTU_DATA, val);
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ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
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}
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op |= AR8216_VTU_ACTIVE;
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priv->write(priv, AR8216_REG_VTU, op);
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ar8xxx_write(priv, AR8216_REG_VTU, op);
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}
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static void
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@ -789,7 +779,7 @@ ar8216_atu_flush(struct ar8xxx_priv *priv)
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ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
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if (!ret)
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priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
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ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
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return ret;
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}
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@ -797,7 +787,7 @@ ar8216_atu_flush(struct ar8xxx_priv *priv)
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static u32
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ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
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{
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return priv->read(priv, AR8216_REG_PORT_STATUS(port));
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return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
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}
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static void
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@ -857,7 +847,7 @@ static void
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ar8216_init_globals(struct ar8xxx_priv *priv)
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{
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/* standard atheros magic */
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priv->write(priv, 0x38, 0xc000050e);
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ar8xxx_write(priv, 0x38, 0xc000050e);
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ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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AR8216_GCTRL_MTU, 1518 + 8 + 2);
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@ -867,14 +857,14 @@ static void
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ar8216_init_port(struct ar8xxx_priv *priv, int port)
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{
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/* Enable port learning and tx */
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priv->write(priv, AR8216_REG_PORT_CTRL(port),
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ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
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AR8216_PORT_CTRL_LEARN |
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(4 << AR8216_PORT_CTRL_STATE_S));
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priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
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ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
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if (port == AR8216_PORT_CPU) {
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priv->write(priv, AR8216_REG_PORT_STATUS(port),
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ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
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AR8216_PORT_STATUS_LINK_UP |
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(ar8xxx_has_gige(priv) ?
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AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
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@ -884,7 +874,7 @@ ar8216_init_port(struct ar8xxx_priv *priv, int port)
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(chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
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AR8216_PORT_STATUS_DUPLEX);
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} else {
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priv->write(priv, AR8216_REG_PORT_STATUS(port),
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ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
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AR8216_PORT_STATUS_LINK_AUTO);
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}
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}
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@ -954,7 +944,7 @@ ar8316_hw_init(struct ar8xxx_priv *priv)
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{
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u32 val, newval;
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val = priv->read(priv, AR8316_REG_POSTRIP);
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val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
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if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
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if (priv->port4_phy) {
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@ -978,7 +968,7 @@ ar8316_hw_init(struct ar8xxx_priv *priv)
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if (val == newval)
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goto out;
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priv->write(priv, AR8316_REG_POSTRIP, newval);
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ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
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if (priv->port4_phy &&
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priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
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@ -1002,10 +992,10 @@ static void
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ar8316_init_globals(struct ar8xxx_priv *priv)
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{
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/* standard atheros magic */
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priv->write(priv, 0x38, 0xc000050e);
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ar8xxx_write(priv, 0x38, 0xc000050e);
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/* enable cpu port to receive multicast and broadcast frames */
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priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
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ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
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/* enable jumbo frames */
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ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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@ -1495,13 +1485,13 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
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if (chip_is_ar8337(priv))
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t |= AR8337_PAD_MAC06_EXCHANGE_EN;
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priv->write(priv, AR8327_REG_PAD0_MODE, t);
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ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
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t = ar8327_get_pad_cfg(pdata->pad5_cfg);
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priv->write(priv, AR8327_REG_PAD5_MODE, t);
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ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
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t = ar8327_get_pad_cfg(pdata->pad6_cfg);
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priv->write(priv, AR8327_REG_PAD6_MODE, t);
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ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
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pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
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pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
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new_pos = pos;
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led_cfg = pdata->led_cfg;
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@ -1511,10 +1501,10 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
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else
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new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
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priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
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priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
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priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
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priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
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ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
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ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
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ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
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ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
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if (new_pos != pos)
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new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
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@ -1531,7 +1521,7 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
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AR8327_SGMII_CTRL_EN_RX |
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AR8327_SGMII_CTRL_EN_TX);
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priv->write(priv, AR8327_REG_SGMII_CTRL, t);
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ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
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if (pdata->sgmii_cfg->serdes_aen)
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new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
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@ -1539,7 +1529,7 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
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new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
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}
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priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
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ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
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if (pdata->leds && pdata->num_leds) {
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int i;
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@ -1586,7 +1576,7 @@ ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
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data->port6_status = val;
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break;
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default:
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priv->write(priv, reg, val);
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ar8xxx_write(priv, reg, val);
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break;
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}
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}
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@ -1640,13 +1630,13 @@ ar8327_init_globals(struct ar8xxx_priv *priv)
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/* enable CPU port and disable mirror port */
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t = AR8327_FWD_CTRL0_CPU_PORT_EN |
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AR8327_FWD_CTRL0_MIRROR_PORT;
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priv->write(priv, AR8327_REG_FWD_CTRL0, t);
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ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
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/* forward multicast and broadcast frames to CPU */
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t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
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(AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
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(AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
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priv->write(priv, AR8327_REG_FWD_CTRL1, t);
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ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
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/* enable jumbo frames */
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ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
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@ -1657,13 +1647,13 @@ ar8327_init_globals(struct ar8xxx_priv *priv)
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AR8327_MODULE_EN_MIB);
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/* Disable EEE on all ports due to stability issues */
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t = priv->read(priv, AR8327_REG_EEE_CTRL);
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t = ar8xxx_read(priv, AR8327_REG_EEE_CTRL);
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t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
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AR8327_EEE_CTRL_DISABLE_PHY(1) |
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AR8327_EEE_CTRL_DISABLE_PHY(2) |
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AR8327_EEE_CTRL_DISABLE_PHY(3) |
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AR8327_EEE_CTRL_DISABLE_PHY(4);
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priv->write(priv, AR8327_REG_EEE_CTRL, t);
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ar8xxx_write(priv, AR8327_REG_EEE_CTRL, t);
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}
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static void
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@ -1679,25 +1669,25 @@ ar8327_init_port(struct ar8xxx_priv *priv, int port)
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else
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t = AR8216_PORT_STATUS_LINK_AUTO;
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priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
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priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
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ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
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ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
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t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
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t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
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priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
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ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
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t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
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priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
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ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
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t = AR8327_PORT_LOOKUP_LEARN;
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t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
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priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
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ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
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}
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static u32
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ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
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{
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return priv->read(priv, AR8327_REG_PORT_STATUS(port));
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return ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
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}
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static int
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@ -1708,7 +1698,7 @@ ar8327_atu_flush(struct ar8xxx_priv *priv)
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ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
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AR8327_ATU_FUNC_BUSY, 0);
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if (!ret)
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priv->write(priv, AR8327_REG_ATU_FUNC,
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ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
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AR8327_ATU_FUNC_OP_FLUSH);
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return ret;
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@ -1722,10 +1712,10 @@ ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
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return;
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if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
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priv->write(priv, AR8327_REG_VTU_FUNC0, val);
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ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
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op |= AR8327_VTU_FUNC1_BUSY;
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priv->write(priv, AR8327_REG_VTU_FUNC1, op);
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ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
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}
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static void
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@ -1777,17 +1767,17 @@ ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
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t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
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t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
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priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
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ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
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t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
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t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
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priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
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ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
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t = members;
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t |= AR8327_PORT_LOOKUP_LEARN;
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t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
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t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
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priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
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ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
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}
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static int
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@ -2647,7 +2637,7 @@ ar8xxx_id_chip(struct ar8xxx_priv *priv)
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u16 id;
|
||||
int i;
|
||||
|
||||
val = priv->read(priv, AR8216_REG_CTRL);
|
||||
val = ar8xxx_read(priv, AR8216_REG_CTRL);
|
||||
if (val == ~0)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
@ -2655,7 +2645,7 @@ ar8xxx_id_chip(struct ar8xxx_priv *priv)
|
|||
for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
|
||||
u16 t;
|
||||
|
||||
val = priv->read(priv, AR8216_REG_CTRL);
|
||||
val = ar8xxx_read(priv, AR8216_REG_CTRL);
|
||||
if (val == ~0)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
@ -2791,12 +2781,8 @@ ar8xxx_create_mii(struct mii_bus *bus)
|
|||
struct ar8xxx_priv *priv;
|
||||
|
||||
priv = ar8xxx_create();
|
||||
if (priv) {
|
||||
if (priv)
|
||||
priv->mii_bus = bus;
|
||||
priv->read = ar8xxx_mii_read;
|
||||
priv->write = ar8xxx_mii_write;
|
||||
priv->rmw = ar8xxx_mii_rmw;
|
||||
}
|
||||
|
||||
return priv;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue