mirror of https://github.com/hak5/openwrt.git
Lars-Peter Clausen
parent
8c43d37dbb
commit
2233a27d43
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@ -0,0 +1,98 @@
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#
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# Copyright (C) 2010 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=u-boot
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PKG_VERSION:=2010.03
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PKG_RELEASE:=1
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PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
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PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
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PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
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PKG_MD5SUM:=
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PKG_TARGETS:=bin
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include $(INCLUDE_DIR)/package.mk
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define uboot/Default
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TITLE:=
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CONFIG:=
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IMAGE:=
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endef
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define uboot/sheevaplug
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TITLE:=U-boot for the Sheevaplug
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endef
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define uboot/dockstar
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TITLE:=U-boot for the Seagate Dockstar
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endef
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UBOOTS:=sheevaplug dockstar
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define Package/uboot/template
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define Package/uboot-kirkwood-$(1)
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SECTION:=boot
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CATEGORY:=Boot Loaders
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DEPENDS:=@TARGET_kirkwood
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TITLE:=$(2)
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URL:=http://www.denx.de/wiki/U-Boot
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VARIANT:=$(1)
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endef
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endef
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define BuildUbootPackage
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$(eval $(uboot/Default))
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$(eval $(uboot/$(1)))
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$(call Package/uboot/template,$(1),$(TITLE))
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endef
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ifdef BUILD_VARIANT
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$(eval $(call uboot/$(BUILD_VARIANT)))
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UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
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UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_BARIANT)-u-boot.bin)
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endif
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define Build/Prepare
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$(call Build/Prepare/Default)
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$(CP) ./files/* $(PKG_BUILD_DIR) || true
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find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
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endef
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define Build/Configure
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$(MAKE) -C $(PKG_BUILD_DIR) \
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$(UBOOT_CONFIG)_config
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endef
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define Build/Compile
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$(MAKE) -C $(PKG_BUILD_DIR) \
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CROSS_COMPILE=$(TARGET_CROSS)
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endef
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define Package/uboot/install/default
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$(INSTALL_DIR) $(BIN_DIR)
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$(CP) $(PKG_BUILD_DIR)/u-boot.bin \
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$(BIN_DIR)/openwrt-$(BOARD)-$(1)-u-boot.bin
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endef
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define Package/uboot/install/template
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define Package/uboot-kirkwood-$(1)/install
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$(call Package/uboot/install/default,$(2))
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endef
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endef
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$(foreach u,$(UBOOTS), \
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$(eval $(call Package/uboot/install/template,$(u),$(u))) \
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)
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$(foreach u,$(UBOOTS), \
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$(eval $(call BuildUbootPackage,$(u))) \
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$(eval $(call BuildPackage,uboot-kirkwood-$(u))) \
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)
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@ -0,0 +1,51 @@
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := dockstar.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,28 @@
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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TEXT_BASE = 0x00800000
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# Kirkwood Boot Image configuration file
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KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
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@ -0,0 +1,155 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "dockstar.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
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DOCKSTAR_OE_VAL_HIGH,
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DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_UART0_RTS,
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MPP9_UART0_CTS,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_TSMP9,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config);
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/*
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* arch number of board
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*/
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gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = kw_sdram_bar(i);
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gd->bd->bi_dram[i].size = kw_sdram_bs(i);
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}
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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u16 reg;
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u16 devadr;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__FUNCTION__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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@ -0,0 +1,41 @@
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/*
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* (C) Copyright 2009
|
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
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*/
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#ifndef __DOCKSTAR_H
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#define __DOCKSTAR_H
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#define DOCKSTAR_OE_LOW (~(0))
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#define DOCKSTAR_OE_HIGH (~(0))
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#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
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#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
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/* PHY related */
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __DOCKSTAR_H */
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@ -0,0 +1,162 @@
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#
|
||||
# (C) Copyright 2009
|
||||
# Marvell Semiconductor <www.marvell.com>
|
||||
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.kwimage for more details about how-to configure
|
||||
# and create kirkwood boot image
|
||||
#
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM nand
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||||
NAND_ECC_MODE default
|
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NAND_PAGE_SIZE 0x0800
|
||||
|
||||
# SOC registers configuration using bootrom header extension
|
||||
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
||||
|
||||
# Configure RGMII-0 interface pad voltage to 1.8V
|
||||
DATA 0xFFD100e0 0x1b1b1b9b
|
||||
|
||||
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
||||
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
|
||||
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
|
||||
# bit23-14: zero
|
||||
# bit24: 1= enable exit self refresh mode on DDR access
|
||||
# bit25: 1 required
|
||||
# bit29-26: zero
|
||||
# bit31-30: 01
|
||||
|
||||
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
|
||||
# bit 4: 0=addr/cmd in smame cycle
|
||||
# bit 5: 0=clk is driven during self refresh, we don't care for APX
|
||||
# bit 6: 0=use recommended falling edge of clk for addr/cmd
|
||||
# bit14: 0=input buffer always powered up
|
||||
# bit18: 1=cpu lock transaction enabled
|
||||
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
||||
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
||||
# bit30-28: 3 required
|
||||
# bit31: 0=no additional STARTBURST delay
|
||||
|
||||
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
|
||||
# bit3-0: TRAS lsbs
|
||||
# bit7-4: TRCD
|
||||
# bit11- 8: TRP
|
||||
# bit15-12: TWR
|
||||
# bit19-16: TWTR
|
||||
# bit20: TRAS msb
|
||||
# bit23-21: 0x0
|
||||
# bit27-24: TRRD
|
||||
# bit31-28: TRTP
|
||||
|
||||
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
|
||||
# bit6-0: TRFC
|
||||
# bit8-7: TR2R
|
||||
# bit10-9: TR2W
|
||||
# bit12-11: TW2W
|
||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x000000cc # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
||||
# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs1width=x8
|
||||
# bit7-6: 11, Cs1size=1Gb
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x0F, Size (i.e. 256MB)
|
||||
|
||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_SHEEVAPLUG_H
|
||||
#define _CONFIG_SHEEVAPLUG_H
|
||||
|
||||
/*
|
||||
* Version number information
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING "\nMarvell-Sheevaplug"
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_MARVELL 1
|
||||
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
|
||||
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
|
||||
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
|
||||
#define CONFIG_KW88F6281 1 /* SOC Name */
|
||||
#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
|
||||
|
||||
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
|
||||
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
|
||||
|
||||
/*
|
||||
* CLKs configurations
|
||||
*/
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
|
||||
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
|
||||
|
||||
/*
|
||||
* Serial Port configuration
|
||||
* The following definitions let you select what serial you want to use
|
||||
* for your console driver.
|
||||
*/
|
||||
|
||||
#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
|
||||
115200,230400, 460800, 921600 }
|
||||
/* auto boot */
|
||||
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
|
||||
|
||||
#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_AUTOSCRIPT
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* NAND configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_KIRKWOOD
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
|
||||
#define NAND_ALLOW_ERASE_ALL 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
|
||||
#endif
|
||||
/*
|
||||
* max 4k env size is enough, but in case of nand
|
||||
* it has to be rounded to sector size
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
|
||||
#define CONFIG_ENV_ADDR 0x140000
|
||||
#define CONFIG_ENV_OFFSET 0x140000 /* env starts here */
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
|
||||
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
|
||||
"${x_bootcmd_usb}; bootm 0x6400000;"
|
||||
|
||||
#define CONFIG_MTDPARTS "orion_nand:1M(u-boot)," \
|
||||
"1M@1M(second_stage_u-boot)," \
|
||||
"3M@2M(kernel),64M@5M(rootfs),187M@69M(data) rw\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
|
||||
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
|
||||
"x_bootcmd_kernel=nand read 0x6400000 0x200000 0x300000\0" \
|
||||
"x_bootcmd_usb=usb start\0" \
|
||||
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
|
||||
/*
|
||||
* Other required minimal configurations
|
||||
*/
|
||||
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
|
||||
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
|
||||
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
|
||||
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
|
||||
#define CONFIG_NR_DRAM_BANKS 4
|
||||
#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
#define CONFIG_NET_MULTI /* specify more that one ports available */
|
||||
#define CONFIG_MII /* expose smi ove miiphy interface */
|
||||
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
|
||||
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
|
||||
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 0
|
||||
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
|
||||
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* USB/EHCI
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
|
||||
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
#endif /* CONFIG_CMD_USB */
|
||||
|
||||
#define CONFIG_SERVERIP 169.254.254.254
|
||||
#define CONFIG_IPADDR 169.254.254.243
|
||||
#endif /* _CONFIG_SHEEVAPLUG_H */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -3039,6 +3039,9 @@
|
||||
sheevaplug_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
|
||||
|
||||
+dockstar_config: unconfig
|
||||
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
|
||||
+
|
||||
smdk2400_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 samsung s3c24x0
|
||||
|
||||
--- a/include/asm-arm/mach-types.h
|
||||
+++ b/include/asm-arm/mach-types.h
|
||||
@@ -2699,6 +2699,7 @@
|
||||
#define MACH_TYPE_MX53_EVK 2716
|
||||
#define MACH_TYPE_IGEP0030 2717
|
||||
#define MACH_TYPE_AXELL_H40_H50_CTRL 2718
|
||||
+#define MACH_TYPE_DOCKSTAR 2998
|
||||
|
||||
#ifdef CONFIG_ARCH_EBSA110
|
||||
# ifdef machine_arch_type
|
||||
Loading…
Reference in New Issue