mirror of https://github.com/hak5/openwrt.git
ramips: remove conditional compilation.
Code currently defines: and then compiles code only if they are defined. We might want to disable some of these via devicetree one day, but for now just remove the #defines and the conditions - all the code for different ports is easy to identify. Signed-off-by: NeilBrown <neil@brown.name> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>openwrt-18.06
NeilBrown
John Crispin
parent
5f7396ebef
commit
1f78625714
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@ -65,9 +65,6 @@ extern void chk_phy_pll(void);
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* devices.
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*/
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#define CONFIG_PCIE_PORT0
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#define CONFIG_PCIE_PORT1
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#define CONFIG_PCIE_PORT2
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#define RALINK_PCIE0_CLK_EN (1<<24)
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#define RALINK_PCIE1_CLK_EN (1<<25)
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#define RALINK_PCIE2_CLK_EN (1<<26)
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@ -144,7 +141,7 @@ extern void chk_phy_pll(void);
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#define RALINK_PCI_IO_MAP_BASE 0x1e160000
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#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
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#define GPIO_PERST
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#define ASSERT_SYSRST_PCIE(val) do { \
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if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
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RALINK_RSTCTRL |= val; \
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@ -397,21 +394,15 @@ set_pcie_phy(u32 *addr, int start_b, int bits, int val)
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void
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bypass_pipe_rst(void)
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{
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#if defined (CONFIG_PCIE_PORT0)
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/* PCIe Port 0 */
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
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#endif
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#if defined (CONFIG_PCIE_PORT1)
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/* PCIe Port 1 */
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
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#endif
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#if defined (CONFIG_PCIE_PORT2)
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/* PCIe Port 2 */
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
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#endif
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}
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void
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@ -420,7 +411,6 @@ set_phy_for_ssc(void)
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unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
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reg = (reg >> 6) & 0x7;
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#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
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/* Set PCIe Port0 & Port1 PHY to disable SSC */
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/* Debug Xtal Type */
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
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@ -461,8 +451,7 @@ set_phy_for_ssc(void)
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
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#endif
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#if defined (CONFIG_PCIE_PORT2)
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/* Set PCIe Port2 PHY to disable SSC */
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/* Debug Xtal Type */
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
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@ -495,7 +484,6 @@ set_phy_for_ssc(void)
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/* Enable PHY and disable force mode */
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
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#endif
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}
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void setup_cm_memory_region(struct resource *mem_resource)
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@ -528,18 +516,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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ioport_resource.start= 0;
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ioport_resource.end = ~0;
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#if defined (CONFIG_PCIE_PORT0)
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val = RALINK_PCIE0_RST;
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#endif
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#if defined (CONFIG_PCIE_PORT1)
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val |= RALINK_PCIE1_RST;
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#endif
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#if defined (CONFIG_PCIE_PORT2)
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val |= RALINK_PCIE2_RST;
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#endif
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ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
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printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
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#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
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*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
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*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
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mdelay(100);
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@ -548,18 +531,11 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
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mdelay(100);
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#else
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*(unsigned int *)(0xbe000060) &= ~0x00000c00;
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#endif
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#if defined (CONFIG_PCIE_PORT0)
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val = RALINK_PCIE0_RST;
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#endif
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#if defined (CONFIG_PCIE_PORT1)
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val |= RALINK_PCIE1_RST;
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#endif
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#if defined (CONFIG_PCIE_PORT2)
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val |= RALINK_PCIE2_RST;
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#endif
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DEASSERT_SYSRST_PCIE(val);
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printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
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@ -568,18 +544,12 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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set_phy_for_ssc();
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printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
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#if defined (CONFIG_PCIE_PORT0)
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read_config(0, 0, 0, 0x70c, &val);
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printk("Port 0 N_FTS = %x\n", (unsigned int)val);
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#endif
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#if defined (CONFIG_PCIE_PORT1)
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read_config(0, 1, 0, 0x70c, &val);
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printk("Port 1 N_FTS = %x\n", (unsigned int)val);
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#endif
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#if defined (CONFIG_PCIE_PORT2)
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read_config(0, 2, 0, 0x70c, &val);
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printk("Port 2 N_FTS = %x\n", (unsigned int)val);
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#endif
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RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
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RALINK_SYSCFG1 &= ~(0x30);
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@ -590,19 +560,11 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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RALINK_PCIE_CLK_GEN |= 0x80000000;
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mdelay(50);
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RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
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#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
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/* Use GPIO control instead of PERST_N */
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*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
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mdelay(100);
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#else
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RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
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#endif
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mdelay(500);
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mdelay(1000);
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mdelay(500);
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#if defined (CONFIG_PCIE_PORT0)
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if(( RALINK_PCI0_STATUS & 0x1) == 0)
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{
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printk("PCIE0 no card, disable it(RST&CLK)\n");
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@ -613,8 +575,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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pcie_link_status |= 1<<0;
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RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
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}
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#endif
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#if defined (CONFIG_PCIE_PORT1)
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if(( RALINK_PCI1_STATUS & 0x1) == 0)
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{
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printk("PCIE1 no card, disable it(RST&CLK)\n");
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@ -625,8 +585,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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pcie_link_status |= 1<<1;
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RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
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}
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#endif
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#if defined (CONFIG_PCIE_PORT2)
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if (( RALINK_PCI2_STATUS & 0x1) == 0) {
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printk("PCIE2 no card, disable it(RST&CLK)\n");
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ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
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@ -636,7 +594,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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pcie_link_status |= 1<<2;
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RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
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}
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#endif
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if (pcie_link_status == 0)
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return 0;
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@ -687,7 +644,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
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RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
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#if defined (CONFIG_PCIE_PORT0)
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//PCIe0
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if((pcie_link_status & 0x1) != 0) {
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RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
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@ -695,8 +651,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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RALINK_PCI0_CLASS = 0x06040001;
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printk("PCIE0 enabled\n");
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}
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#endif
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#if defined (CONFIG_PCIE_PORT1)
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//PCIe1
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if ((pcie_link_status & 0x2) != 0) {
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RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
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@ -704,8 +658,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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RALINK_PCI1_CLASS = 0x06040001;
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printk("PCIE1 enabled\n");
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}
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#endif
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#if defined (CONFIG_PCIE_PORT2)
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//PCIe2
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if ((pcie_link_status & 0x4) != 0) {
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RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
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@ -713,8 +665,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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RALINK_PCI2_CLASS = 0x06040001;
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printk("PCIE2 enabled\n");
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}
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#endif
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switch(pcie_link_status) {
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case 7:
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