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lantiq: update to 3.14 

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 42188
lede-17.01
John Crispin 2014-08-18 13:09:30 +00:00
parent 860e01d7c4
commit 12b73579e4
35 changed files with 16059 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

164
target/linux/lantiq/config-3.14 Normal file
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@ -0,0 +1,164 @@
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_CEVT_R4K=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CSRC_R4K=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DTC=y
CONFIG_DT_EASY50712=y
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_MM_LANTIQ=y
CONFIG_GPIO_STP_XWAY=y
CONFIG_GPIO_SYSFS=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_GENERIC_HARDIRQS=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_MACH_CLKDEV=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQ_CPU=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_LANTIQ=y
CONFIG_LANTIQ_ETOP=y
# CONFIG_LANTIQ_PHY is not set
CONFIG_LANTIQ_WDT=y
# CONFIG_LANTIQ_XRX200 is not set
CONFIG_LEDS_GPIO=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MIPS=y
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_LANTIQ=y
# CONFIG_MTD_NAND_XWAY is not set
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_UIMAGE_SPLIT=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DEVICE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_PERCPU_RWSEM=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PHYLIB=y
CONFIG_PINCONF=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_LANTIQ=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PINCTRL_XWAY=y
CONFIG_PINMUX=y
# CONFIG_PREEMPT_RCU is not set
CONFIG_PROC_DEVICETREE=y
CONFIG_PSB6970_PHY=y
CONFIG_RTL8366RB_PHY=y
CONFIG_RTL8366_SMI=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_LANTIQ=y
# CONFIG_SOC_AMAZON_SE is not set
# CONFIG_SOC_FALCON is not set
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SOC_XWAY=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SWCONFIG=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_UIDGID_CONVERTED=y
CONFIG_USB_ARCH_HAS_XHCI=y
CONFIG_USE_OF=y
CONFIG_ZONE_DMA_FLAG=0

5597
target/linux/lantiq/patches-3.14/0001-MIPS-lantiq-add-pcie-driver.patch Normal file
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49
target/linux/lantiq/patches-3.14/0002-MIPS-lantiq-dtb-image-hack.patch Normal file
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@ -0,0 +1,49 @@
From 17348293f7f8103c97c8d2a6b0ef36eae06ec371 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 13 Mar 2013 09:36:16 +0100
Subject: [PATCH 02/31] MIPS: lantiq: dtb image hack
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/Makefile | 2 --
arch/mips/lantiq/prom.c | 4 +++-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
index d6bdc57..690257a 100644
--- a/arch/mips/lantiq/Makefile
+++ b/arch/mips/lantiq/Makefile
@@ -6,8 +6,6 @@
obj-y := irq.o clk.o prom.o
-obj-y += dts/
-
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 19686c5..202e118 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -58,6 +58,8 @@ static void __init prom_init_cmdline(void)
}
}
+extern struct boot_param_header __image_dtb;
+
void __init plat_mem_setup(void)
{
ioport_resource.start = IOPORT_RESOURCE_START;
@@ -71,7 +73,7 @@ void __init plat_mem_setup(void)
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
- __dt_setup_arch(&__dtb_start);
+ __dt_setup_arch(&__image_dtb);
}
void __init device_tree_init(void)
--
1.7.10.4

94
target/linux/lantiq/patches-3.14/0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch Normal file
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@ -0,0 +1,94 @@
From 16e315864132b59749faff739230daf4cee9abbb Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 13 Mar 2013 10:04:01 +0100
Subject: [PATCH 03/31] MIPS: lantiq: handle vmmc memory reservation
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/Makefile | 2 ++
arch/mips/lantiq/xway/vmmc.c | 63 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 arch/mips/lantiq/xway/vmmc.c
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 087497d..a2edc53 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,5 @@
obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+obj-y += vmmc.o
+
obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/vmmc.c b/arch/mips/lantiq/xway/vmmc.c
new file mode 100644
index 0000000..cea0ff9
--- /dev/null
+++ b/arch/mips/lantiq/xway/vmmc.c
@@ -0,0 +1,63 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/dma-mapping.h>
+
+#include <lantiq_soc.h>
+
+static unsigned int *cp1_base = 0;
+unsigned int* ltq_get_cp1_base(void)
+{
+ if (!cp1_base)
+ panic("no cp1 base was set\n");
+ return cp1_base;
+}
+EXPORT_SYMBOL(ltq_get_cp1_base);
+
+static int vmmc_probe(struct platform_device *pdev)
+{
+#define CP1_SIZE (1 << 20)
+ int gpio_count;
+ dma_addr_t dma;
+ cp1_base =
+ (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
+
+ gpio_count = of_gpio_count(pdev->dev.of_node);
+ while (gpio_count > 0) {
+ enum of_gpio_flags flags;
+ int gpio = of_get_gpio_flags(pdev->dev.of_node, --gpio_count, &flags);
+ if (gpio_request(gpio, "vmmc-relay"))
+ continue;
+ dev_info(&pdev->dev, "requested GPIO %d\n", gpio);
+ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
+ }
+
+ dev_info(&pdev->dev, "reserved %dMB at 0x%p", CP1_SIZE >> 20, cp1_base);
+
+ return 0;
+}
+
+static const struct of_device_id vmmc_match[] = {
+ { .compatible = "lantiq,vmmc" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, vmmc_match);
+
+static struct platform_driver vmmc_driver = {
+ .probe = vmmc_probe,
+ .driver = {
+ .name = "lantiq,vmmc",
+ .owner = THIS_MODULE,
+ .of_match_table = vmmc_match,
+ },
+};
+
+module_platform_driver(vmmc_driver);
--
1.7.10.4

519
target/linux/lantiq/patches-3.14/0004-MIPS-lantiq-add-atm-hack.patch Normal file
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@ -0,0 +1,519 @@
From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 3 Aug 2012 10:27:25 +0200
Subject: [PATCH 04/31] MIPS: lantiq: add atm hack
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
arch/mips/lantiq/irq.c | 2 +
arch/mips/mm/cache.c | 2 +
include/uapi/linux/atm.h | 6 +
net/atm/common.c | 6 +
net/atm/proc.c | 2 +-
7 files changed, 416 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_atm.h b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
new file mode 100644
index 0000000..bf045a9
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
@@ -0,0 +1,196 @@
+/******************************************************************************
+**
+** FILE NAME : ifx_atm.h
+** PROJECT : UEIP
+** MODULES : ATM
+**
+** DATE : 17 Jun 2009
+** AUTHOR : Xu Liang
+** DESCRIPTION : Global ATM driver header file
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Date $Author $Comment
+** 07 JUL 2009 Xu Liang Init Version
+*******************************************************************************/
+
+#ifndef IFX_ATM_H
+#define IFX_ATM_H
+
+
+
+/*!
+ \defgroup IFX_ATM UEIP Project - ATM driver module
+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+ \defgroup IFX_ATM_IOCTL IOCTL Commands
+ \ingroup IFX_ATM
+ \brief IOCTL Commands used by user application.
+ */
+
+/*!
+ \defgroup IFX_ATM_STRUCT Structures
+ \ingroup IFX_ATM
+ \brief Structures used by user application.
+ */
+
+/*!
+ \file ifx_atm.h
+ \ingroup IFX_ATM
+ \brief ATM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ * Definition
+ * ####################################
+ */
+
+/*!
+ \addtogroup IFX_ATM_STRUCT
+ */
+/*@{*/
+
+/*
+ * ATM MIB
+ */
+
+/*!
+ \struct atm_cell_ifEntry_t
+ \brief Structure used for Cell Level MIB Counters.
+
+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
+ */
+typedef struct {
+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
+ __u32 ifInErrors; /*!< counter of error ingress cells */
+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
+ __u32 ifOutErrors; /*!< counter of error egress cells */
+} atm_cell_ifEntry_t;
+
+/*!
+ \struct atm_aal5_ifEntry_t
+ \brief Structure used for AAL5 Frame Level MIB Counters.
+
+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
+ */
+typedef struct {
+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
+ __u32 ifInUcastPkts; /*!< counter of ingress packets */
+ __u32 ifOutUcastPkts; /*!< counter of egress packets */
+ __u32 ifInErrors; /*!< counter of error ingress packets */
+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */
+ __u32 ifOutErros; /*!< counter of error egress packets */
+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */
+} atm_aal5_ifEntry_t;
+
+/*!
+ \struct atm_aal5_vcc_t
+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
+
+ This structure is a part of structure "atm_aal5_vcc_x_t".
+ */
+typedef struct {
+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
+} atm_aal5_vcc_t;
+
+/*!
+ \struct atm_aal5_vcc_x_t
+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
+
+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
+ */
+typedef struct {
+ int vpi; /*!< VPI of the VCC to get MIB counters */
+ int vci; /*!< VCI of the VCC to get MIB counters */
+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
+} atm_aal5_vcc_x_t;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ * IOCTL
+ * ####################################
+ */
+
+/*!
+ \addtogroup IFX_ATM_IOCTL
+ */
+/*@{*/
+
+/*
+ * ioctl Command
+ */
+/*!
+ \brief ATM IOCTL Magic Number
+ */
+#define PPE_ATM_IOC_MAGIC 'o'
+/*!
+ \brief ATM IOCTL Command - Get Cell Level MIB Counters
+
+ This command is obsolete. User can get cell level MIB from DSL API.
+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
+/*!
+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
+
+ Get AAL5 packet counters.
+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
+ */
+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
+/*!
+ \brief ATM IOCTL Command - Get Per PVC MIB Counters
+
+ Get AAL5 packet counters for each PVC.
+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
+ */
+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
+/*!
+ \brief Total Number of ATM IOCTL Commands
+ */
+#define PPE_ATM_IOC_MAXNR 3
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ * API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+ unsigned int port_num;
+ unsigned int tx_link_rate[2];
+};
+#endif
+
+
+
+#endif // IFX_ATM_H
+
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
new file mode 100644
index 0000000..698e5c3
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
@@ -0,0 +1,203 @@
+/******************************************************************************
+**
+** FILE NAME : ifx_ptm.h
+** PROJECT : UEIP
+** MODULES : PTM
+**
+** DATE : 17 Jun 2009
+** AUTHOR : Xu Liang
+** DESCRIPTION : Global PTM driver header file
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Date $Author $Comment
+** 07 JUL 2009 Xu Liang Init Version
+*******************************************************************************/
+
+#ifndef IFX_PTM_H
+#define IFX_PTM_H
+
+
+
+/*!
+ \defgroup IFX_PTM UEIP Project - PTM driver module
+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
+ */
+
+/*!
+ \defgroup IFX_PTM_IOCTL IOCTL Commands
+ \ingroup IFX_PTM
+ \brief IOCTL Commands used by user application.
+ */
+
+/*!
+ \defgroup IFX_PTM_STRUCT Structures
+ \ingroup IFX_PTM
+ \brief Structures used by user application.
+ */
+
+/*!
+ \file ifx_ptm.h
+ \ingroup IFX_PTM
+ \brief PTM driver header file
+ */
+
+
+
+/*
+ * ####################################
+ * Definition
+ * ####################################
+ */
+
+
+
+/*
+ * ####################################
+ * IOCTL
+ * ####################################
+ */
+
+/*!
+ \addtogroup IFX_PTM_IOCTL
+ */
+/*@{*/
+
+/*
+ * ioctl Command
+ */
+/*!
+ \brief PTM IOCTL Command - Get codeword MIB counters.
+
+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
+ */
+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
+/*!
+ \brief PTM IOCTL Command - Get packet MIB counters.
+
+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
+ */
+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
+/*!
+ \brief PTM IOCTL Command - Get firmware configuration (CRC).
+
+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
+ */
+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
+/*!
+ \brief PTM IOCTL Command - Set firmware configuration (CRC).
+
+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
+ */
+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
+/*!
+ \brief PTM IOCTL Command - Program priority value to TX queue mapping.
+
+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
+ */
+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
+
+/*@}*/
+
+
+/*!
+ \addtogroup IFX_PTM_STRUCT
+ */
+/*@{*/
+
+/*
+ * ioctl Data Type
+ */
+
+/*!
+ \typedef PTM_CW_IF_ENTRY_T
+ \brief Wrapping of structure "ptm_cw_ifEntry_t".
+ */
+/*!
+ \struct ptm_cw_ifEntry_t
+ \brief Structure used for CodeWord level MIB counters.
+ */
+typedef struct ptm_cw_ifEntry_t {
+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
+} PTM_CW_IF_ENTRY_T;
+
+/*!
+ \typedef PTM_FRAME_MIB_T
+ \brief Wrapping of structure "ptm_frame_mib_t".
+ */
+/*!
+ \struct ptm_frame_mib_t
+ \brief Structure used for packet level MIB counters.
+ */
+typedef struct ptm_frame_mib_t {
+ uint32_t RxCorrect; /*!< output, number of ingress packet */
+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */
+ uint32_t TxSend; /*!< output, number of egress packet */
+} PTM_FRAME_MIB_T;
+
+/*!
+ \typedef IFX_PTM_CFG_T
+ \brief Wrapping of structure "ptm_cfg_t".
+ */
+/*!
+ \struct ptm_cfg_t
+ \brief Structure used for ETH/TC CRC configuration.
+ */
+typedef struct ptm_cfg_t {
+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
+} IFX_PTM_CFG_T;
+
+/*!
+ \typedef IFX_PTM_PRIO_Q_MAP_T
+ \brief Wrapping of structure "ppe_prio_q_map".
+ */
+/*!
+ \struct ppe_prio_q_map
+ \brief Structure used for Priority Value to TX Queue mapping.
+ */
+typedef struct ppe_prio_q_map {
+ int pkt_prio;
+ int qid;
+ int vpi; // ignored in eth interface
+ int vci; // ignored in eth interface
+} IFX_PTM_PRIO_Q_MAP_T;
+
+/*@}*/
+
+
+
+/*
+ * ####################################
+ * API
+ * ####################################
+ */
+
+#ifdef __KERNEL__
+struct port_cell_info {
+ unsigned int port_num;
+ unsigned int tx_link_rate[2];
+};
+#endif
+
+
+
+#endif // IFX_PTM_H
+
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 85685e1..6b94cc7 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -14,6 +14,7 @@
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/module.h>
#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>
@@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
ltq_icu_w32(im, BIT(offset), isr);
}
+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
static void ltq_ack_irq(struct irq_data *d)
{
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index fde7e56..e5bd72f 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -57,6 +57,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
EXPORT_SYMBOL(_dma_cache_wback_inv);
+EXPORT_SYMBOL(_dma_cache_wback);
+EXPORT_SYMBOL(_dma_cache_inv);
#endif /* CONFIG_DMA_NONCOHERENT */
diff --git a/include/uapi/linux/atm.h b/include/uapi/linux/atm.h
index 88399db..78c8bbc 100644
--- a/include/uapi/linux/atm.h
+++ b/include/uapi/linux/atm.h
@@ -130,8 +130,14 @@
#define ATM_ABR 4
#define ATM_ANYCLASS 5 /* compatible with everything */
+#define ATM_VBR_NRT ATM_VBR
+#define ATM_VBR_RT 6
+#define ATM_UBR_PLUS 7
+#define ATM_GFR 8
+
#define ATM_MAX_PCR -1 /* maximum available PCR */
+
struct atm_trafprm {
unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
int max_pcr; /* maximum PCR in cells per second */
diff --git a/net/atm/common.c b/net/atm/common.c
index 7b49100..d2af929 100644
--- a/net/atm/common.c
+++ b/net/atm/common.c
@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct sock *sk)
write_unlock_irq(&vcc_sklist_lock);
}
+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
+EXPORT_SYMBOL(ifx_atm_alloc_tx);
+
static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
{
struct sk_buff *skb;
struct sock *sk = sk_atm(vcc);
+ if (ifx_atm_alloc_tx != NULL)
+ return ifx_atm_alloc_tx(vcc, size);
+
if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
diff --git a/net/atm/proc.c b/net/atm/proc.c
index bbb6461..ecb584a 100644
--- a/net/atm/proc.c
+++ b/net/atm/proc.c
@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
{
static const char *const class_name[] = {
- "off", "UBR", "CBR", "VBR", "ABR"};
+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
static const char *const aal_name[] = {
"---", "1", "2", "3/4", /* 0- 3 */
"???", "5", "???", "???", /* 4- 7 */
--
1.7.10.4

95
target/linux/lantiq/patches-3.14/0005-MIPS-lantiq-add-reset-controller-api-support.patch Normal file
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@ -0,0 +1,95 @@
From 223f1c46e109a8420765aee099a5d1dc4ab7ee98 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 3 Sep 2013 13:18:12 +0200
Subject: [PATCH 05/31] MIPS: lantiq: add reset-controller api support
Add a reset-controller binding for the reset registers found on the lantiq
SoC.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/reset.c | 61 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 1fa0f17..a1e06b7 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -14,6 +14,7 @@
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/reset-controller.h>
#include <asm/reboot.h>
@@ -113,6 +114,66 @@ void ltq_reset_once(unsigned int module, ulong u)
ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
}
+static int ltq_assert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ u32 val;
+
+ if (id < 8)
+ return -1;
+
+ val = ltq_rcu_r32(RCU_RST_REQ);
+ val |= BIT(id);
+ ltq_rcu_w32(val, RCU_RST_REQ);
+
+ return 0;
+}
+
+static int ltq_deassert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ u32 val;
+
+ if (id < 8)
+ return -1;
+
+ val = ltq_rcu_r32(RCU_RST_REQ);
+ val &= ~BIT(id);
+ ltq_rcu_w32(val, RCU_RST_REQ);
+
+ return 0;
+}
+
+static int ltq_reset_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ ltq_assert_device(rcdev, id);
+ return ltq_deassert_device(rcdev, id);
+}
+
+static struct reset_control_ops reset_ops = {
+ .reset = ltq_reset_device,
+ .assert = ltq_assert_device,
+ .deassert = ltq_deassert_device,
+};
+
+static struct reset_controller_dev reset_dev = {
+ .ops = &reset_ops,
+ .owner = THIS_MODULE,
+ .nr_resets = 32,
+ .of_reset_n_cells = 1,
+};
+
+void ltq_rst_init(void)
+{
+ reset_dev.of_node = of_find_compatible_node(NULL, NULL,
+ "lantiq,xway-reset");
+ if (!reset_dev.of_node)
+ pr_err("Failed to find reset controller node");
+ else
+ reset_controller_register(&reset_dev);
+}
+
static void ltq_machine_restart(char *command)
{
local_irq_disable();
--
1.7.10.4

34
target/linux/lantiq/patches-3.14/0006-MIPS-lantiq-reboot-gphy-on-restart.patch Normal file
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@ -0,0 +1,34 @@
From f81979f4b297693ac70616feaa4a79bdcb11db35 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:55:57 +0200
Subject: [PATCH 06/31] MIPS: lantiq: reboot gphy on restart
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/reset.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index a1e06b7..fe68f9a 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -176,8 +176,15 @@ void ltq_rst_init(void)
static void ltq_machine_restart(char *command)
{
+ u32 val = ltq_rcu_r32(RCU_RST_REQ);
+
+ if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
+ val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
+
+ val |= RCU_RD_SRST;
+
local_irq_disable();
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
+ ltq_rcu_w32(val, RCU_RST_REQ);
unreachable();
}
--
1.7.10.4

119
target/linux/lantiq/patches-3.14/0007-MIPS-lantiq-add-basic-tffs-driver.patch Normal file
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@ -0,0 +1,119 @@
From d27ec8bb97db0f60d81ab255d51ac4e967362067 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:34:19 +0200
Subject: [PATCH 07/31] MIPS: lantiq: add basic tffs driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/Makefile | 2 +-
arch/mips/lantiq/xway/tffs.c | 87 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 88 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/lantiq/xway/tffs.c
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index a2edc53..c73d3f2 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,5 +1,5 @@
obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
-obj-y += vmmc.o
+obj-y += vmmc.o tffs.o
obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/tffs.c b/arch/mips/lantiq/xway/tffs.c
new file mode 100644
index 0000000..c9c6e19
--- /dev/null
+++ b/arch/mips/lantiq/xway/tffs.c
@@ -0,0 +1,87 @@
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+
+struct tffs_entry {
+ uint16_t id;
+ uint16_t len;
+};
+
+static struct tffs_id {
+ uint32_t id;
+ char *name;
+ unsigned char *val;
+ uint32_t offset;
+ uint32_t len;
+} ids[] = {
+ { 0x01A9, "annex" },
+ { 0x0188, "maca" },
+ { 0x0189, "macb" },
+ { 0x018a, "macwlan" },
+ { 0x0195, "macwlan2" },
+ { 0x018b, "macdsl" },
+ { 0x01C2, "webgui_pass" },
+ { 0x01AB, "wlan_key" },
+};
+
+static struct mtd_info *tffs1, *tffs2;
+
+static struct tffs_id* tffs_find_id(int id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ if (id == ids[i].id)
+ return &ids[i];
+
+ return NULL;
+}
+
+static void tffs_index(void)
+{
+ struct tffs_entry *E = NULL;
+ struct tffs_entry entry;
+ int ret, retlen;
+
+ while ((unsigned int) E + sizeof(struct tffs_entry) < tffs2->size) {
+ struct tffs_id *id;
+ int len;
+
+ ret = mtd_read(tffs2, (unsigned int) E, sizeof(struct tffs_entry), &retlen, (unsigned char *)&entry);
+ if (ret)
+ return;
+
+ if (entry.id == 0xffff)
+ return;
+
+ id = tffs_find_id(entry.id);
+ if (id) {
+ id->offset = (uint32_t) E;
+ id->len = entry.len;
+ id->val = kzalloc(entry.len + 1, GFP_KERNEL);
+ mtd_read(tffs2, ((unsigned int) E) + sizeof(struct tffs_entry), entry.len, &retlen, id->val);
+
+ }
+ //printk(KERN_INFO "found entry at 0x%08X-> [<0x%x> %u bytes]\n", (uint32_t) E, entry.id, entry.len);
+ if (id && id->name)
+ printk(KERN_INFO "found entry name -> %s=%s\n", id->name, id->val);
+
+ len = (entry.len + 3) & ~0x03;
+ E = (struct tffs_entry *)(((unsigned int)E) + sizeof(struct tffs_entry) + len);
+ }
+}
+
+static int __init tffs_init(void)
+{
+ tffs1 = get_mtd_device_nm("tffs (1)");
+ tffs2 = get_mtd_device_nm("tffs (2)");
+ if (IS_ERR(tffs1) || IS_ERR(tffs2))
+ return -1;
+
+ tffs_index();
+
+ return 0;
+}
+late_initcall(tffs_init);
+
--
1.7.10.4

1039
target/linux/lantiq/patches-3.14/0008-MIPS-lantiq-backport-old-timer-code.patch Normal file
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File diff suppressed because it is too large Load Diff

84
target/linux/lantiq/patches-3.14/0009-pinctrl-lantiq-fix-up-pinmux.patch Normal file
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@ -0,0 +1,84 @@
From 29452de974f2cdc87876dbdc18a16405ef80c05f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 9 Aug 2013 20:38:15 +0200
Subject: [PATCH 09/31] pinctrl/lantiq: fix up pinmux
We found out how to set the gphy led pinmuxing.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/pinctrl/pinctrl-xway.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index e66f4ca..b5f43c8 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -609,10 +609,9 @@ static struct pinctrl_desc xway_pctrl_desc = {
.confops = &xway_pinconf_ops,
};
-static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
+static int mux_apply(struct ltq_pinmux_info *info,
int pin, int mux)
{
- struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
int port = PORT(pin);
u32 alt1_reg = GPIO_ALT1(pin);
@@ -632,6 +631,14 @@ static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
return 0;
}
+static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
+ int pin, int mux)
+{
+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
+
+ return mux_apply(info, pin, mux);
+}
+
static const struct ltq_cfg_param xway_cfg_params[] = {
{"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
{"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
@@ -676,6 +683,10 @@ static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
{
struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
+ if (PORT(pin) == PORT3)
+ gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
+ else
+ gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
xway_gpio_set(chip, pin, val);
@@ -696,6 +707,18 @@ static void xway_gpio_free(struct gpio_chip *chip, unsigned offset)
pinctrl_free_gpio(gpio);
}
+static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
+ int i;
+
+ for (i = 0; i < info->num_exin; i++)
+ if (info->exin[i] == offset)
+ return ltq_eiu_get_irq(i);
+
+ return -1;
+}
+
static struct gpio_chip xway_chip = {
.label = "gpio-xway",
.direction_input = xway_gpio_dir_in,
@@ -704,6 +727,7 @@ static struct gpio_chip xway_chip = {
.set = xway_gpio_set,
.request = xway_gpio_req,
.free = xway_gpio_free,
+ .to_irq = xway_gpio_to_irq,
.base = -1,
};
--
1.7.10.4

606
target/linux/lantiq/patches-3.14/0010-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch Normal file
View File

@ -0,0 +1,606 @@
From 9f921445b6dbf2beef397c6aa038db135e92eb80 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 13 Mar 2013 10:02:58 +0100
Subject: [PATCH 10/31] owrt: lantiq: wifi and ethernet eeprom handling
---
arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h | 6 +
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
arch/mips/lantiq/xway/Makefile | 3 +
arch/mips/lantiq/xway/ath_eep.c | 277 ++++++++++++++++++++
arch/mips/lantiq/xway/eth_mac.c | 76 ++++++
arch/mips/lantiq/xway/pci-ath-fixup.c | 109 ++++++++
arch/mips/lantiq/xway/rt_eep.c | 60 +++++
7 files changed, 534 insertions(+)
create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
create mode 100644 arch/mips/lantiq/xway/ath_eep.c
create mode 100644 arch/mips/lantiq/xway/eth_mac.c
create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c
create mode 100644 arch/mips/lantiq/xway/rt_eep.c
diff --git a/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
new file mode 100644
index 0000000..095d261
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h
@@ -0,0 +1,6 @@
+#ifndef _PCI_ATH_FIXUP
+#define _PCI_ATH_FIXUP
+
+void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init;
+
+#endif /* _PCI_ATH_FIXUP */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 133336b..779715c 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -90,5 +90,8 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
+/* allow the ethernet driver to load a flash mapped mac addr */
+const u8* ltq_get_eth_mac(void);
+
#endif /* CONFIG_SOC_TYPE_XWAY */
#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 2dd442c..de876e1 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -2,4 +2,7 @@ obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o
obj-y += vmmc.o tffs.o
+obj-y += eth_mac.o
+obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o
+
obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/ath_eep.c b/arch/mips/lantiq/xway/ath_eep.c
new file mode 100644
index 0000000..cd07f9a
--- /dev/null
+++ b/arch/mips/lantiq/xway/ath_eep.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
+ * Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/etherdevice.h>
+#include <linux/ath5k_platform.h>
+#include <linux/ath9k_platform.h>
+#include <linux/pci.h>
+#include <linux/err.h>
+#include <linux/mtd/mtd.h>
+#include <pci-ath-fixup.h>
+#include <lantiq_soc.h>
+
+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
+struct ath5k_platform_data ath5k_pdata;
+struct ath9k_platform_data ath9k_pdata = {
+ .led_pin = -1,
+};
+static u8 athxk_eeprom_mac[6];
+
+static int ath9k_pci_plat_dev_init(struct pci_dev *dev)
+{
+ dev->dev.platform_data = &ath9k_pdata;
+ return 0;
+}
+
+static int ath9k_eep_load;
+int __init of_ath9k_eeprom_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node, *mtd_np;
+ struct resource *eep_res, *mac_res = NULL;
+ void __iomem *eep, *mac;
+ int mac_offset;
+ u32 mac_inc = 0, pci_slot = 0;
+ int i;
+ struct mtd_info *the_mtd;
+ size_t flash_readlen;
+ const __be32 *list;
+ const char *part;
+ phandle phandle;
+
+ if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 *
+ sizeof(*list) && (phandle = be32_to_cpup(list++)) &&
+ (mtd_np = of_find_node_by_phandle(phandle)) && ((part =
+ of_get_property(mtd_np, "label", NULL)) || (part =
+ mtd_np->name)) && (the_mtd = get_mtd_device_nm(part))
+ != ERR_PTR(-ENODEV)) {
+ i = mtd_read(the_mtd, be32_to_cpup(list),
+ ATH9K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen,
+ (void *) ath9k_pdata.eeprom_data);
+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
+ size_t mac_readlen;
+ mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
+ (void *) athxk_eeprom_mac);
+ }
+ put_mtd_device(the_mtd);
+ if ((sizeof(ath9k_pdata.eeprom_data) != flash_readlen) || i) {
+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
+ return -ENODEV;
+ }
+ } else {
+ eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+ if (!eep_res) {
+ dev_err(&pdev->dev, "failed to load eeprom address\n");
+ return -ENODEV;
+ }
+ if (resource_size(eep_res) != ATH9K_PLAT_EEP_MAX_WORDS << 1) {
+ dev_err(&pdev->dev, "eeprom has an invalid size\n");
+ return -EINVAL;
+ }
+
+ eep = ioremap(eep_res->start, resource_size(eep_res));
+ memcpy_fromio(ath9k_pdata.eeprom_data, eep,
+ ATH9K_PLAT_EEP_MAX_WORDS << 1);
+ }
+
+ if (of_find_property(np, "ath,eep-swap", NULL))
+ for (i = 0; i < ATH9K_PLAT_EEP_MAX_WORDS; i++)
+ ath9k_pdata.eeprom_data[i] = swab16(ath9k_pdata.eeprom_data[i]);
+
+ if (of_find_property(np, "ath,eep-endian", NULL)) {
+ ath9k_pdata.endian_check = true;
+
+ dev_info(&pdev->dev, "endian check enabled.\n");
+ }
+
+ if (!is_valid_ether_addr(athxk_eeprom_mac)) {
+ if (mac_res) {
+ if (resource_size(mac_res) != 6) {
+ dev_err(&pdev->dev, "mac has an invalid size\n");
+ return -EINVAL;
+ }
+ mac = ioremap(mac_res->start, resource_size(mac_res));
+ memcpy_fromio(athxk_eeprom_mac, mac, 6);
+ } else if (ltq_get_eth_mac()) {
+ memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6);
+ }
+ }
+ if (!is_valid_ether_addr(athxk_eeprom_mac)) {
+ dev_warn(&pdev->dev, "using random mac\n");
+ random_ether_addr(athxk_eeprom_mac);
+ }
+
+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
+ athxk_eeprom_mac[5] += mac_inc;
+
+ ath9k_pdata.macaddr = athxk_eeprom_mac;
+ ltq_pci_plat_dev_init = ath9k_pci_plat_dev_init;
+
+ if (!of_property_read_u32(np, "ath,pci-slot", &pci_slot)) {
+ ltq_pci_ath_fixup(pci_slot, ath9k_pdata.eeprom_data);
+
+ dev_info(&pdev->dev, "pci slot: %u\n", pci_slot);
+ if (ath9k_eep_load) {
+ struct pci_dev *d = NULL;
+ while ((d = pci_get_device(PCI_VENDOR_ID_ATHEROS,
+ PCI_ANY_ID, d)) != NULL)
+ pci_fixup_device(pci_fixup_early, d);
+ }
+
+ }
+
+ dev_info(&pdev->dev, "loaded ath9k eeprom\n");
+
+ return 0;
+}
+
+static struct of_device_id ath9k_eeprom_ids[] = {
+ { .compatible = "ath9k,eeprom" },
+ { }
+};
+
+static struct platform_driver ath9k_eeprom_driver = {
+ .driver = {
+ .name = "ath9k,eeprom",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(ath9k_eeprom_ids),
+ },
+};
+
+static int __init of_ath9k_eeprom_init(void)
+{
+ int ret = platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
+
+ if (ret)
+ ath9k_eep_load = 1;
+
+ return ret;
+}
+
+static int __init of_ath9k_eeprom_init_late(void)
+{
+ if (!ath9k_eep_load)
+ return 0;
+ return platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe);
+}
+late_initcall(of_ath9k_eeprom_init_late);
+subsys_initcall(of_ath9k_eeprom_init);
+
+
+static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
+{
+ dev->dev.platform_data = &ath5k_pdata;
+ return 0;
+}
+
+int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node, *mtd_np;
+ struct resource *eep_res, *mac_res = NULL;
+ void __iomem *eep, *mac;
+ int mac_offset;
+ u32 mac_inc = 0;
+ int i;
+ struct mtd_info *the_mtd;
+ size_t flash_readlen;
+ const __be32 *list;
+ const char *part;
+ phandle phandle;
+
+ if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 *
+ sizeof(*list) && (phandle = be32_to_cpup(list++)) &&
+ (mtd_np = of_find_node_by_phandle(phandle)) && ((part =
+ of_get_property(mtd_np, "label", NULL)) || (part =
+ mtd_np->name)) && (the_mtd = get_mtd_device_nm(part))
+ != ERR_PTR(-ENODEV)) {
+ i = mtd_read(the_mtd, be32_to_cpup(list),
+ ATH5K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen,
+ (void *) ath5k_pdata.eeprom_data);
+ put_mtd_device(the_mtd);
+ if ((sizeof(ATH5K_PLAT_EEP_MAX_WORDS << 1) != flash_readlen)
+ || i) {
+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
+ return -ENODEV;
+ }
+ } else {
+ eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+ if (!eep_res) {
+ dev_err(&pdev->dev, "failed to load eeprom address\n");
+ return -ENODEV;
+ }
+ if (resource_size(eep_res) != ATH5K_PLAT_EEP_MAX_WORDS << 1) {
+ dev_err(&pdev->dev, "eeprom has an invalid size\n");
+ return -EINVAL;
+ }
+
+ eep = ioremap(eep_res->start, resource_size(eep_res));
+ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1,
+ GFP_KERNEL);
+ memcpy_fromio(ath5k_pdata.eeprom_data, eep,
+ ATH5K_PLAT_EEP_MAX_WORDS << 1);
+ }
+
+ if (of_find_property(np, "ath,eep-swap", NULL))
+ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
+ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
+
+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
+ memcpy_fromio(athxk_eeprom_mac, (void*) ath5k_pdata.eeprom_data + mac_offset, 6);
+ } else if (mac_res) {
+ if (resource_size(mac_res) != 6) {
+ dev_err(&pdev->dev, "mac has an invalid size\n");
+ return -EINVAL;
+ }
+ mac = ioremap(mac_res->start, resource_size(mac_res));
+ memcpy_fromio(athxk_eeprom_mac, mac, 6);
+ } else if (ltq_get_eth_mac())
+ memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6);
+ else {
+ dev_warn(&pdev->dev, "using random mac\n");
+ random_ether_addr(athxk_eeprom_mac);
+ }
+
+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
+ athxk_eeprom_mac[5] += mac_inc;
+
+ ath5k_pdata.macaddr = athxk_eeprom_mac;
+ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
+
+ dev_info(&pdev->dev, "loaded ath5k eeprom\n");
+
+ return 0;
+}
+
+static struct of_device_id ath5k_eeprom_ids[] = {
+ { .compatible = "ath5k,eeprom" },
+ { }
+};
+
+static struct platform_driver ath5k_eeprom_driver = {
+ .driver = {
+ .name = "ath5k,eeprom",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(ath5k_eeprom_ids),
+ },
+};
+
+static int __init of_ath5k_eeprom_init(void)
+{
+ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
+}
+device_initcall(of_ath5k_eeprom_init);
diff --git a/arch/mips/lantiq/xway/eth_mac.c b/arch/mips/lantiq/xway/eth_mac.c
new file mode 100644
index 0000000..d288a0e
--- /dev/null
+++ b/arch/mips/lantiq/xway/eth_mac.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/if_ether.h>
+
+static u8 eth_mac[6];
+static int eth_mac_set;
+
+const u8* ltq_get_eth_mac(void)
+{
+ return eth_mac;
+}
+
+static int __init setup_ethaddr(char *str)
+{
+ eth_mac_set = mac_pton(str, eth_mac);
+ return !eth_mac_set;
+}
+__setup("ethaddr=", setup_ethaddr);
+
+int __init of_eth_mac_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct resource *mac_res;
+ void __iomem *mac;
+ u32 mac_inc = 0;
+
+ if (eth_mac_set) {
+ dev_err(&pdev->dev, "mac was already set by bootloader\n");
+ return -EINVAL;
+ }
+ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ if (!mac_res) {
+ dev_err(&pdev->dev, "failed to load mac\n");
+ return -EINVAL;
+ }
+ if (resource_size(mac_res) != 6) {
+ dev_err(&pdev->dev, "mac has an invalid size\n");
+ return -EINVAL;
+ }
+ mac = ioremap(mac_res->start, resource_size(mac_res));
+ memcpy_fromio(eth_mac, mac, 6);
+
+ if (!of_property_read_u32(np, "mac-increment", &mac_inc))
+ eth_mac[5] += mac_inc;
+
+ return 0;
+}
+
+static struct of_device_id eth_mac_ids[] = {
+ { .compatible = "lantiq,eth-mac" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver eth_mac_driver = {
+ .driver = {
+ .name = "lantiq,eth-mac",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(eth_mac_ids),
+ },
+};
+
+static int __init of_eth_mac_init(void)
+{
+ return platform_driver_probe(&eth_mac_driver, of_eth_mac_probe);
+}
+device_initcall(of_eth_mac_init);
diff --git a/arch/mips/lantiq/xway/pci-ath-fixup.c b/arch/mips/lantiq/xway/pci-ath-fixup.c
new file mode 100644
index 0000000..c87ffb2
--- /dev/null
+++ b/arch/mips/lantiq/xway/pci-ath-fixup.c
@@ -0,0 +1,109 @@
+/*
+ * Atheros AP94 reference board PCI initialization
+ *
+ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <lantiq_soc.h>
+
+#define LTQ_PCI_MEM_BASE 0x18000000
+
+struct ath_fixup {
+ u16 *cal_data;
+ unsigned slot;
+};
+
+static int ath_num_fixups;
+static struct ath_fixup ath_fixups[2];
+
+static void ath_pci_fixup(struct pci_dev *dev)
+{
+ void __iomem *mem;
+ u16 *cal_data = NULL;
+ u16 cmd;
+ u32 bar0;
+ u32 val;
+ unsigned i;
+
+ for (i = 0; i < ath_num_fixups; i++) {
+ if (ath_fixups[i].cal_data == NULL)
+ continue;
+
+ if (ath_fixups[i].slot != PCI_SLOT(dev->devfn))
+ continue;
+
+ cal_data = ath_fixups[i].cal_data;
+ break;
+ }
+
+ if (cal_data == NULL)
+ return;
+
+ if (*cal_data != 0xa55a) {
+ pr_err("pci %s: invalid calibration data\n", pci_name(dev));
+ return;
+ }
+
+ pr_info("pci %s: fixup device configuration\n", pci_name(dev));
+
+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
+ if (!mem) {
+ pr_err("pci %s: ioremap error\n", pci_name(dev));
+ return;
+ }
+
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+ /* set pointer to first reg address */
+ cal_data += 3;
+ while (*cal_data != 0xffff) {
+ u32 reg;
+ reg = *cal_data++;
+ val = *cal_data++;
+ val |= (*cal_data++) << 16;
+
+ ltq_w32(swab32(val), mem + reg);
+ udelay(100);
+ }
+
+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
+ dev->vendor = val & 0xffff;
+ dev->device = (val >> 16) & 0xffff;
+
+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
+ dev->revision = val & 0xff;
+ dev->class = val >> 8; /* upper 3 bytes */
+
+ pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n",
+ pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class);
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
+
+ iounmap(mem);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup);
+
+void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data)
+{
+ if (ath_num_fixups >= ARRAY_SIZE(ath_fixups))
+ return;
+
+ ath_fixups[ath_num_fixups].slot = slot;
+ ath_fixups[ath_num_fixups].cal_data = cal_data;
+ ath_num_fixups++;
+}
diff --git a/arch/mips/lantiq/xway/rt_eep.c b/arch/mips/lantiq/xway/rt_eep.c
new file mode 100644
index 0000000..00f2d4c
--- /dev/null
+++ b/arch/mips/lantiq/xway/rt_eep.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/rt2x00_platform.h>
+
+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
+static struct rt2x00_platform_data rt2x00_pdata;
+
+static int rt2x00_pci_plat_dev_init(struct pci_dev *dev)
+{
+ dev->dev.platform_data = &rt2x00_pdata;
+ return 0;
+}
+
+int __init of_ralink_eeprom_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const char *eeprom;
+
+ if (of_property_read_string(np, "ralink,eeprom", &eeprom)) {
+ dev_err(&pdev->dev, "failed to load eeprom filename\n");
+ return 0;
+ }
+
+ rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL);
+// rt2x00_pdata.mac_address = mac;
+ ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init;
+
+ dev_info(&pdev->dev, "using %s as eeprom\n", eeprom);
+
+ return 0;
+}
+
+static struct of_device_id ralink_eeprom_ids[] = {
+ { .compatible = "ralink,eeprom" },
+ { }
+};
+
+static struct platform_driver ralink_eeprom_driver = {
+ .driver = {
+ .name = "ralink,eeprom",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(ralink_eeprom_ids),
+ },
+};
+
+static int __init of_ralink_eeprom_init(void)
+{
+ return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe);
+}
+device_initcall(of_ralink_eeprom_init);
--
1.7.10.4

27
target/linux/lantiq/patches-3.14/0011-owrt-generic-dtb-image-hack.patch Normal file
View File

@ -0,0 +1,27 @@
From 572e107a37deb7bc8512ca9144f4e8f24b36e451 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:32:12 +0200
Subject: [PATCH 11/31] owrt: generic dtb image hack
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/kernel/head.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 7b6a5b3..78518b8 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -101,6 +101,9 @@ FEXPORT(__kernel_entry)
j kernel_entry
#endif
+ .ascii "OWRTDTB:"
+ EXPORT(__image_dtb)
+ .fill 0x4000
__REF
NESTED(kernel_entry, 16, sp) # kernel entry point
--
1.7.10.4

30
target/linux/lantiq/patches-3.14/0012-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch Normal file
View File

@ -0,0 +1,30 @@
From 6c476b89f3d685b41f2e216698fc8c90ddb11dfd Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:18:00 +0200
Subject: [PATCH 12/31] MTD: lantiq: handle NO_XIP on cfi0001 flash
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/maps/lantiq-flash.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 93c507a..710d699 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -140,7 +140,11 @@ ltq_mtd_probe(struct platform_device *pdev)
if (!ltq_mtd->map)
return -ENOMEM;
- ltq_mtd->map->phys = ltq_mtd->res->start;
+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
+ ltq_mtd->map->phys = NO_XIP;
+ else
+ ltq_mtd->map->phys = ltq_mtd->res->start;
+ ltq_mtd->res->start;
ltq_mtd->map->size = resource_size(ltq_mtd->res);
ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
if (IS_ERR(ltq_mtd->map->virt))
--
1.7.10.4

29
target/linux/lantiq/patches-3.14/0013-MTD-lantiq-xway-fix-invalid-operator.patch Normal file
View File

@ -0,0 +1,29 @@
From c243da18ea2a02e8cfb3f821232783376131948a Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 18:03:54 +0200
Subject: [PATCH 13/31] MTD: lantiq: xway: fix invalid operator
xway_read_byte should use a logic or and not an add operator when working out
the nand address.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
index 3f81dc8..169a91d 100644
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -124,7 +124,7 @@ static unsigned char xway_read_byte(struct mtd_info *mtd)
int ret;
spin_lock_irqsave(&ebu_lock, flags);
- ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
+ ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
spin_unlock_irqrestore(&ebu_lock, flags);
return ret;
--
1.7.10.4

49
target/linux/lantiq/patches-3.14/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch Normal file
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@ -0,0 +1,49 @@
From b2ef79004dd8e26f3a4625610bff5362b70e956b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 18:06:39 +0200
Subject: [PATCH 14/31] MTD: lantiq: xway: the latched command should be
persistent
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
index 169a91d..7f2bdd1 100644
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -54,6 +54,8 @@
#define NAND_CON_CSMUX (1 << 1)
#define NAND_CON_NANDM 1
+static u32 xway_latchcmd;
+
static void xway_reset_chip(struct nand_chip *chip)
{
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
unsigned long flags;
if (ctrl & NAND_CTRL_CHANGE) {
- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
if (ctrl & NAND_CLE)
- nandaddr |= NAND_WRITE_CMD;
- else
- nandaddr |= NAND_WRITE_ADDR;
- this->IO_ADDR_W = (void __iomem *) nandaddr;
+ xway_latchcmd = NAND_WRITE_CMD;
+ else if (ctrl & NAND_ALE)
+ xway_latchcmd = NAND_WRITE_ADDR;
}
if (cmd != NAND_CMD_NONE) {
spin_lock_irqsave(&ebu_lock, flags);
- writeb(cmd, this->IO_ADDR_W);
+ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
spin_unlock_irqrestore(&ebu_lock, flags);
--
1.7.10.4

46
target/linux/lantiq/patches-3.14/0015-MTD-lantiq-xway-remove-endless-loop.patch Normal file
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@ -0,0 +1,46 @@
From 836c433cec22555d81bf02bb205dee5772b8df08 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 18:02:06 +0200
Subject: [PATCH 15/31] MTD: lantiq: xway: remove endless loop
The reset loop logic could run into a endless loop. Lets fix it as requested.
--> http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
index 7f2bdd1..8d14f1b 100644
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -59,16 +59,22 @@ static u32 xway_latchcmd;
static void xway_reset_chip(struct nand_chip *chip)
{
unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
+ unsigned long timeout;
unsigned long flags;
nandaddr &= ~NAND_WRITE_ADDR;
nandaddr |= NAND_WRITE_CMD;
/* finish with a reset */
+ timeout = jiffies + msecs_to_jiffies(20);
+
spin_lock_irqsave(&ebu_lock, flags);
writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
- ;
+ do {
+ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ break;
+ cond_resched();
+ } while (!time_after_eq(jiffies, timeout));
spin_unlock_irqrestore(&ebu_lock, flags);
}
--
1.7.10.4

60
target/linux/lantiq/patches-3.14/0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch Normal file
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@ -0,0 +1,60 @@
From 6f5bf300afa3c6f41a973fb3f39827db59512343 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 28 Jul 2013 17:59:51 +0200
Subject: [PATCH 16/31] MTD: lantiq: xway: add missing write_buf and read_buf
to nand driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
index 8d14f1b..f813a55 100644
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -136,6 +136,32 @@ static unsigned char xway_read_byte(struct mtd_info *mtd)
return ret;
}
+static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&ebu_lock, flags);
+ for (i = 0; i < len; i++)
+ buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
+ spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&ebu_lock, flags);
+ for (i = 0; i < len; i++)
+ ltq_w8(buf[i], (void __iomem *)nandaddr);
+ spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
static int xway_nand_probe(struct platform_device *pdev)
{
struct nand_chip *this = platform_get_drvdata(pdev);
@@ -181,6 +207,8 @@ static struct platform_nand_data xway_nand_data = {
.dev_ready = xway_dev_ready,
.select_chip = xway_select_chip,
.read_byte = xway_read_byte,
+ .read_buf = xway_read_buf,
+ .write_buf = xway_write_buf,
}
};
--
1.7.10.4

94
target/linux/lantiq/patches-3.14/0017-MTD-xway-fix-nand-locking.patch Normal file
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@ -0,0 +1,94 @@
From bbaf5aaf4b430f2139e5f561b6372008d26766a2 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:55:31 +0200
Subject: [PATCH 17/31] MTD: xway: fix nand locking
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/xway_nand.c | 15 +++------------
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
index f813a55..e430f2d 100644
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -80,13 +80,16 @@ static void xway_reset_chip(struct nand_chip *chip)
static void xway_select_chip(struct mtd_info *mtd, int chip)
{
+ static unsigned long csflags;
switch (chip) {
case -1:
ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
+ spin_unlock_irqrestore(&ebu_lock, csflags);
break;
case 0:
+ spin_lock_irqsave(&ebu_lock, csflags);
ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
break;
@@ -99,7 +102,6 @@ static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
- unsigned long flags;
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_CLE)
@@ -109,11 +111,9 @@ static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
}
if (cmd != NAND_CMD_NONE) {
- spin_lock_irqsave(&ebu_lock, flags);
writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
;
- spin_unlock_irqrestore(&ebu_lock, flags);
}
}
@@ -126,12 +126,9 @@ static unsigned char xway_read_byte(struct mtd_info *mtd)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
- unsigned long flags;
int ret;
- spin_lock_irqsave(&ebu_lock, flags);
ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
- spin_unlock_irqrestore(&ebu_lock, flags);
return ret;
}
@@ -140,26 +137,20 @@ static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
- unsigned long flags;
int i;
- spin_lock_irqsave(&ebu_lock, flags);
for (i = 0; i < len; i++)
buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA));
- spin_unlock_irqrestore(&ebu_lock, flags);
}
static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
struct nand_chip *this = mtd->priv;
unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
- unsigned long flags;
int i;
- spin_lock_irqsave(&ebu_lock, flags);
for (i = 0; i < len; i++)
ltq_w8(buf[i], (void __iomem *)nandaddr);
- spin_unlock_irqrestore(&ebu_lock, flags);
}
static int xway_nand_probe(struct platform_device *pdev)
--
1.7.10.4

138
target/linux/lantiq/patches-3.14/0018-MTD-lantiq-Add-NAND-support-on-Lantiq-Falcon-SoC.patch Normal file
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@ -0,0 +1,138 @@
From e2c285e95e75258c196fbc04a742d91be6d00f49 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 30 Jan 2013 21:12:47 +0100
Subject: [PATCH 18/31] MTD: lantiq: Add NAND support on Lantiq Falcon SoC.
The driver uses plat_nand. As the platform_device is loaded from DT, we need
to lookup the node and attach our falcon specific "struct platform_nand_data"
to it.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/nand/Kconfig | 8 ++++
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/falcon_nand.c | 83 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 92 insertions(+)
create mode 100644 drivers/mtd/nand/falcon_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 90ff447..7064f0e 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -510,4 +510,12 @@ config MTD_NAND_XWAY
Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
to the External Bus Unit (EBU).
+config MTD_NAND_FALCON
+ tristate "Support for NAND on Lantiq FALC-ON SoC"
+ depends on LANTIQ && SOC_FALCON
+ select MTD_NAND_PLATFORM
+ help
+ Enables support for NAND Flash chips on Lantiq FALC-ON SoCs. NAND is
+ attached to the External Bus Unit (EBU).
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 542b568..78a1cd2 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
+obj-$(CONFIG_MTD_NAND_FALCON) += falcon_nand.o
nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/falcon_nand.c b/drivers/mtd/nand/falcon_nand.c
new file mode 100644
index 0000000..13458d3
--- /dev/null
+++ b/drivers/mtd/nand/falcon_nand.c
@@ -0,0 +1,83 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/mtd/nand.h>
+#include <linux/of_platform.h>
+
+#include <lantiq_soc.h>
+
+/* address lines used for NAND control signals */
+#define NAND_ADDR_ALE 0x10000
+#define NAND_ADDR_CLE 0x20000
+
+/* Ready/Busy Status */
+#define MODCON_STS 0x0002
+
+/* Ready/Busy Status Edge */
+#define MODCON_STSEDGE 0x0004
+#define LTQ_EBU_MODCON 0x000C
+
+static const char const *part_probes[] = { "cmdlinepart", "ofpart", NULL };
+
+static int falcon_nand_ready(struct mtd_info *mtd)
+{
+ u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
+
+ return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
+ (MODCON_STS | MODCON_STSEDGE)));
+}
+
+static void falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
+
+ if (ctrl & NAND_CLE)
+ nandaddr |= NAND_ADDR_CLE;
+ if (ctrl & NAND_ALE)
+ nandaddr |= NAND_ADDR_ALE;
+
+ this->IO_ADDR_W = (void __iomem *) nandaddr;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static struct platform_nand_data falcon_nand_data = {
+ .chip = {
+ .nr_chips = 1,
+ .chip_delay = 25,
+ .part_probe_types = part_probes,
+ },
+ .ctrl = {
+ .cmd_ctrl = falcon_hwcontrol,
+ .dev_ready = falcon_nand_ready,
+ }
+};
+
+int __init falcon_register_nand(void)
+{
+ struct device_node *node;
+ struct platform_device *pdev;
+
+ node = of_find_compatible_node(NULL, NULL, "lantiq,nand-falcon");
+ if (!node)
+ return -1;
+ pdev = of_find_device_by_node(node);
+ if (pdev)
+ pdev->dev.platform_data = &falcon_nand_data;
+ of_node_put(node);
+ return 0;
+}
+
+arch_initcall(falcon_register_nand);
--
1.7.10.4

46
target/linux/lantiq/patches-3.14/0019-MTD-lantiq-Makes-the-Lantiq-flash-driver-try-jedec-p.patch Normal file
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@ -0,0 +1,46 @@
From 4e2a4dcadb70985e86d9cebfca308891be377510 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:57:30 +0200
Subject: [PATCH 19/31] MTD: lantiq: Makes the Lantiq flash driver try jedec
probing if cfi probing fails.
(Based on work by Simon Hayes first published on www.psidoc.com and
http://sourceforge.net/projects/hh2b4ever/)
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/maps/lantiq-flash.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 710d699..dd1e853 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -117,6 +117,11 @@ ltq_mtd_probe(struct platform_device *pdev)
struct cfi_private *cfi;
int err;
+ static const char *rom_probe_types[] = {
+ "cfi_probe", "jedec_probe", NULL
+ };
+ const char **type;
+
if (of_machine_is_compatible("lantiq,falcon") &&
(ltq_boot_select() != BS_FLASH)) {
dev_err(&pdev->dev, "invalid bootstrap options\n");
@@ -158,7 +163,10 @@ ltq_mtd_probe(struct platform_device *pdev)
ltq_mtd->map->copy_to = ltq_copy_to;
ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING;
- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map);
+
+ for (type = rom_probe_types; !ltq_mtd->mtd && *type; type++)
+ ltq_mtd->mtd = do_map_probe(*type, ltq_mtd->map);
+
ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL;
if (!ltq_mtd->mtd) {
--
1.7.10.4

281
target/linux/lantiq/patches-3.14/0020-NET-PHY-adds-driver-for-lantiq-PHY11G.patch Normal file
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@ -0,0 +1,281 @@
From 6c895c9b0ceff79fdeb73876e35b536a312f851b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:15:36 +0200
Subject: [PATCH 20/31] NET: PHY: adds driver for lantiq PHY11G
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 237 insertions(+)
create mode 100644 drivers/net/phy/lantiq.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 9b5d46c..f3724b1 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -106,6 +106,11 @@ config MICREL_PHY
---help---
Supports the KSZ9021, VSC8201, KS8001 PHYs.
+config LANTIQ_PHY
+ tristate "Driver for Lantiq PHYs"
+ ---help---
+ Supports the 11G and 22E PHYs.
+
config FIXED_PHY
bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
depends on PHYLIB=y
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9013dfa..b5e030f 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
+obj-$(CONFIG_LANTIQ_PHY) += lantiq.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
obj-$(CONFIG_AT803X_PHY) += at803x.o
diff --git a/drivers/net/phy/lantiq.c b/drivers/net/phy/lantiq.c
new file mode 100644
index 0000000..f109bb9
--- /dev/null
+++ b/drivers/net/phy/lantiq.c
@@ -0,0 +1,231 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/phy.h>
+
+#define MII_MMDCTRL 0x0d
+#define MII_MMDDATA 0x0e
+
+#define MII_VR9_11G_IMASK 0x19 /* interrupt mask */
+#define MII_VR9_11G_ISTAT 0x1a /* interrupt status */
+
+#define INT_VR9_11G_WOL BIT(15) /* Wake-On-LAN */
+#define INT_VR9_11G_ANE BIT(11) /* Auto-Neg error */
+#define INT_VR9_11G_ANC BIT(10) /* Auto-Neg complete */
+#define INT_VR9_11G_ADSC BIT(5) /* Link auto-downspeed detect */
+#define INT_VR9_11G_DXMC BIT(2) /* Duplex mode change */
+#define INT_VR9_11G_LSPC BIT(1) /* Link speed change */
+#define INT_VR9_11G_LSTC BIT(0) /* Link state change */
+#define INT_VR9_11G_MASK (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
+
+#define ADVERTISED_MPD BIT(10) /* Multi-port device */
+
+#define MMD_DEVAD 0x1f
+#define MMD_ACTYPE_SHIFT 14
+#define MMD_ACTYPE_ADDRESS (0 << MMD_ACTYPE_SHIFT)
+#define MMD_ACTYPE_DATA (1 << MMD_ACTYPE_SHIFT)
+#define MMD_ACTYPE_DATA_PI (2 << MMD_ACTYPE_SHIFT)
+#define MMD_ACTYPE_DATA_PIWR (3 << MMD_ACTYPE_SHIFT)
+
+static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
+ u16 regnum)
+{
+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
+ phy_write(phydev, MII_MMDDATA, regnum);
+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
+
+ return phy_read(phydev, MII_MMDDATA);
+}
+
+static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
+ u16 regnum, u16 val)
+{
+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
+ phy_write(phydev, MII_MMDDATA, regnum);
+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
+ phy_write(phydev, MII_MMDDATA, val);
+
+ return 0;
+}
+
+static int vr9_gphy_config_init(struct phy_device *phydev)
+{
+ int err;
+
+ dev_dbg(&phydev->dev, "%s\n", __func__);
+
+ /* Mask all interrupts */
+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
+ if (err)
+ return err;
+
+ /* Clear all pending interrupts */
+ phy_read(phydev, MII_VR9_11G_ISTAT);
+
+ vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5);
+ vr9_gphy_mmd_write(phydev, 0x1e1, 0x67);
+ vr9_gphy_mmd_write(phydev, 0x1e2, 0x42);
+ vr9_gphy_mmd_write(phydev, 0x1e3, 0x10);
+ vr9_gphy_mmd_write(phydev, 0x1e4, 0x70);
+ vr9_gphy_mmd_write(phydev, 0x1e5, 0x03);
+ vr9_gphy_mmd_write(phydev, 0x1e6, 0x20);
+ vr9_gphy_mmd_write(phydev, 0x1e7, 0x00);
+ vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
+ vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
+
+ return 0;
+}
+
+static int vr9_gphy_config_aneg(struct phy_device *phydev)
+{
+ int reg, err;
+
+ /* Advertise as multi-port device */
+ reg = phy_read(phydev, MII_CTRL1000);
+ reg |= ADVERTISED_MPD;
+ err = phy_write(phydev, MII_CTRL1000, reg);
+ if (err)
+ return err;
+
+ return genphy_config_aneg(phydev);
+}
+
+static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
+{
+ int reg;
+
+ /*
+ * Possible IRQ numbers:
+ * - IM3_IRL18 for GPHY0
+ * - IM3_IRL17 for GPHY1
+ *
+ * Due to a silicon bug IRQ lines are not really independent from
+ * each other. Sometimes the two lines are driven at the same time
+ * if only one GPHY core raises the interrupt.
+ */
+
+ reg = phy_read(phydev, MII_VR9_11G_ISTAT);
+
+ return (reg < 0) ? reg : 0;
+}
+
+static int vr9_gphy_did_interrupt(struct phy_device *phydev)
+{
+ int reg;
+
+ reg = phy_read(phydev, MII_VR9_11G_ISTAT);
+
+ return reg > 0;
+}
+
+static int vr9_gphy_config_intr(struct phy_device *phydev)
+{
+ int err;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+ err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
+ else
+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
+
+ return err;
+}
+
+static struct phy_driver lantiq_phy[] = {
+ {
+ .phy_id = 0xd565a400,
+ .phy_id_mask = 0xffffffff,
+ .name = "Lantiq XWAY PEF7071",
+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
+ .config_init = vr9_gphy_config_init,
+ .config_aneg = vr9_gphy_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = vr9_gphy_ack_interrupt,
+ .did_interrupt = vr9_gphy_did_interrupt,
+ .config_intr = vr9_gphy_config_intr,
+ .driver = { .owner = THIS_MODULE },
+ }, {
+ .phy_id = 0x030260D0,
+ .phy_id_mask = 0xfffffff0,
+ .name = "Lantiq XWAY VR9 GPHY 11G v1.3",
+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
+ .config_init = vr9_gphy_config_init,
+ .config_aneg = vr9_gphy_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = vr9_gphy_ack_interrupt,
+ .did_interrupt = vr9_gphy_did_interrupt,
+ .config_intr = vr9_gphy_config_intr,
+ .driver = { .owner = THIS_MODULE },
+ }, {
+ .phy_id = 0xd565a408,
+ .phy_id_mask = 0xfffffff8,
+ .name = "Lantiq XWAY VR9 GPHY 11G v1.4",
+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
+ .config_init = vr9_gphy_config_init,
+ .config_aneg = vr9_gphy_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = vr9_gphy_ack_interrupt,
+ .did_interrupt = vr9_gphy_did_interrupt,
+ .config_intr = vr9_gphy_config_intr,
+ .driver = { .owner = THIS_MODULE },
+ }, {
+ .phy_id = 0xd565a418,
+ .phy_id_mask = 0xfffffff8,
+ .name = "Lantiq XWAY XRX PHY22F v1.4",
+ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
+ .config_init = vr9_gphy_config_init,
+ .config_aneg = vr9_gphy_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = vr9_gphy_ack_interrupt,
+ .did_interrupt = vr9_gphy_did_interrupt,
+ .config_intr = vr9_gphy_config_intr,
+ .driver = { .owner = THIS_MODULE },
+ },
+};
+
+static int __init ltq_phy_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
+ int err = phy_driver_register(&lantiq_phy[i]);
+ if (err)
+ pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
+ }
+
+ return 0;
+}
+
+static void __exit ltq_phy_exit(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
+ phy_driver_unregister(&lantiq_phy[i]);
+}
+
+module_init(ltq_phy_init);
+module_exit(ltq_phy_exit);
+
+MODULE_DESCRIPTION("Lantiq PHY drivers");
+MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
+MODULE_LICENSE("GPL");
--
1.7.10.4

375
target/linux/lantiq/patches-3.14/0021-NET-lantiq-adds-PHY11G-firmware-blobs.patch Normal file
View File

@ -0,0 +1,375 @@
From c64015eb950202f84829498a9c9daf949eded81f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 22 Oct 2012 09:26:24 +0200
Subject: [PATCH 21/31] NET: lantiq: adds PHY11G firmware blobs
Signed-off-by: John Crispin <blogic@openwrt.org>
---
firmware/Makefile | 4 +
firmware/lantiq/COPYING | 286 +++++++++++++++++++++++++++++++++++++++++++++++
firmware/lantiq/README | 45 ++++++++
3 files changed, 335 insertions(+)
create mode 100644 firmware/lantiq/COPYING
create mode 100644 firmware/lantiq/README
diff --git a/firmware/Makefile b/firmware/Makefile
index cbb09ce..171ebab 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -134,6 +134,10 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_PDA) += keyspan_pda/keyspan_pda.fw
fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw
fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a1x.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a2x.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a1x.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a2x.bin
fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
diff --git a/firmware/lantiq/COPYING b/firmware/lantiq/COPYING
new file mode 100644
index 0000000..5ec70b2
--- /dev/null
+++ b/firmware/lantiq/COPYING
@@ -0,0 +1,286 @@
+All firmware files are copyrighted by Lantiq Deutschland GmbH.
+The files have been extracted from header files found in Lantiq BSPs.
+If not stated otherwise all files are licensed under GPL.
+
+=======================================================================
+
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
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+if you want it, that you can change the software or use pieces of it
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+
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+Foundation.
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+ 10. If you wish to incorporate parts of the Program into other free
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+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
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+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
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+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
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+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
diff --git a/firmware/lantiq/README b/firmware/lantiq/README
new file mode 100644
index 0000000..1b666d4
--- /dev/null
+++ b/firmware/lantiq/README
@@ -0,0 +1,45 @@
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# (C) Copyright 2007 - 2012
+# Lantiq Deutschland GmbH
+#
+# (C) Copyright 2012
+# Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+#
+
+#
+# How to use
+#
+Configure kernel with:
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR"
+CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES"
+
+where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list
+of space separated files from list below.
+
+#
+# Firmware files
+#
+
+# GPHY core on Lantiq XWAY VR9 v1.1
+lantiq/vr9_phy11g_a1x.bin
+lantiq/vr9_phy22f_a1x.bin
+
+# GPHY core on Lantiq XWAY VR9 v1.2
+lantiq/vr9_phy11g_a2x.bin
+lantiq/vr9_phy22f_a2x.bin
--
1.7.10.4

3357
target/linux/lantiq/patches-3.14/0022-NET-MIPS-lantiq-adds-xrx200-net.patch Normal file
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File diff suppressed because it is too large Load Diff

60
target/linux/lantiq/patches-3.14/0023-NET-multi-phy-support.patch Normal file
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@ -0,0 +1,60 @@
From 2e265bc5154636daecf941acfea3087e7820877d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 27 Jul 2014 09:38:50 +0100
Subject: [PATCH 23/31] NET: multi phy support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/phy/phy.c | 9 ++++++---
include/linux/phy.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 76d96b9..371f0b6 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -715,7 +715,8 @@ void phy_state_machine(struct work_struct *work)
/* If the link is down, give up on negotiation for now */
if (!phydev->link) {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
break;
}
@@ -781,7 +782,8 @@ void phy_state_machine(struct work_struct *work)
netif_carrier_on(phydev->attached_dev);
} else {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
}
phydev->adjust_link(phydev->attached_dev);
@@ -793,7 +795,8 @@ void phy_state_machine(struct work_struct *work)
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
do_suspend = 1;
}
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 565188c..91b93f7 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -308,6 +308,7 @@ struct phy_device {
struct phy_c45_device_ids c45_ids;
bool is_c45;
bool is_internal;
+ bool no_auto_carrier_off;
enum phy_state state;
--
1.7.10.4

83
target/linux/lantiq/patches-3.14/0024-NET-add-of_get_mac_address_mtd.patch Normal file
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@ -0,0 +1,83 @@
From c4f036afb2016d21433c0214c55c01b8b9b7f4ee Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 27 Jul 2014 09:40:01 +0100
Subject: [PATCH 24/31] NET: add of_get_mac_address_mtd()
Many embedded devices have information such as mac addresses stored inside mtd
devices. This patch allows us to add a property inside a node describing a
network interface. The new property points at a mtd partition with an offset
where the mac address can be found.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++
include/linux/of_net.h | 1 +
2 files changed, 38 insertions(+)
diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
index a208a45..de93111 100644
--- a/drivers/of/of_net.c
+++ b/drivers/of/of_net.c
@@ -10,6 +10,7 @@
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/export.h>
+#include <linux/mtd/mtd.h>
/**
* It maps 'enum phy_interface_t' found in include/linux/phy.h
@@ -94,3 +95,39 @@ const void *of_get_mac_address(struct device_node *np)
return NULL;
}
EXPORT_SYMBOL(of_get_mac_address);
+
+int of_get_mac_address_mtd(struct device_node *np, void *mac)
+{
+ struct device_node *mtd_np = NULL;
+ size_t retlen;
+ int size, ret;
+ struct mtd_info *mtd;
+ const char *part;
+ const __be32 *list;
+ phandle phandle;
+
+ list = of_get_property(np, "mtd-mac-address", &size);
+ if (!list || (size != (2 * sizeof(*list))))
+ return -ENOENT;
+
+ phandle = be32_to_cpup(list++);
+ if (phandle)
+ mtd_np = of_find_node_by_phandle(phandle);
+
+ if (!mtd_np)
+ return -ENOENT;
+
+ part = of_get_property(mtd_np, "label", NULL);
+ if (!part)
+ part = mtd_np->name;
+
+ mtd = get_mtd_device_nm(part);
+ if (IS_ERR(mtd))
+ return PTR_ERR(mtd);
+
+ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, (u_char *) mac);
+ put_mtd_device(mtd);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(of_get_mac_address_mtd);
diff --git a/include/linux/of_net.h b/include/linux/of_net.h
index 34597c8..cdfbc60 100644
--- a/include/linux/of_net.h
+++ b/include/linux/of_net.h
@@ -11,6 +11,7 @@
#include <linux/of.h>
extern int of_get_phy_mode(struct device_node *np);
extern const void *of_get_mac_address(struct device_node *np);
+extern int of_get_mac_address_mtd(struct device_node *np, void *mac);
#else
static inline int of_get_phy_mode(struct device_node *np)
{
--
1.7.10.4

404
target/linux/lantiq/patches-3.14/0025-GPIO-MIPS-lantiq-add-gpio-driver-for-falcon-SoC.patch Normal file
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@ -0,0 +1,404 @@
From 8d45ea02fc0e9b5edd7deaf564663f1ffe8bed64 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Aug 2014 18:22:19 +0200
Subject: [PATCH 25/31] GPIO: MIPS: lantiq: add gpio driver for falcon SoC
Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
up to 32 pads. The GPIO blocks have a per pin IRQs.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-gpio@vger.kernel.org
---
drivers/gpio/Kconfig | 5 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-falcon.c | 348 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 354 insertions(+)
create mode 100644 drivers/gpio/gpio-falcon.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 903f24d..670c064 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -145,6 +145,11 @@ config GPIO_EP93XX
depends on ARCH_EP93XX
select GPIO_GENERIC
+config GPIO_FALCON
+ def_bool y
+ depends on MIPS && SOC_FALCON
+ select GPIO_GENERIC
+
config GPIO_MM_LANTIQ
bool "Lantiq Memory mapped GPIOs"
depends on LANTIQ && SOC_XWAY
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 5d50179..c92db39 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
obj-$(CONFIG_GPIO_EM) += gpio-em.o
obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
+obj-$(CONFIG_GPIO_FALCON) += gpio-falcon.o
obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o
obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
diff --git a/drivers/gpio/gpio-falcon.c b/drivers/gpio/gpio-falcon.c
new file mode 100644
index 0000000..ae3bdfb
--- /dev/null
+++ b/drivers/gpio/gpio-falcon.c
@@ -0,0 +1,348 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/export.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+
+#include <lantiq_soc.h>
+
+/* Data Output Register */
+#define GPIO_OUT 0x00000000
+/* Data Input Register */
+#define GPIO_IN 0x00000004
+/* Direction Register */
+#define GPIO_DIR 0x00000008
+/* External Interrupt Control Register 0 */
+#define GPIO_EXINTCR0 0x00000018
+/* External Interrupt Control Register 1 */
+#define GPIO_EXINTCR1 0x0000001C
+/* IRN Capture Register */
+#define GPIO_IRNCR 0x00000020
+/* IRN Interrupt Configuration Register */
+#define GPIO_IRNCFG 0x0000002C
+/* IRN Interrupt Enable Set Register */
+#define GPIO_IRNRNSET 0x00000030
+/* IRN Interrupt Enable Clear Register */
+#define GPIO_IRNENCLR 0x00000034
+/* Output Set Register */
+#define GPIO_OUTSET 0x00000040
+/* Output Cler Register */
+#define GPIO_OUTCLR 0x00000044
+/* Direction Clear Register */
+#define GPIO_DIRSET 0x00000048
+/* Direction Set Register */
+#define GPIO_DIRCLR 0x0000004C
+
+/* turn a gpio_chip into a falcon_gpio_port */
+#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
+/* turn a irq_data into a falcon_gpio_port */
+#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
+
+#define port_r32(p, reg) ltq_r32(p->port + reg)
+#define port_w32(p, val, reg) ltq_w32(val, p->port + reg)
+#define port_w32_mask(p, clear, set, reg) \
+ port_w32(p, (port_r32(p, reg) & ~(clear)) | (set), reg)
+
+#define MAX_BANKS 5
+#define PINS_PER_PORT 32
+
+struct falcon_gpio_port {
+ struct gpio_chip gpio_chip;
+ void __iomem *port;
+ unsigned int irq_base;
+ unsigned int chained_irq;
+ struct clk *clk;
+ char name[6];
+};
+
+static struct irq_chip falcon_gpio_irq_chip;
+
+static int falcon_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ port_w32(ctop(chip), 1 << offset, GPIO_DIRCLR);
+
+ return 0;
+}
+
+static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
+{
+ if (value)
+ port_w32(ctop(chip), 1 << offset, GPIO_OUTSET);
+ else
+ port_w32(ctop(chip), 1 << offset, GPIO_OUTCLR);
+}
+
+static int falcon_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset, int value)
+{
+ falcon_gpio_set(chip, offset, value);
+ port_w32(ctop(chip), 1 << offset, GPIO_DIRSET);
+
+ return 0;
+}
+
+static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ if ((port_r32(ctop(chip), GPIO_DIR) >> offset) & 1)
+ return (port_r32(ctop(chip), GPIO_OUT) >> offset) & 1;
+ else
+ return (port_r32(ctop(chip), GPIO_IN) >> offset) & 1;
+}
+
+static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ int gpio = chip->base + offset;
+
+ return pinctrl_request_gpio(gpio);
+}
+
+static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ int gpio = chip->base + offset;
+
+ pinctrl_free_gpio(gpio);
+}
+
+static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ return ctop(chip)->irq_base + offset;
+}
+
+static void falcon_gpio_disable_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
+}
+
+static void falcon_gpio_enable_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ port_w32(itop(d), 1 << offset, GPIO_IRNRNSET);
+}
+
+static void falcon_gpio_ack_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ port_w32(itop(d), 1 << offset, GPIO_IRNCR);
+}
+
+static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
+ port_w32(itop(d), 1 << offset, GPIO_IRNCR);
+}
+
+static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+ unsigned int mask = 1 << offset;
+
+ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
+ return 0;
+
+ if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
+ /* level triggered */
+ port_w32_mask(itop(d), 0, mask, GPIO_IRNCFG);
+ irq_set_chip_and_handler_name(d->irq,
+ &falcon_gpio_irq_chip, handle_level_irq, "mux");
+ } else {
+ /* edge triggered */
+ port_w32_mask(itop(d), mask, 0, GPIO_IRNCFG);
+ irq_set_chip_and_handler_name(d->irq,
+ &falcon_gpio_irq_chip, handle_simple_irq, "mux");
+ }
+
+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+ port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
+ port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR1);
+ } else {
+ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
+ /* positive logic: rising edge, high level */
+ port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
+ else
+ /* negative logic: falling edge, low level */
+ port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR0);
+ port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR1);
+ }
+
+ return gpio_direction_input(itop(d)->gpio_chip.base + offset);
+}
+
+static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
+ unsigned long irncr;
+ int offset;
+
+ /* acknowledge interrupt */
+ irncr = port_r32(gpio_port, GPIO_IRNCR);
+ port_w32(gpio_port, irncr, GPIO_IRNCR);
+
+ desc->irq_data.chip->irq_ack(&desc->irq_data);
+
+ for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
+ generic_handle_irq(gpio_port->irq_base + offset);
+}
+
+static int falcon_gpio_irq_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ struct falcon_gpio_port *port = d->host_data;
+
+ irq_set_chip_and_handler_name(irq, &falcon_gpio_irq_chip,
+ handle_simple_irq, "mux");
+ irq_set_chip_data(irq, port);
+
+ /* set to negative logic (falling edge, low level) */
+ port_w32_mask(port, 0, 1 << hw, GPIO_EXINTCR0);
+ return 0;
+}
+
+static struct irq_chip falcon_gpio_irq_chip = {
+ .name = "gpio_irq_mux",
+ .irq_mask = falcon_gpio_disable_irq,
+ .irq_unmask = falcon_gpio_enable_irq,
+ .irq_ack = falcon_gpio_ack_irq,
+ .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
+ .irq_set_type = falcon_gpio_irq_type,
+};
+
+static const struct irq_domain_ops irq_domain_ops = {
+ .xlate = irq_domain_xlate_onetwocell,
+ .map = falcon_gpio_irq_map,
+};
+
+static struct irqaction gpio_cascade = {
+ .handler = no_action,
+ .flags = IRQF_DISABLED,
+ .name = "gpio_cascade",
+};
+
+static int falcon_gpio_probe(struct platform_device *pdev)
+{
+ struct pinctrl_gpio_range *gpio_range;
+ struct device_node *node = pdev->dev.of_node;
+ const __be32 *bank = of_get_property(node, "lantiq,bank", NULL);
+ struct falcon_gpio_port *gpio_port;
+ struct resource *gpiores, irqres;
+ int ret, size;
+
+ if (!bank || *bank >= MAX_BANKS)
+ return -ENODEV;
+
+ size = pinctrl_falcon_get_range_size(*bank);
+ if (size < 1) {
+ dev_err(&pdev->dev, "pad not loaded for bank %d\n", *bank);
+ return size;
+ }
+
+ gpio_range = devm_kzalloc(&pdev->dev, sizeof(struct pinctrl_gpio_range),
+ GFP_KERNEL);
+ if (!gpio_range)
+ return -ENOMEM;
+
+ gpio_port = devm_kzalloc(&pdev->dev, sizeof(struct falcon_gpio_port),
+ GFP_KERNEL);
+ if (!gpio_port)
+ return -ENOMEM;
+
+ snprintf(gpio_port->name, 6, "gpio%d", *bank);
+ gpio_port->gpio_chip.label = gpio_port->name;
+ gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
+ gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
+ gpio_port->gpio_chip.get = falcon_gpio_get;
+ gpio_port->gpio_chip.set = falcon_gpio_set;
+ gpio_port->gpio_chip.request = falcon_gpio_request;
+ gpio_port->gpio_chip.free = falcon_gpio_free;
+ gpio_port->gpio_chip.base = *bank * PINS_PER_PORT;
+ gpio_port->gpio_chip.ngpio = size;
+ gpio_port->gpio_chip.dev = &pdev->dev;
+
+ gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ gpio_port->port = devm_request_and_ioremap(&pdev->dev, gpiores);
+ if (IS_ERR(gpio_port->port))
+ return PTR_ERR(gpio_port->port);
+
+ gpio_port->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(gpio_port->clk))
+ return PTR_ERR(gpio_port->clk);
+ clk_activate(gpio_port->clk);
+
+ if (of_irq_to_resource_table(node, &irqres, 1) == 1) {
+ gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * *bank);
+ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
+ gpio_port->chained_irq = irqres.start;
+ irq_domain_add_legacy(node, size, gpio_port->irq_base, 0,
+ &irq_domain_ops, gpio_port);
+ setup_irq(irqres.start, &gpio_cascade);
+ irq_set_handler_data(irqres.start, gpio_port);
+ irq_set_chained_handler(irqres.start, falcon_gpio_irq_handler);
+ }
+
+ ret = gpiochip_add(&gpio_port->gpio_chip);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, gpio_port);
+
+ gpio_range->name = "FALCON GPIO";
+ gpio_range->id = *bank;
+ gpio_range->base = gpio_port->gpio_chip.base;
+ gpio_range->pin_base = gpio_port->gpio_chip.base;
+ gpio_range->npins = gpio_port->gpio_chip.ngpio;
+ gpio_range->gc = &gpio_port->gpio_chip;
+
+ pinctrl_falcon_add_gpio_range(gpio_range);
+
+ return 0;
+}
+
+static const struct of_device_id falcon_gpio_match[] = {
+ { .compatible = "lantiq,falcon-gpio" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, falcon_gpio_match);
+
+static struct platform_driver falcon_gpio_driver = {
+ .probe = falcon_gpio_probe,
+ .driver = {
+ .name = "gpio-falcon",
+ .owner = THIS_MODULE,
+ .of_match_table = falcon_gpio_match,
+ },
+};
+
+int __init falcon_gpio_init(void)
+{
+ int ret;
+
+ pr_info("FALC(tm) ON GPIO Driver, (C) 2012 Lantiq Deutschland Gmbh\n");
+ ret = platform_driver_register(&falcon_gpio_driver);
+ if (ret)
+ pr_err("falcon_gpio: Error registering platform driver!");
+ return ret;
+}
+
+subsys_initcall(falcon_gpio_init);
--
1.7.10.4

1047
target/linux/lantiq/patches-3.14/0026-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch Normal file
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File diff suppressed because it is too large Load Diff

38
target/linux/lantiq/patches-3.14/0027-USB-fix-roothub-for-IFXHCD.patch Normal file
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@ -0,0 +1,38 @@
From 53c4acc1d3c7eae439b8bf3422de876e8a3e3bdb Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 6 Dec 2012 19:59:53 +0100
Subject: [PATCH 27/31] USB: fix roothub for IFXHCD
---
arch/mips/lantiq/Kconfig | 1 +
drivers/usb/core/hub.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 1621b1d..4c9a241 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -3,6 +3,7 @@ if LANTIQ
config SOC_TYPE_XWAY
bool
select PINCTRL_XWAY
+ select USB_ARCH_HAS_HCD
default n
choice
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 64ea219..30f4bdf 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -4077,7 +4077,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
udev->ttport = hdev->ttport;
} else if (udev->speed != USB_SPEED_HIGH
&& hdev->speed == USB_SPEED_HIGH) {
- if (!hub->tt.hub) {
+ if (hdev->parent && !hub->tt.hub) {
dev_err(&udev->dev, "parent hub has no TT\n");
retval = -EINVAL;
goto fail;
--
1.7.10.4

1032
target/linux/lantiq/patches-3.14/0028-SPI-MIPS-lantiq-adds-spi-xway.patch Normal file
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File diff suppressed because it is too large Load Diff

112
target/linux/lantiq/patches-3.14/0029-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch Normal file
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@ -0,0 +1,112 @@
From 748c654a6ba890e9a1b5bd29d0f198ce6b2c091f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 9 Aug 2013 18:47:27 +0200
Subject: [PATCH 29/31] reset: Fix compile when reset RESET_CONTROLLER is not
selected
Drivers need to protect their reset api calls with #ifdef to avoid compile
errors.
This patch adds dummy wrappers in the same way that linux/of.h does it.
Cc: linux-kernel@vger.kernel.org
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Gabor Juhos <juhosg@openwrt.org>
---
include/linux/reset-controller.h | 16 ++++++++++++++
include/linux/reset.h | 43 ++++++++++++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
index 41a4695..f38f530 100644
--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
@@ -46,7 +46,23 @@ struct reset_controller_dev {
unsigned int nr_resets;
};
+#if defined(CONFIG_RESET_CONTROLLER)
+
int reset_controller_register(struct reset_controller_dev *rcdev);
void reset_controller_unregister(struct reset_controller_dev *rcdev);
+#else
+
+static inline int reset_controller_register(struct reset_controller_dev *rcdev)
+{
+ return -ENOSYS;
+}
+
+void reset_controller_unregister(struct reset_controller_dev *rcdev)
+{
+
+}
+
+#endif
+
#endif
diff --git a/include/linux/reset.h b/include/linux/reset.h
index 6082247..1b36c9e 100644
--- a/include/linux/reset.h
+++ b/include/linux/reset.h
@@ -1,9 +1,13 @@
#ifndef _LINUX_RESET_H_
#define _LINUX_RESET_H_
+#include <linux/err.h>
+
struct device;
struct reset_control;
+#if defined(CONFIG_RESET_CONTROLLER)
+
int reset_control_reset(struct reset_control *rstc);
int reset_control_assert(struct reset_control *rstc);
int reset_control_deassert(struct reset_control *rstc);
@@ -14,4 +18,43 @@ struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
int device_reset(struct device *dev);
+#else /* CONFIG_RESET_CONTROLLER */
+
+static inline int reset_control_reset(struct reset_control *rstc)
+{
+ return -ENOSYS;
+}
+
+static inline int reset_control_assert(struct reset_control *rstc)
+{
+ return -ENOSYS;
+}
+
+static inline int reset_control_deassert(struct reset_control *rstc)
+{
+ return -ENOSYS;
+}
+
+static inline struct reset_control *reset_control_get(struct device *dev, const char *id)
+{
+ return ERR_PTR(-ENOSYS);
+}
+
+static inline void reset_control_put(struct reset_control *rstc)
+{
+
+}
+
+static inline struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
+{
+ return ERR_PTR(-ENOSYS);
+}
+
+static inline int device_reset(struct device *dev)
+{
+ return -ENOSYS;
+}
+
+#endif
+
#endif
--
1.7.10.4

26
target/linux/lantiq/patches-3.14/0030-MIPS-lantiq-command-line-work-around.patch Normal file
View File

@ -0,0 +1,26 @@
From 015e22a637fe6ab9f9d2d94d3be1b0b312d21b39 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 12 Aug 2014 21:40:41 +0200
Subject: [PATCH 30/31] MIPS: lantiq: command line work around
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/prom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 202e118..227feed 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -74,6 +74,8 @@ void __init plat_mem_setup(void)
* parsed resulting in our memory appearing
*/
__dt_setup_arch(&__image_dtb);
+
+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
}
void __init device_tree_init(void)
--
1.7.10.4

177
target/linux/lantiq/patches-3.14/0031-GPIO-add-named-gpio-exports.patch Normal file
View File

@ -0,0 +1,177 @@
From 6774a8fcd63da9511faa7501ee20c4dde289bb07 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 12 Aug 2014 20:49:27 +0200
Subject: [PATCH 31/31] GPIO: add named gpio exports
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
drivers/gpio/gpiolib.c | 11 +++++--
include/asm-generic/gpio.h | 5 +++
include/linux/gpio/consumer.h | 8 +++++
4 files changed, 90 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index e0a98f5..f16f271 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -21,6 +21,8 @@
#include <linux/of_gpio.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
struct gpio_desc;
@@ -296,3 +298,69 @@ void of_gpiochip_remove(struct gpio_chip *chip)
if (chip->of_node)
of_node_put(chip->of_node);
}
+
+static struct of_device_id gpio_export_ids[] = {
+ { .compatible = "gpio-export" },
+ { /* sentinel */ }
+};
+
+static int __init of_gpio_export_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *cnp;
+ u32 val;
+ int nb = 0;
+
+ for_each_child_of_node(np, cnp) {
+ const char *name = NULL;
+ int gpio;
+ bool dmc;
+ int max_gpio = 1;
+ int i;
+
+ of_property_read_string(cnp, "gpio-export,name", &name);
+
+ if (!name)
+ max_gpio = of_gpio_count(cnp);
+
+ for (i = 0; i < max_gpio; i++) {
+ unsigned flags = 0;
+ enum of_gpio_flags of_flags;
+
+ gpio = of_get_gpio_flags(cnp, i, &of_flags);
+
+ if (of_flags == OF_GPIO_ACTIVE_LOW)
+ flags |= GPIOF_ACTIVE_LOW;
+
+ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
+ else
+ flags |= GPIOF_IN;
+
+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
+ continue;
+
+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
+ gpio_export_with_name(gpio, dmc, name);
+ nb++;
+ }
+ }
+
+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
+
+ return 0;
+}
+
+static struct platform_driver gpio_export_driver = {
+ .driver = {
+ .name = "gpio-export",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(gpio_export_ids),
+ },
+};
+
+static int __init of_gpio_export_init(void)
+{
+ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe);
+}
+device_initcall(of_gpio_export_init);
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 50c4922..aece9f1 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -803,7 +803,7 @@ static struct class gpio_class = {
*
* Returns zero on success, else an error.
*/
-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
{
unsigned long flags;
int status;
@@ -843,7 +843,8 @@ int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
offset = gpio_chip_hwgpio(desc);
if (desc->chip->names && desc->chip->names[offset])
ioname = desc->chip->names[offset];
-
+ if (name)
+ ioname = name;
dev = device_create(&gpio_class, desc->chip->dev, MKDEV(0, 0),
desc, ioname ? ioname : "gpio%u",
desc_to_gpio(desc));
@@ -880,6 +881,12 @@ fail_unlock:
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
return status;
}
+EXPORT_SYMBOL_GPL(_gpiod_export);
+
+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+{
+ return _gpiod_export(desc, direction_may_change, NULL);
+}
EXPORT_SYMBOL_GPL(gpiod_export);
static int match_export(struct device *dev, const void *data)
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index a5f56a0..70a32ee 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -126,6 +126,11 @@ static inline int gpio_export(unsigned gpio, bool direction_may_change)
return gpiod_export(gpio_to_desc(gpio), direction_may_change);
}
+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
+{
+ return _gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
+}
+
static inline int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
{
diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h
index 7a8144f..085c31c 100644
--- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h
@@ -219,6 +219,7 @@ static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc);
@@ -227,6 +228,13 @@ void gpiod_unexport(struct gpio_desc *desc);
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
+static inline int _gpiod_export(struct gpio_desc *desc,
+ bool direction_may_change,
+ const char *name)
+{
+ return -ENOSYS;
+}
+
static inline int gpiod_export(struct gpio_desc *desc,
bool direction_may_change)
{
--
1.7.10.4

11
target/linux/lantiq/patches-3.14/0100-lantiq-xrx200-strip-fcs.patch Normal file
View File

@ -0,0 +1,11 @@
--- a/drivers/net/ethernet/lantiq_xrx200.c
+++ b/drivers/net/ethernet/lantiq_xrx200.c
@@ -933,7 +933,7 @@ static void xrx200_hw_receive(struct xrx
struct xrx200_priv *priv = netdev_priv(dev);
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
struct sk_buff *skb = ch->skb[ch->dma.desc];
- int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - ETH_FCS_LEN;
+ int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
unsigned long flags;
spin_lock_irqsave(&priv->hw->lock, flags);

70
target/linux/lantiq/xrx200/config-3.14 Normal file
View File

@ -0,0 +1,70 @@
CONFIG_ADM6996_PHY=y
CONFIG_AR8216_PHY=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GPIO_DEVRES=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_ARCH_TRACEHOOK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HZ_PERIODIC=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_POLLDEV=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_WORK=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_PHY=y
CONFIG_LANTIQ_XRX200=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MIPS_O32_FP64_SUPPORT is not set
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_XWAY=y
# CONFIG_MTD_PHYSMAP_OF is not set
# CONFIG_MTD_SM_COMMON is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_BLOCK is not set
# CONFIG_MTD_UBI_FASTMAP is not set
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_NLS=y
CONFIG_PCIE_LANTIQ=y
# CONFIG_PCI_LANTIQ is not set
# CONFIG_PROC_DEVICETREE is not set
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_RTL8306_PHY=y
CONFIG_RTL8366S_PHY=y
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
# CONFIG_UBIFS_FS_XZ is not set
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_XRX200_PHY_FW=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

67
target/linux/lantiq/xway/config-3.14 Normal file
View File

@ -0,0 +1,67 @@
CONFIG_ADM6996_PHY=y
CONFIG_AR8216_PHY=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GPIO_DEVRES=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_ARCH_TRACEHOOK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HZ_PERIODIC=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_POLLDEV=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_WORK=y
# CONFIG_ISDN is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MIPS_O32_FP64_SUPPORT is not set
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_XWAY=y
# CONFIG_MTD_PHYSMAP_OF is not set
# CONFIG_MTD_SM_COMMON is not set
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_NLS=y
# CONFIG_PROC_DEVICETREE is not set
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_RTL8306_PHY=y
CONFIG_RTL8366S_PHY=y
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
# CONFIG_UBIFS_FS_XZ is not set
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_XRX200_PHY_FW is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y