mirror of https://github.com/hak5/openwrt.git
ramips: support jumbo frame on mt7621 up to 2k
Signed-off-by: Michael Lee <igvtee@gmail.com>
(cherry picked from commit eee09bfe01
)
lede-17.01
parent
8d4c047dd1
commit
108a42bcba
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@ -600,7 +600,7 @@ Signed-off-by: Michael Lee <igvtee@gmail.com>
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+#endif
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -0,0 +1,1587 @@
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@@ -0,0 +1,1593 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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@ -1945,6 +1945,10 @@ Signed-off-by: Michael Lee <igvtee@gmail.com>
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+ if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
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+ return eth_change_mtu(dev, new_mtu);
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+
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+ if (IS_ENABLED(CONFIG_SOC_MT7621))
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+ if (new_mtu > 2048)
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+ return -EINVAL;
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+
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+ frag_size = fe_max_frag_size(new_mtu);
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+ if (new_mtu < 68 || frag_size > PAGE_SIZE)
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+ return -EINVAL;
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@ -1968,15 +1972,17 @@ Signed-off-by: Michael Lee <igvtee@gmail.com>
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+ return 0;
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+
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+ fe_stop(dev);
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+ fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
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+ if (new_mtu <= ETH_DATA_LEN) {
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+ fwd_cfg &= ~FE_GDM1_JMB_EN;
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+ } else {
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+ fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
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+ fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
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+ FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
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+ if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
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+ fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
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+ if (new_mtu <= ETH_DATA_LEN) {
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+ fwd_cfg &= ~FE_GDM1_JMB_EN;
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+ } else {
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+ fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
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+ fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
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+ FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
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+ }
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+ fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
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+ }
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+ fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
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+
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+ return fe_open(dev);
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+}
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@ -274,7 +274,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+MODULE_VERSION(MTK_FE_DRV_VERSION);
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
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@@ -0,0 +1,117 @@
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@@ -0,0 +1,123 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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@ -322,6 +322,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#define GSW_REG_ISR 0x700c
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+#define GSW_REG_GPC1 0x7014
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+
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+#define GSW_REG_MAC_P0_MCR 0x100
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+#define GSW_REG_MAC_P1_MCR 0x200
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+
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+// Global MAC control register
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+#define GSW_REG_GMACCR 0x30E0
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+
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+#define SYSC_REG_CHIP_REV_ID 0x0c
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+#define SYSC_REG_CFG1 0x14
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+#define RST_CTRL_MCM BIT(2)
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@ -14,7 +14,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/gsw_mt7621.c
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@@ -0,0 +1,284 @@
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@@ -0,0 +1,287 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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@ -115,17 +115,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ usleep_range(10, 20);
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+
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+ if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
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+ /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
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+ mtk_switch_w32(gsw, 0x2105e30b, 0x100);
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+ /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 2k) */
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+ mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
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+ mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
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+ } else {
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+ /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
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+ mtk_switch_w32(gsw, 0x2105e33b, 0x100);
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+ /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 2k) */
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+ mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P0_MCR);
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+ mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
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+ }
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+
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+ /* (GE2, Link down) */
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+ mtk_switch_w32(gsw, 0x8000, 0x200);
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+ mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
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+
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+ /* Set switch max RX frame length to 2k */
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+ mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B);
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+
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+ /* Enable Port 6, P5 as GMAC5, P5 disable */
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+ val = mt7530_mdio_r32(gsw, 0x7804);
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@ -163,7 +163,7 @@ Signed-off-by: Michael Lee <igvtee@gmail.com>
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+
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+ priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
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+ FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT |
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+ FE_FLAG_HAS_SWITCH;
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+ FE_FLAG_HAS_SWITCH | FE_FLAG_JUMBO_FRAME;
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+
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+ netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
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+ NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
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