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bump kernel to 3.2.12 

SVN-Revision: 31060
lede-17.01
John Crispin 2012-03-25 08:50:09 +00:00
parent c49f66675e
commit 0f6a9d5c7c
135 changed files with 30650 additions and 2285 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/linux/lantiq/Makefile
View File

@ -12,7 +12,7 @@ BOARDNAME:=Lantiq GPON/XWAY
FEATURES:=squashfs jffs2
DEFAULT_SUBTARGET:=danube
LINUX_VERSION:=3.1.10
LINUX_VERSION:=3.2.12
CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -fno-caller-saves

52
target/linux/lantiq/ar9/config-default
View File

@ -1,54 +1,38 @@
CONFIG_ADM6996_PHY=y
CONFIG_AR8216_PHY=y
# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_ATH79 is not set
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_HARDIRQS=y
CONFIG_HAVE_IRQ_WORK=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_ATMEL_PWM is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_FSNOTIFY=y
CONFIG_HAVE_MACH_CLKDEV=y
CONFIG_HW_HAS_PCI=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_GPIO_BUTTONS is not set
CONFIG_INPUT_POLLDEV=y
CONFIG_IRQ_FORCED_THREADING=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_ETOP=y
# CONFIG_LANTIQ_MACH_ARV45XX is not set
# CONFIG_LANTIQ_MACH_ARV is not set
# CONFIG_LANTIQ_MACH_EASY50712 is not set
CONFIG_LANTIQ_MACH_FRITZ_AR9=y
# CONFIG_LANTIQ_MACH_FRITZ_VR9 is not set
# CONFIG_LANTIQ_MACH_GIGASX76X is not set
CONFIG_LANTIQ_MACH_NETGEAR=y
CONFIG_LANTIQ_MACH_WBMR=y
# CONFIG_LANTIQ_MACH_GIGASX76X is not set
CONFIG_MACH_NO_WESTBRIDGE=y
# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_LANTIQ_VRX200 is not set
CONFIG_MDIO_BOARDINFO=y
# CONFIG_MLX4_CORE is not set
CONFIG_MTD_BLOCK2MTD=y
CONFIG_PCI=y
# CONFIG_PCIEPORTBUS is not set
# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PERF_USE_VMALLOC=y
# CONFIG_PREEMPT_RCU is not set
# CONFIG_QUOTACTL is not set
CONFIG_PCI_LANTIQ=y
# CONFIG_PCI_LANTIQ_NONE is not set
CONFIG_RTL8306_PHY=y
# CONFIG_SOC_AMAZON_SE is not set
# CONFIG_SOC_VR9 is not set
# CONFIG_SOC_FALCON is not set
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SOC_XWAY=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_LANTIQ=y
CONFIG_SPI_MASTER=y
CONFIG_USB_ARCH_HAS_XHCI=y
CONFIG_USB_SUPPORT=y
CONFIG_XZ_DEC=y
CONFIG_SPI_XWAY=y

2
target/linux/lantiq/ar9/profiles/001-lantiq.mk
View File

@ -1,5 +1,5 @@
define Profile/EASY50812
NAME:=EASY50812
NAME:=EASY50812 - Eval Board
PACKAGES:= kmod-usb-core kmod-usb-dwc-otg
endef

2
target/linux/lantiq/ar9/profiles/002-netgear.mk
View File

@ -1,5 +1,5 @@
define Profile/DGN3500B
NAME:=DGN3500B
NAME:=DGN3500B Netgear
PACKAGES:= kmod-usb-core kmod-usb-dwc-otg
endef

7
target/linux/lantiq/ar9/profiles/004-avm.mk Normal file
View File

@ -0,0 +1,7 @@
define Profile/FRITZ7320
NAME:=FRITZ7320 Fritzbox
PACKAGES:= kmod-usb-core kmod-usb-ifxhcd kmod-ledtrig-usbdev \
kmod-ltq-dsl-firmware-b-ar9 kmod-ath9k wpad-mini
endef
$(eval $(call Profile,FRITZ7320))

39
target/linux/lantiq/ase/config-default
View File

@ -1,39 +1,22 @@
# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_ATH79 is not set
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_HARDIRQS=y
CONFIG_HAVE_IRQ_WORK=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_ATMEL_PWM is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_FSNOTIFY=y
CONFIG_HAVE_MACH_CLKDEV=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_GPIO_BUTTONS is not set
CONFIG_INPUT_POLLDEV=y
CONFIG_IRQ_FORCED_THREADING=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_ETOP=y
CONFIG_LANTIQ_MACH_EASY50601=y
CONFIG_MACH_NO_WESTBRIDGE=y
# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
# CONFIG_MTD_LATCH_ADDR is not set
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_PERF_USE_VMALLOC=y
# CONFIG_PREEMPT_RCU is not set
# CONFIG_QUOTACTL is not set
# CONFIG_LANTIQ_VRX200 is not set
CONFIG_MDIO_BOARDINFO=y
CONFIG_SOC_AMAZON_SE=y
# CONFIG_SOC_VR9 is not set
# CONFIG_SOC_FALCON is not set
CONFIG_SOC_TYPE_XWAY=y
# CONFIG_SOC_XWAY is not set
CONFIG_XZ_DEC=y
CONFIG_SPI_XWAY=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_XHCI is not set
CONFIG_USB_SUPPORT=y

0
target/linux/lantiq/config-default → target/linux/lantiq/config-3.2
View File

51
target/linux/lantiq/danube/config-default
View File

@ -1,54 +1,37 @@
CONFIG_ADM6996_PHY=y
CONFIG_AR8216_PHY=y
# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_ATH79 is not set
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_GENERIC_HARDIRQS=y
CONFIG_HAVE_IRQ_WORK=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_ATMEL_PWM is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_FSNOTIFY=y
CONFIG_HAVE_MACH_CLKDEV=y
CONFIG_HW_HAS_PCI=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_GPIO_BUTTONS is not set
CONFIG_INPUT_POLLDEV=y
CONFIG_IRQ_FORCED_THREADING=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_ETOP=y
CONFIG_LANTIQ_MACH_ARV45XX=y
CONFIG_LANTIQ_MACH_ARV=y
CONFIG_LANTIQ_MACH_EASY50712=y
# CONFIG_LANTIQ_MACH_FRITZ_AR9 is not set
# CONFIG_LANTIQ_MACH_FRITZ_VR9 is not set
CONFIG_LANTIQ_MACH_GIGASX76X=y
# CONFIG_LANTIQ_MACH_NETGEAR is not set
# CONFIG_LANTIQ_MACH_WBMR is not set
CONFIG_LANTIQ_MACH_GIGASX76X=y
CONFIG_MACH_NO_WESTBRIDGE=y
# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_LANTIQ_VRX200 is not set
CONFIG_MDIO_BOARDINFO=y
# CONFIG_MLX4_CORE is not set
CONFIG_PCI=y
# CONFIG_PCIEPORTBUS is not set
# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PERF_USE_VMALLOC=y
# CONFIG_PREEMPT_RCU is not set
# CONFIG_QUOTACTL is not set
CONFIG_PCI_LANTIQ=y
# CONFIG_PCI_LANTIQ_NONE is not set
CONFIG_RTL8306_PHY=y
# CONFIG_SOC_AMAZON_SE is not set
# CONFIG_SOC_FALCON is not set
# CONFIG_SOC_VR9 is not set
CONFIG_SOC_TYPE_XWAY=y
CONFIG_SOC_XWAY=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_LANTIQ=y
CONFIG_SPI_MASTER=y
CONFIG_USB_ARCH_HAS_XHCI=y
CONFIG_USB_SUPPORT=y
CONFIG_XZ_DEC=y
CONFIG_SPI_XWAY=y

23
target/linux/lantiq/danube/profiles/004-bt.mk Normal file
View File

@ -0,0 +1,23 @@
define Profile/BTHOMEHUBV2B
NAME:=BTHOMEHUBV2B - BT Homehub V2.0 Type B
PACKAGES:= kmod-usb-core kmod-usb-dwc-otg kmod-ledtrig-usbdev \
kmod-ath9k wpad-mini kmod-ltq-dsl-firmware-a-danube
endef
define Profile/BTHOMEHUBV2B/Description
Package set optimized for the BT Homehub V2.0 Type B using whole nand for OpenWRT
endef
$(eval $(call Profile,BTHOMEHUBV2B))
define Profile/BTHOMEHUBV2BOPENRG
NAME:=BTHOMEHUBV2B - BT Homehub V2.0 Type B (OpenRG)
PACKAGES:= kmod-usb-core kmod-usb-dwc-otg kmod-ledtrig-usbdev \
kmod-ath9k wpad-mini kmod-ltq-dsl-firmware-a-danube
endef
define Profile/BTHOMEHUBV2BOPENRG/Description
Package set optimized for the BT Homehub V2.0 Type B but retaining OpenRG image
endef
$(eval $(call Profile,BTHOMEHUBV2BOPENRG))

18
target/linux/lantiq/falcon/config-default
View File

@ -1,28 +1,20 @@
CONFIG_CPU_MIPSR2_IRQ_EI=y
CONFIG_CPU_MIPSR2_IRQ_VI=y
CONFIG_IFX_VPE_CACHE_SPLIT=y
CONFIG_IFX_VPE_EXT=y
# CONFIG_ATMEL_PWM is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_FSNOTIFY=y
CONFIG_HAVE_MACH_CLKDEV=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_M25PXX_USE_FAST_READ=y
CONFIG_MIPS_MT=y
# CONFIG_MIPS_VPE_APSP_API is not set
CONFIG_MIPS_VPE_LOADER=y
CONFIG_MIPS_VPE_LOADER_TOM=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_PLATFORM=y
# CONFIG_MTD_SM_COMMON is not set
CONFIG_MTSCHED=y
# CONFIG_PERFCTRS is not set
# CONFIG_SOC_AMAZON_SE is not set
CONFIG_SOC_FALCON=y
# CONFIG_SOC_TYPE_XWAY is not set
# CONFIG_SOC_XWAY is not set
# CONFIG_SOC_VR9 is not set
CONFIG_SPI=y
# CONFIG_SPI_BITBANG is not set
CONFIG_SPI_FALCON=y
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_MASTER=y
# CONFIG_I2C_DESIGNWARE is not set

77
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-fritz.c
View File

@ -1,77 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/phy.h>
#include <lantiq_soc.h>
#include <irq.h>
#include "../machtypes.h"
#include "devices.h"
/*static struct mtd_partition fritz3370_partitions[] = {
{
.name = "uboot",
.offset = 0x0,
.size = 0x10000,
},
{
.name = "uboot_env",
.offset = 0x10000,
.size = 0x10000,
},
{
.name = "linux",
.offset = 0x20000,
.size = 0xe0000,
},
{
.name = "rootfs",
.offset = 0x100000,
.size = 0x300000,
},
};
static struct physmap_flash_data fritz3370_flash_data = {
.nr_parts = ARRAY_SIZE(fritz3370_partitions),
.parts = fritz3370_partitions,
};
static struct ltq_pci_data ltq_pci_data = {
.clock = PCI_CLOCK_INT,
.gpio = PCI_GNT1 | PCI_REQ1,
.irq = {
[14] = INT_NUM_IM0_IRL0 + 22,
},
};
*/
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_MII,
};
extern void xway_register_nand(void);
static void __init fritz3370_init(void)
{
// ltq_register_gpio_stp();
// ltq_register_nor(&fritz3370_flash_data);
// ltq_register_pci(&ltq_pci_data);
ltq_register_etop(&ltq_eth_data);
xway_register_nand();
}
MIPS_MACHINE(LANTIQ_MACH_FRITZ3370,
"FRITZ3370",
"FRITZ!BOX 3370",
fritz3370_init);

233
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-gigasx76x.c
View File

@ -1,233 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Andrej Vlašić
* Copyright (C) 2011 Luka Perkov
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/ath5k_platform.h>
#include <linux/pci.h>
#include <linux/phy.h>
#include <linux/io.h>
#include <linux/string.h>
#include <irq.h>
#include <lantiq_soc.h>
#include <lantiq_platform.h>
#include <dev-gpio-leds.h>
#include <dev-gpio-buttons.h>
#include "../machtypes.h"
#include "dev-wifi-ath5k.h"
#include "devices.h"
#include "dev-dwc_otg.h"
#include "mach-gigasx76x.h"
#define UBOOT_ENV_OFFSET 0x010000
#define UBOOT_ENV_SIZE 0x010000
static struct mtd_partition gigasx76x_partitions[] =
{
{
.name = "uboot",
.offset = 0x000000,
.size = 0x010000,
},
{
.name = "uboot_env",
.offset = UBOOT_ENV_OFFSET,
.size = UBOOT_ENV_SIZE,
},
{
.name = "linux",
.offset = 0x020000,
.size = 0x7e0000,
},
};
static struct gpio_led
gigasx76x_gpio_leds[] __initdata = {
{ .name = "soc:green:voip", .gpio = 216, },
{ .name = "soc:green:adsl", .gpio = 217, },
{ .name = "soc:green:usb", .gpio = 218, },
{ .name = "soc:green:wifi", .gpio = 219, },
{ .name = "soc:green:phone2", .gpio = 220, },
{ .name = "soc:green:phone1", .gpio = 221, },
{ .name = "soc:green:line", .gpio = 222, },
{ .name = "soc:green:online", .gpio = 223, },
};
static struct gpio_keys_button
gigasx76x_gpio_keys[] __initdata = {
{
.desc = "wps",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 22,
.active_low = 1,
},
{
.desc = "reset",
.type = EV_KEY,
.code = BTN_0,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 14,
.active_low = 0,
},
};
static struct physmap_flash_data gigasx76x_flash_data = {
.nr_parts = ARRAY_SIZE(gigasx76x_partitions),
.parts = gigasx76x_partitions,
};
static struct ltq_pci_data ltq_pci_data = {
.clock = PCI_CLOCK_INT,
.gpio = PCI_GNT1 | PCI_REQ1,
.irq = { [14] = INT_NUM_IM0_IRL0 + 22, },
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_MII,
};
static char __init *get_uboot_env_var(char *haystack, int haystack_len, char *needle, int needle_len) {
int i;
for (i = 0; i <= haystack_len - needle_len; i++) {
if (memcmp(haystack + i, needle, needle_len) == 0) {
return haystack + i + needle_len;
}
}
return NULL;
}
/*
* gigasx76x_parse_hex_* are not uniq. in arm/orion there are also duplicates:
* dns323_parse_hex_*
* TODO: one day write a patch for this :)
*/
static int __init gigasx76x_parse_hex_nibble(char n) {
if (n >= '0' && n <= '9')
return n - '0';
if (n >= 'A' && n <= 'F')
return n - 'A' + 10;
if (n >= 'a' && n <= 'f')
return n - 'a' + 10;
return -1;
}
static int __init gigasx76x_parse_hex_byte(const char *b) {
int hi;
int lo;
hi = gigasx76x_parse_hex_nibble(b[0]);
lo = gigasx76x_parse_hex_nibble(b[1]);
if (hi < 0 || lo < 0)
return -1;
return (hi << 4) | lo;
}
static u16 gigasx76x_ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
static u8 gigasx76x_ath5k_eeprom_mac[6];
static int __init gigasx76x_register_ethernet(void) {
u_int8_t addr[6];
int i;
char *uboot_env_page;
char *mac;
char *boardid;
uboot_env_page = ioremap(LTQ_FLASH_START + UBOOT_ENV_OFFSET, UBOOT_ENV_SIZE);
if (!uboot_env_page)
return -ENOMEM;
mac = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0ethaddr=", 9);
boardid = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0boardid=", 9);
if (!mac) {
goto error_fail;
}
if (!boardid) {
goto error_fail;
}
/* Sanity check the string we're looking at */
for (i = 0; i < 5; i++) {
if (*(mac + (i * 3) + 2) != ':') {
goto error_fail;
}
}
for (i = 0; i < 6; i++) {
int byte;
byte = gigasx76x_parse_hex_byte(mac + (i * 3));
if (byte < 0) {
goto error_fail;
}
addr[i] = byte;
}
iounmap(uboot_env_page);
printk("GIGASX76X: Found ethernet MAC address: ");
for (i = 0; i < 6; i++)
printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
memcpy(&ltq_eth_data.mac.sa_data, addr, 6);
ltq_register_etop(&ltq_eth_data);
memcpy(&gigasx76x_ath5k_eeprom_mac, addr, 6);
gigasx76x_ath5k_eeprom_mac[5]++;
if (strncmp(boardid, "sx763", 5) == 0) {
printk("GIGASX76X: Board id is sx763.");
memcpy(&gigasx76x_ath5k_eeprom_data, sx763_eeprom_data, ATH5K_PLAT_EEP_MAX_WORDS);
} else if (strncmp(boardid, "sx762", 5) == 0) {
printk("GIGASX76X: Board id is sx762.");
memcpy(&gigasx76x_ath5k_eeprom_data, sx762_eeprom_data, ATH5K_PLAT_EEP_MAX_WORDS);
} else {
printk("GIGASX76X: Board id is unknown, fix uboot_env data.");
}
return 0;
error_fail:
iounmap(uboot_env_page);
return -EINVAL;
}
static void __init gigasx76x_init(void) {
#define GIGASX76X_USB 29
#define GIGASX76X_MADWIFI_ADDR 0xb07f0000
ltq_register_gpio_stp();
ltq_register_nor(&gigasx76x_flash_data);
ltq_register_pci(&ltq_pci_data);
ltq_register_tapi();
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(gigasx76x_gpio_leds), gigasx76x_gpio_leds);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(gigasx76x_gpio_keys), gigasx76x_gpio_keys);
ltq_register_ath5k(gigasx76x_ath5k_eeprom_data, gigasx76x_ath5k_eeprom_mac);
xway_register_dwc(GIGASX76X_USB);
gigasx76x_register_ethernet();
}
MIPS_MACHINE(LANTIQ_MACH_GIGASX76X, "GIGASX76X", "GIGASX76X - Gigaset SX761,SX762,SX763", gigasx76x_init);

0
target/linux/lantiq/files-3.1/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h → target/linux/lantiq/files-3.2/arch/mips/include/asm/mach-lantiq/dev-gpio-buttons.h
View File

0
target/linux/lantiq/files-3.1/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h → target/linux/lantiq/files-3.2/arch/mips/include/asm/mach-lantiq/dev-gpio-leds.h
View File

0
target/linux/lantiq/files-3.1/arch/mips/lantiq/dev-gpio-buttons.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/dev-gpio-buttons.c
View File

0
target/linux/lantiq/files-3.1/arch/mips/lantiq/dev-gpio-leds.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/dev-gpio-leds.c
View File

1
target/linux/lantiq/files-3.1/arch/mips/lantiq/falcon/addon-easy98000.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/falcon/addon-easy98000.c
View File

@ -10,6 +10,7 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/types.h>
#include <linux/init.h>

1
target/linux/lantiq/files-3.1/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c
View File

@ -14,6 +14,7 @@
#include <linux/types.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/leds.h>
#include <linux/slab.h>

0
target/linux/lantiq/files-3.1/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h → target/linux/lantiq/files-3.2/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/falcon/mach-95C3AM1.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/falcon/mach-95C3AM1.c
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/falcon/mach-easy98020.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/falcon/mach-easy98020.c
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/dev-dwc_otg.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/dev-dwc_otg.c
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/dev-dwc_otg.h → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/dev-dwc_otg.h
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/dev-wifi-ath5k.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/dev-wifi-ath5k.c
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/dev-wifi-ath5k.h → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/dev-wifi-ath5k.h
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/dev-wifi-rt2x00.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/dev-wifi-rt2x00.c
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0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/dev-wifi-rt2x00.h → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/dev-wifi-rt2x00.h
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433
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-arv45xx.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-arv.c
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@ -17,6 +17,7 @@
#include <linux/input.h>
#include <linux/etherdevice.h>
#include <linux/ath5k_platform.h>
#include <linux/ath9k_platform.h>
#include <linux/pci.h>
#include <lantiq_soc.h>
@ -26,57 +27,10 @@
#include "../machtypes.h"
#include "dev-wifi-rt2x00.h"
#include "dev-wifi-ath5k.h"
#include "dev-wifi-athxk.h"
#include "devices.h"
#include "dev-dwc_otg.h"
static struct mtd_partition arv4510_partitions[] =
{
{
.name = "uboot",
.offset = 0x0,
.size = 0x20000,
},
{
.name = "uboot_env",
.offset = 0x20000,
.size = 0x120000,
},
{
.name = "linux",
.offset = 0x40000,
.size = 0xfa0000,
},
{
.name = "board_config",
.offset = 0xfe0000,
.size = 0x20000,
},
};
static struct mtd_partition arv45xx_partitions[] =
{
{
.name = "uboot",
.offset = 0x0,
.size = 0x20000,
},
{
.name = "uboot_env",
.offset = 0x20000,
.size = 0x10000,
},
{
.name = "linux",
.offset = 0x30000,
.size = 0x3c0000,
},
{
.name = "board_config",
.offset = 0x3f0000,
.size = 0x10000,
},
};
#include "pci-ath-fixup.h"
static struct mtd_partition arv45xx_brnboot_partitions[] =
{
@ -107,46 +61,27 @@ static struct mtd_partition arv45xx_brnboot_partitions[] =
},
};
static struct mtd_partition arv7525_partitions[] =
static struct mtd_partition arv75xx_brnboot_partitions[] =
{
{
.name = "uboot",
.name = "brn-boot",
.offset = 0x0,
.size = 0x10000,
.size = 0x20000,
},
{
.name = "uboot_env",
.offset = 0x10000,
.size = 0x10000,
.name = "config",
.offset = 0x20000,
.size = 0x40000,
},
{
.name = "linux",
.offset = 0x20000,
.size = 0x3d0000,
.offset = 0x440000,
.size = 0x3a0000,
},
{
.name = "board_config",
.offset = 0x3f0000,
.size = 0x10000,
},
};
static struct mtd_partition arv75xx_partitions[] =
{
{
.name = "uboot",
.offset = 0x0,
.size = 0x10000,
},
{
.name = "uboot_env",
.offset = 0x10000,
.size = 0x10000,
},
{
.name = "linux",
.offset = 0x20000,
.size = 0x7d0000,
.name = "reserved", /* 12-byte signature at 0x7efff4 :/ */
.offset = 0x7e0000,
.size = 0x010000,
},
{
.name = "board_config",
@ -155,14 +90,32 @@ static struct mtd_partition arv75xx_partitions[] =
},
};
static struct physmap_flash_data arv4510_flash_data = {
.nr_parts = ARRAY_SIZE(arv4510_partitions),
.parts = arv4510_partitions,
};
static struct physmap_flash_data arv45xx_flash_data = {
.nr_parts = ARRAY_SIZE(arv45xx_partitions),
.parts = arv45xx_partitions,
/*
* this is generic configuration for all arv based boards, note that it can be
* rewriten in arv_load_nor()
*/
static struct mtd_partition arv_partitions[] =
{
{
.name = "uboot",
.offset = 0x0,
.size = 0x20000,
},
{
.name = "uboot_env",
.offset = 0x20000,
.size = 0x10000,
},
{
.name = "linux",
.offset = 0x30000,
.size = 0x3c0000,
},
{
.name = "board_config",
.offset = 0x3f0000,
.size = 0x10000,
},
};
static struct physmap_flash_data arv45xx_brnboot_flash_data = {
@ -170,16 +123,48 @@ static struct physmap_flash_data arv45xx_brnboot_flash_data = {
.parts = arv45xx_brnboot_partitions,
};
static struct physmap_flash_data arv7525_flash_data = {
.nr_parts = ARRAY_SIZE(arv7525_partitions),
.parts = arv7525_partitions,
static struct physmap_flash_data arv75xx_brnboot_flash_data = {
.nr_parts = ARRAY_SIZE(arv75xx_brnboot_partitions),
.parts = arv75xx_brnboot_partitions,
};
static struct physmap_flash_data arv75xx_flash_data = {
.nr_parts = ARRAY_SIZE(arv75xx_partitions),
.parts = arv75xx_partitions,
static struct physmap_flash_data arv_flash_data = {
.nr_parts = ARRAY_SIZE(arv_partitions),
.parts = arv_partitions,
};
static void arv_load_nor(unsigned int max)
{
#define UBOOT_MAGIC 0x27051956
int i;
int sector = -1;
if (ltq_brn_boot) {
if (max == 0x800000)
ltq_register_nor(&arv75xx_brnboot_flash_data);
else
ltq_register_nor(&arv45xx_brnboot_flash_data);
return;
}
for (i = 1; i < 4 && sector < 0; i++) {
unsigned int uboot_magic;
memcpy_fromio(&uboot_magic, (void *)KSEG1ADDR(LTQ_FLASH_START) + (i * 0x10000), 4);
if (uboot_magic == UBOOT_MAGIC)
sector = i;
}
if (sector < 0)
return;
arv_partitions[0].size = arv_partitions[1].offset = (sector - 1) * 0x10000;
arv_partitions[2].offset = arv_partitions[0].size + 0x10000;
arv_partitions[2].size = max - arv_partitions[2].offset - 0x10000;
arv_partitions[3].offset = max - 0x10000;
ltq_register_nor(&arv_flash_data);
}
static struct ltq_pci_data ltq_pci_data = {
.clock = PCI_CLOCK_EXT,
.gpio = PCI_GNT1 | PCI_REQ1,
@ -240,6 +225,45 @@ arv4518pw_gpio_keys[] __initdata = {
},
};
static struct gpio_led
arv4519pw_gpio_leds[] __initdata = {
{ .name = "soc:red:power", .gpio = 7, .active_low = 1, },
{ .name = "soc:green:power", .gpio = 2, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:wifi", .gpio = 6, .active_low = 1, },
{ .name = "soc:green:adsl", .gpio = 4, .active_low = 1, },
{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, },
{ .name = "soc:red:internet", .gpio = 8, .active_low = 1, },
{ .name = "soc:green:voip", .gpio = 100, .active_low = 1, },
{ .name = "soc:green:phone1", .gpio = 101, .active_low = 1, },
{ .name = "soc:green:phone2", .gpio = 102, .active_low = 1, },
{ .name = "soc:green:fxo", .gpio = 103, .active_low = 1, },
{ .name = "soc:green:usb", .gpio = 19, .active_low = 1, },
{ .name = "soc:orange:wps", .gpio = 104, .active_low = 1, },
{ .name = "soc:green:wps", .gpio = 105, .active_low = 1, },
{ .name = "soc:red:wps", .gpio = 106, .active_low = 1, },
};
static struct gpio_keys_button
arv4519pw_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = BTN_1,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 30,
.active_low = 1,
},
{
.desc = "wlan",
.type = EV_KEY,
.code = BTN_2,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 28,
.active_low = 1,
},
};
static struct gpio_led
arv4520pw_gpio_leds[] __initdata = {
{ .name = "soc:blue:power", .gpio = 3, .active_low = 1, },
@ -343,28 +367,37 @@ arv752dpw22_gpio_keys[] __initdata = {
static struct gpio_led
arv7518pw_gpio_leds[] __initdata = {
{ .name = "soc:green:power", .gpio = 2, .active_low = 1, },
{ .name = "soc:red:power", .gpio = 7, .active_low = 1, },
{ .name = "soc:green:power", .gpio = 2, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:wifi", .gpio = 6, .active_low = 1, },
{ .name = "soc:green:adsl", .gpio = 4, .active_low = 1, },
{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, },
{ .name = "soc:green:wifi", .gpio = 6, .active_low = 1, },
{ .name = "soc:red:internet", .gpio = 8, .active_low = 1, },
{ .name = "soc:green:voip", .gpio = 100, .active_low = 1, },
{ .name = "soc:green:phone1", .gpio = 101, .active_low = 1, },
{ .name = "soc:green:phone2", .gpio = 102, .active_low = 1, },
{ .name = "soc:orange:fail", .gpio = 103, .active_low = 1, },
{ .name = "soc:green:usb", .gpio = 19, .active_low = 1, },
{ .name = "soc:orange:wps", .gpio = 104, .active_low = 1, },
{ .name = "soc:green:wps", .gpio = 105, .active_low = 1, },
{ .name = "soc:red:wps", .gpio = 106, .active_low = 1, },
};
static struct gpio_keys_button
arv7518pw_gpio_keys[] __initdata = {
{
/*{
.desc = "reset",
.type = EV_KEY,
.code = BTN_0,
.code = BTN_1,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 23,
.active_low = 1,
},
},*/
{
.desc = "wifi",
.type = EV_KEY,
.code = BTN_1,
.code = BTN_2,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 25,
.active_low = 1,
@ -384,70 +417,75 @@ arv7525pw_gpio_keys[] __initdata = {
};
static void
arv45xx_register_ethernet(void)
arv_register_ethernet(unsigned int mac_addr)
{
#define ARV45XX_BRN_MAC 0x3f0016
memcpy_fromio(&ltq_eth_data.mac.sa_data,
(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_MAC), 6);
(void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6);
ltq_register_etop(&ltq_eth_data);
}
static void
arv75xx_register_ethernet(void)
{
#define ARV75XX_BRN_MAC 0x7f0016
memcpy_fromio(&ltq_eth_data.mac.sa_data,
(void *)KSEG1ADDR(LTQ_FLASH_START + ARV75XX_BRN_MAC), 6);
ltq_register_etop(&ltq_eth_data);
}
static void
bewan_register_ethernet(void)
{
#define BEWAN_BRN_MAC 0x3f0014
memcpy_fromio(&ltq_eth_data.mac.sa_data,
(void *)KSEG1ADDR(LTQ_FLASH_START + BEWAN_BRN_MAC), 6);
ltq_register_etop(&ltq_eth_data);
}
static u16 arv45xx_ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
static u8 arv45xx_ath5k_eeprom_mac[6];
static u16 arv_ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
static u16 arv_ath9k_eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS];
static u8 arv_athxk_eeprom_mac[6];
void __init
arv45xx_register_ath5k(void)
arv_register_ath5k(unsigned int ath_addr, unsigned int mac_addr)
{
#define ARV45XX_BRN_ATH 0x3f0478
int i;
static u16 eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
u32 *p = (u32*)arv45xx_ath5k_eeprom_data;
memcpy_fromio(arv45xx_ath5k_eeprom_mac,
(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_MAC), 6);
arv45xx_ath5k_eeprom_mac[5]++;
memcpy_fromio(arv45xx_ath5k_eeprom_data,
(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_ATH), ATH5K_PLAT_EEP_MAX_WORDS);
memcpy_fromio(arv_athxk_eeprom_mac,
(void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6);
arv_athxk_eeprom_mac[5]++;
memcpy_fromio(arv_ath5k_eeprom_data,
(void *)KSEG1ADDR(LTQ_FLASH_START + ath_addr), ATH5K_PLAT_EEP_MAX_WORDS);
// swap eeprom bytes
for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS>>1; i++) {
//arv4518_ath5k_eeprom_data[i] = ((eeprom_data[i]&0xff)<<8)|((eeprom_data[i]&0xff00)>>8);
p[i] = ((eeprom_data[(i<<1)+1]&0xff)<<24)|((eeprom_data[(i<<1)+1]&0xff00)<<8)|((eeprom_data[i<<1]&0xff)<<8)|((eeprom_data[i<<1]&0xff00)>>8);
if (i == 0xbf>>1){
// printk ("regdomain: 0x%x --> 0x%x\n", p[i], (p[i] & 0xffff0000)|0x67);
/* regdomain is invalid?? how did original fw convert
* value to 0x82d4 ??
* for now, force to 0x67 */
p[i] &= 0xffff0000;
p[i] |= 0x67;
arv_ath5k_eeprom_data[i] = swab16(arv_ath5k_eeprom_data[i]);
if (i == 0x17e>>1) {
/*
* regdomain is invalid. it's unknown how did original
* fw convered value to 0x82d4 so for now force to 0x67
*/
arv_ath5k_eeprom_data[i] &= 0x0000;
arv_ath5k_eeprom_data[i] |= 0x67;
}
}
}
void __init
arv_register_ath9k(unsigned int ath_addr, unsigned int mac_addr)
{
int i;
u16 *eepdata, sum, el;
memcpy_fromio(arv_athxk_eeprom_mac,
(void *)KSEG1ADDR(LTQ_FLASH_START + mac_addr), 6);
arv_athxk_eeprom_mac[5]++;
memcpy_fromio(arv_ath9k_eeprom_data,
(void *)KSEG1ADDR(LTQ_FLASH_START + ath_addr), ATH9K_PLAT_EEP_MAX_WORDS);
// force regdomain to 0x67
arv_ath9k_eeprom_data[0x208>>1] = 0x67;
// calculate new checksum
sum = arv_ath9k_eeprom_data[0x200>>1];
el = sum / sizeof(u16) - 2; /* skip length and (old) checksum */
eepdata = (u16 *) (&arv_ath9k_eeprom_data[0x204>>1]); /* after checksum */
for (i = 0; i < el; i++)
sum ^= *eepdata++;
sum ^= 0xffff;
arv_ath9k_eeprom_data[0x202>>1] = sum;
}
static void __init
arv3527p_init(void)
{
#define ARV3527P_MAC_ADDR 0x3f0016
ltq_register_gpio_stp();
//ltq_add_device_gpio_leds(arv3527p_gpio_leds, ARRAY_SIZE(arv3527p_gpio_leds));
ltq_register_nor(&arv45xx_flash_data);
arv45xx_register_ethernet();
arv_load_nor(0x400000);
arv_register_ethernet(ARV3527P_MAC_ADDR);
}
MIPS_MACHINE(LANTIQ_MACH_ARV3527P,
@ -458,14 +496,16 @@ MIPS_MACHINE(LANTIQ_MACH_ARV3527P,
static void __init
arv4510pw_init(void)
{
#define ARV4510PW_MAC_ADDR 0x3f0014
ltq_register_gpio_stp();
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4510pw_gpio_leds), arv4510pw_gpio_leds);
ltq_register_nor(&arv4510_flash_data);
arv_load_nor(0x400000);
ltq_pci_data.irq[12] = (INT_NUM_IM2_IRL0 + 31);
ltq_pci_data.irq[15] = (INT_NUM_IM0_IRL0 + 26);
ltq_pci_data.gpio |= PCI_EXIN2 | PCI_REQ2;
ltq_register_pci(&ltq_pci_data);
bewan_register_ethernet();
arv_register_ethernet(ARV4510PW_MAC_ADDR);
}
MIPS_MACHINE(LANTIQ_MACH_ARV4510PW,
@ -479,19 +519,21 @@ arv4518pw_init(void)
#define ARV4518PW_EBU 0
#define ARV4518PW_USB 14
#define ARV4518PW_SWITCH_RESET 13
#define ARV4518PW_MADWIFI_ADDR 0xb07f0400
#define ARV4518PW_ATH_ADDR 0x3f0400
#define ARV4518PW_MADWIFI_ADDR 0xb03f0400
#define ARV4518PW_MAC_ADDR 0x3f0016
ltq_register_gpio_ebu(ARV4518PW_EBU);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4518pw_gpio_leds), arv4518pw_gpio_leds);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(arv4518pw_gpio_keys), arv4518pw_gpio_keys);
ltq_register_nor(&arv45xx_flash_data);
arv_load_nor(0x400000);
ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ2;
ltq_register_pci(&ltq_pci_data);
ltq_register_madwifi_eep(ARV4518PW_MADWIFI_ADDR);
ltq_register_ath5k(arv45xx_ath5k_eeprom_data, arv45xx_ath5k_eeprom_mac);
xway_register_dwc(ARV4518PW_USB);
arv45xx_register_ethernet();
arv_register_ethernet(ARV4518PW_MAC_ADDR);
arv_register_ath5k(ARV4518PW_ATH_ADDR, ARV4518PW_MAC_ADDR);
ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac);
gpio_request(ARV4518PW_SWITCH_RESET, "switch");
gpio_direction_output(ARV4518PW_SWITCH_RESET, 1);
@ -503,19 +545,56 @@ MIPS_MACHINE(LANTIQ_MACH_ARV4518PW,
"ARV4518PW - SMC7908A-ISP, Airties WAV-221",
arv4518pw_init);
static void __init
arv4519pw_init(void)
{
#define ARV4519PW_EBU 0
#define ARV4519PW_USB 14
#define ARV4519PW_RELAY 31
#define ARV4519PW_SWITCH_RESET 13
#define ARV4519PW_ATH_ADDR 0x3f0400
#define ARV4519PW_MAC_ADDR 0x3f0016
arv_load_nor(0x400000);
ltq_register_gpio_ebu(ARV4519PW_EBU);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4519pw_gpio_leds), arv4519pw_gpio_leds);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(arv4519pw_gpio_keys), arv4519pw_gpio_keys);
ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ1;
ltq_register_pci(&ltq_pci_data);
xway_register_dwc(ARV4519PW_USB);
arv_register_ethernet(ARV4519PW_MAC_ADDR);
arv_register_ath5k(ARV4519PW_ATH_ADDR, ARV4519PW_MAC_ADDR);
ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac);
gpio_request(ARV4519PW_RELAY, "relay");
gpio_direction_output(ARV4519PW_RELAY, 1);
gpio_export(ARV4519PW_RELAY, 0);
gpio_request(ARV4519PW_SWITCH_RESET, "switch");
gpio_set_value(ARV4519PW_SWITCH_RESET, 1);
gpio_export(ARV4519PW_SWITCH_RESET, 0);
}
MIPS_MACHINE(LANTIQ_MACH_ARV4519PW,
"ARV4519PW",
"ARV4519PW - Vodafone, Pirelli",
arv4519pw_init);
static void __init
arv4520pw_init(void)
{
#define ARV4520PW_EBU 0x400
#define ARV4520PW_USB 28
#define ARV4520PW_SWITCH_RESET 110
#define ARV4520PW_MAC_ADDR 0x3f0016
ltq_register_gpio_ebu(ARV4520PW_EBU);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4520pw_gpio_leds), arv4520pw_gpio_leds);
ltq_register_nor(&arv45xx_flash_data);
arv_load_nor(0x400000);
ltq_register_pci(&ltq_pci_data);
ltq_register_tapi();
arv45xx_register_ethernet();
arv_register_ethernet(ARV4520PW_MAC_ADDR);
xway_register_dwc(ARV4520PW_USB);
gpio_request(ARV4520PW_SWITCH_RESET, "switch");
@ -535,16 +614,18 @@ arv452Cpw_init(void)
#define ARV452CPW_RELAY1 31
#define ARV452CPW_RELAY2 107
#define ARV452CPW_SWITCH_RESET 110
#define ARV452CPW_MADWIFI_ADDR 0xb07f0400
#define ARV452CPW_ATH_ADDR 0x3f0400
#define ARV452CPW_MADWIFI_ADDR 0xb03f0400
#define ARV452CPW_MAC_ADDR 0x3f0016
ltq_register_gpio_ebu(ARV452CPW_EBU);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv452cpw_gpio_leds), arv452cpw_gpio_leds);
ltq_register_nor(&arv45xx_flash_data);
arv_load_nor(0x400000);
ltq_register_pci(&ltq_pci_data);
ltq_register_madwifi_eep(ARV452CPW_MADWIFI_ADDR);
xway_register_dwc(ARV452CPW_USB);
arv45xx_register_ethernet();
arv45xx_register_ath5k();
arv_register_ethernet(ARV452CPW_MAC_ADDR);
arv_register_ath5k(ARV452CPW_ATH_ADDR, ARV452CPW_MAC_ADDR);
ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac);
gpio_request(ARV452CPW_SWITCH_RESET, "switch");
gpio_set_value(ARV452CPW_SWITCH_RESET, 1);
@ -567,23 +648,21 @@ MIPS_MACHINE(LANTIQ_MACH_ARV452CPW,
static void __init
arv4525pw_init(void)
{
#define ARV4525PW_ATH_ADDR 0x3f0400
#define ARV4525PW_MADWIFI_ADDR 0xb03f0400
if (ltq_brn_boot)
ltq_register_nor(&arv45xx_brnboot_flash_data);
else
ltq_register_nor(&arv45xx_flash_data);
#define ARV4525PW_MAC_ADDR 0x3f0016
arv_load_nor(0x400000);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4525pw_gpio_leds), arv4525pw_gpio_leds);
gpio_request_array(arv4525pw_gpios, ARRAY_SIZE(arv4525pw_gpios));
gpio_export(ARV4525PW_RELAY, false);
gpio_export(ARV4525PW_PHYRESET, false);
ltq_pci_data.clock = PCI_CLOCK_INT;
ltq_register_pci(&ltq_pci_data);
ltq_register_madwifi_eep(ARV4525PW_MADWIFI_ADDR);
arv45xx_register_ath5k();
ltq_register_ath5k(arv45xx_ath5k_eeprom_data, arv45xx_ath5k_eeprom_mac);
arv_register_ath5k(ARV4525PW_ATH_ADDR, ARV4525PW_MADWIFI_ADDR);
ltq_register_ath5k(arv_ath5k_eeprom_data, arv_athxk_eeprom_mac);
ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII;
arv45xx_register_ethernet();
arv_register_ethernet(ARV4525PW_MAC_ADDR);
}
MIPS_MACHINE(LANTIQ_MACH_ARV4525PW,
@ -594,8 +673,10 @@ MIPS_MACHINE(LANTIQ_MACH_ARV4525PW,
static void __init
arv7525pw_init(void)
{
#define ARV7525P_MAC_ADDR 0x3f0016
arv_load_nor(0x400000);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv4525pw_gpio_leds), arv4525pw_gpio_leds);
ltq_register_nor(&arv7525_flash_data);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(arv7525pw_gpio_keys), arv7525pw_gpio_keys);
ltq_pci_data.clock = PCI_CLOCK_INT;
@ -605,7 +686,7 @@ arv7525pw_init(void)
ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII;
ltq_register_rt2x00("RT2860.eeprom");
ltq_register_tapi();
arv45xx_register_ethernet();
arv_register_ethernet(ARV7525P_MAC_ADDR);
}
MIPS_MACHINE(LANTIQ_MACH_ARV7525PW,
@ -618,17 +699,26 @@ arv7518pw_init(void)
{
#define ARV7518PW_EBU 0x2
#define ARV7518PW_USB 14
#define ARV7518PW_SWITCH_RESET 13
#define ARV7518PW_ATH_ADDR 0x7f0400
#define ARV7518PW_MAC_ADDR 0x7f0016
arv_load_nor(0x800000);
ltq_register_gpio_ebu(ARV7518PW_EBU);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv7518pw_gpio_leds), arv7518pw_gpio_leds);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(arv7518pw_gpio_keys), arv7518pw_gpio_keys);
ltq_register_nor(&arv75xx_flash_data);
ltq_register_pci(&ltq_pci_data);
ltq_register_tapi();
xway_register_dwc(ARV7518PW_USB);
arv75xx_register_ethernet();
//arv7518_register_ath9k(mac);
arv_register_ethernet(ARV7518PW_MAC_ADDR);
arv_register_ath9k(ARV7518PW_ATH_ADDR, ARV7518PW_MAC_ADDR);
ltq_register_ath9k(arv_ath9k_eeprom_data, arv_athxk_eeprom_mac);
ltq_pci_ath_fixup(14, arv_ath9k_eeprom_data);
gpio_request(ARV7518PW_SWITCH_RESET, "switch");
gpio_direction_output(ARV7518PW_SWITCH_RESET, 1);
gpio_export(ARV7518PW_SWITCH_RESET, 0);
}
MIPS_MACHINE(LANTIQ_MACH_ARV7518PW,
@ -642,17 +732,18 @@ arv752dpw22_init(void)
#define ARV752DPW22_EBU 0x2
#define ARV752DPW22_USB 100
#define ARV752DPW22_RELAY 101
#define ARV752DPW22_MAC_ADDR 0x7f0016
arv_load_nor(0x800000);
ltq_register_gpio_ebu(ARV752DPW22_EBU);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(arv752dpw22_gpio_leds), arv752dpw22_gpio_leds);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(arv752dpw22_gpio_keys), arv752dpw22_gpio_keys);
ltq_register_nor(&arv75xx_flash_data);
ltq_pci_data.irq[15] = (INT_NUM_IM3_IRL0 + 31);
ltq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2;
ltq_register_pci(&ltq_pci_data);
xway_register_dwc(ARV752DPW22_USB);
arv75xx_register_ethernet();
arv_register_ethernet(ARV752DPW22_MAC_ADDR);
gpio_request(ARV752DPW22_RELAY, "relay");
gpio_set_value(ARV752DPW22_RELAY, 1);

542
target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-bthomehubv2b.c Normal file
View File

@ -0,0 +1,542 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Andrej Vlašić
* Copyright (C) 2011 Luka Perkov
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/ath5k_platform.h>
#include <linux/ath9k_platform.h>
#include <linux/pci.h>
#include <linux/phy.h>
#include <linux/io.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <irq.h>
#include <lantiq_soc.h>
#include <lantiq_platform.h>
#include <dev-gpio-leds.h>
#include <dev-gpio-buttons.h>
#include "../machtypes.h"
//#include "dev-wifi-ath9k.h"
#include "devices.h"
#include "dev-dwc_otg.h"
#undef USE_BTHH_GPIO_INIT
// this reads certain data from u-boot if it's there
#define USE_UBOOT_ENV_DATA
#define UBOOT_ENV_OFFSET 0x040000
#define UBOOT_ENV_SIZE 0x010000
#ifdef NAND_ORGLAYOUT
// this is only here for reference
// definition of NAND flash area
static struct mtd_partition bthomehubv2b_nand_partitions[] =
{
{
.name = "ART",
.offset = 0x0000000,
.size = 0x0004000,
},
{
.name = "image1",
.offset = 0x0004000,
.size = 0x0E00000,
},
{
.name = "unknown1",
.offset = 0x0E04000,
.size = 0x00FC000,
},
{
.name = "image2",
.offset = 0x0F00000,
.size = 0x0E00000,
},
{
.name = "unknown2",
.offset = 0x1D00000,
.size = 0x0300000,
},
};
#endif
#ifdef NAND_KEEPOPENRG
// this allows both firmwares to co-exist
static struct mtd_partition bthomehubv2b_nand_partitions[] =
{
{
.name = "art",
.offset = 0x0000000,
.size = 0x0004000,
},
{
.name = "Image1",
.offset = 0x0004000,
.size = 0x0E00000,
},
{
.name = "linux",
.offset = 0x0E04000,
.size = 0x11fC000,
},
{
.name = "wholeflash",
.offset = 0x0000000,
.size = 0x2000000,
},
};
#endif
// this gives more jffs2 by overwriting openrg
static struct mtd_partition bthomehubv2b_nand_partitions[] =
{
{
.name = "art",
.offset = 0x0000000,
.size = 0x0004000,
},
{
.name = "linux",
.offset = 0x0004000,
.size = 0x1ffC000,
},
{
.name = "wholeflash",
.offset = 0x0000000,
.size = 0x2000000,
},
};
extern void __init xway_register_nand(struct mtd_partition *parts, int count);
// end BTHH_USE_NAND
static struct gpio_led
bthomehubv2b_gpio_leds[] __initdata = {
{ .name = "soc:orange:upgrading", .gpio = 213, },
{ .name = "soc:orange:phone", .gpio = 214, },
{ .name = "soc:blue:phone", .gpio = 215, },
{ .name = "soc:orange:wireless", .gpio = 216, },
{ .name = "soc:blue:wireless", .gpio = 217, },
{ .name = "soc:red:broadband", .gpio = 218, },
{ .name = "soc:orange:broadband", .gpio = 219, },
{ .name = "soc:blue:broadband", .gpio = 220, },
{ .name = "soc:red:power", .gpio = 221, },
{ .name = "soc:orange:power", .gpio = 222, },
{ .name = "soc:blue:power", .gpio = 223, },
};
static struct gpio_keys_button
bthomehubv2b_gpio_keys[] __initdata = {
{
.desc = "restart",
.type = EV_KEY,
.code = BTN_0,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 2,
.active_low = 1,
},
{
.desc = "findhandset",
.type = EV_KEY,
.code = BTN_1,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 15,
.active_low = 1,
},
{
.desc = "wps",
.type = EV_KEY,
.code = BTN_2,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 22,
.active_low = 1,
},
};
// definition of NOR flash area - as per original.
static struct mtd_partition bthomehubv2b_partitions[] =
{
{
.name = "uboot",
.offset = 0x000000,
.size = 0x040000,
},
{
.name = "uboot_env",
.offset = UBOOT_ENV_OFFSET,
.size = UBOOT_ENV_SIZE,
},
{
.name = "rg_conf_1",
.offset = 0x050000,
.size = 0x010000,
},
{
.name = "rg_conf_2",
.offset = 0x060000,
.size = 0x010000,
},
{
.name = "rg_conf_factory",
.offset = 0x070000,
.size = 0x010000,
},
};
/* nor flash */
/* bt homehubv2b has a very small nor flash */
/* so make it look for a small one, else we get a lot of alias chips identified - */
/* not a bug problem, but fills the logs. */
static struct resource bthhv2b_nor_resource =
MEM_RES("nor", LTQ_FLASH_START, 0x80000);
static struct platform_device ltq_nor = {
.name = "ltq_nor",
.resource = &bthhv2b_nor_resource,
.num_resources = 1,
};
static void __init bthhv2b_register_nor(struct physmap_flash_data *data)
{
ltq_nor.dev.platform_data = data;
platform_device_register(&ltq_nor);
}
static struct physmap_flash_data bthomehubv2b_flash_data = {
.nr_parts = ARRAY_SIZE(bthomehubv2b_partitions),
.parts = bthomehubv2b_partitions,
};
static struct ltq_pci_data ltq_pci_data = {
.clock = PCI_CLOCK_INT,
.gpio = PCI_GNT1 | PCI_REQ1,
.irq = { [14] = INT_NUM_IM0_IRL0 + 22, },
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_MII,
};
static char __init *get_uboot_env_var(char *haystack, int haystack_len, char *needle, int needle_len) {
int i;
for (i = 0; i <= haystack_len - needle_len; i++) {
if (memcmp(haystack + i, needle, needle_len) == 0) {
return haystack + i + needle_len;
}
}
return NULL;
}
/*
* bthomehubv2b_parse_hex_* are not uniq. in arm/orion there are also duplicates:
* dns323_parse_hex_*
* TODO: one day write a patch for this :)
*/
static int __init bthomehubv2b_parse_hex_nibble(char n) {
if (n >= '0' && n <= '9')
return n - '0';
if (n >= 'A' && n <= 'F')
return n - 'A' + 10;
if (n >= 'a' && n <= 'f')
return n - 'a' + 10;
return -1;
}
static int __init bthomehubv2b_parse_hex_byte(const char *b) {
int hi;
int lo;
hi = bthomehubv2b_parse_hex_nibble(b[0]);
lo = bthomehubv2b_parse_hex_nibble(b[1]);
if (hi < 0 || lo < 0)
return -1;
return (hi << 4) | lo;
}
static int __init bthomehubv2b_register_ethernet(void) {
u_int8_t addr[6];
int i;
char *mac = "01:02:03:04:05:06";
int gotmac = 0;
char *boardid = "BTHHV2B";
int gotboardid = 0;
char *uboot_env_page;
uboot_env_page = ioremap(LTQ_FLASH_START + UBOOT_ENV_OFFSET, UBOOT_ENV_SIZE);
if (uboot_env_page)
{
char *Data = NULL;
Data = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0ethaddr=", 9);
if (Data)
{
mac = Data;
}
Data = get_uboot_env_var(uboot_env_page, UBOOT_ENV_SIZE, "\0boardid=", 9);
if (Data)
boardid = Data;
}
else
{
printk("bthomehubv2b: Failed to get uboot_env_page");
}
if (!mac) {
goto error_fail;
}
if (!boardid) {
goto error_fail;
}
/* Sanity check the string we're looking at */
for (i = 0; i < 5; i++) {
if (*(mac + (i * 3) + 2) != ':') {
goto error_fail;
}
}
for (i = 0; i < 6; i++) {
int byte;
byte = bthomehubv2b_parse_hex_byte(mac + (i * 3));
if (byte < 0) {
goto error_fail;
}
addr[i] = byte;
}
if (gotmac)
printk("bthomehubv2b: Found ethernet MAC address: ");
else
printk("bthomehubv2b: using default MAC (pls set ethaddr in u-boot): ");
for (i = 0; i < 6; i++)
printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
memcpy(&ltq_eth_data.mac.sa_data, addr, 6);
ltq_register_etop(&ltq_eth_data);
//memcpy(&bthomehubv2b_ath5k_eeprom_mac, addr, 6);
//bthomehubv2b_ath5k_eeprom_mac[5]++;
if (gotboardid)
printk("bthomehubv2b: Board id is %s.", boardid);
else
printk("bthomehubv2b: Default Board id is %s.", boardid);
if (strncmp(boardid, "BTHHV2B", 7) == 0) {
// read in dev-wifi-ath9k
//memcpy(&bthomehubv2b_ath5k_eeprom_data, sx763_eeprom_data, ATH5K_PLAT_EEP_MAX_WORDS);
}
else {
printk("bthomehubv2b: Board id is unknown, fix uboot_env data.");
}
// should not unmap while we are using the ram?
if (uboot_env_page)
iounmap(uboot_env_page);
return 0;
error_fail:
if (uboot_env_page)
iounmap(uboot_env_page);
return -EINVAL;
}
#define PORTA2_HW_PASS1 0
#define PORTA2_HW_PASS1_SC14480 1
#define PORTA2_HW_PASS2 2
int porta2_hw_revision = -1;
EXPORT_SYMBOL(porta2_hw_revision);
#define LTQ_GPIO_OUT 0x00
#define LTQ_GPIO_IN 0x04
#define LTQ_GPIO_DIR 0x08
#define LTQ_GPIO_ALTSEL0 0x0C
#define LTQ_GPIO_ALTSEL1 0x10
#define LTQ_GPIO_OD 0x14
#define LTQ_GPIO_PUDSEL 0x1C
#define LTQ_GPIO_PUDEN 0x20
#ifdef USE_BTHH_GPIO_INIT
static void bthomehubv2b_board_prom_init(void)
{
int revision = 0;
unsigned int gpio = 0;
void __iomem *mem = ioremap(LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE*2);
#define DANUBE_GPIO_P0_OUT (unsigned short *)(mem + LTQ_GPIO_OUT)
#define DANUBE_GPIO_P0_IN (unsigned short *)(mem + LTQ_GPIO_IN)
#define DANUBE_GPIO_P0_DIR (unsigned short *)(mem + LTQ_GPIO_DIR)
#define DANUBE_GPIO_P0_ALTSEL0 (unsigned short *)(mem + LTQ_GPIO_ALTSEL0)
#define DANUBE_GPIO_P0_ALTSEL1 (unsigned short *)(mem + LTQ_GPIO_ALTSEL1)
#define DANUBE_GPIO_P1_OUT (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_OUT)
#define DANUBE_GPIO_P1_IN (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_IN)
#define DANUBE_GPIO_P1_DIR (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_DIR)
#define DANUBE_GPIO_P1_ALTSEL0 (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_ALTSEL0)
#define DANUBE_GPIO_P1_ALTSEL1 (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_ALTSEL1)
#define DANUBE_GPIO_P1_OD (unsigned short *)(mem + LTQ_GPIO_SIZE + LTQ_GPIO_OD)
printk("About to sense board using GPIOs at %8.8X\n", (unsigned int)mem);
/* First detect HW revision of the board. For that we need to set the GPIO
* lines according to table 7.2.1/7.2.2 in HSI */
*DANUBE_GPIO_P0_OUT = 0x0200;
*DANUBE_GPIO_P0_DIR = 0x2610;
*DANUBE_GPIO_P0_ALTSEL0 = 0x7812;
*DANUBE_GPIO_P0_ALTSEL1 = 0x0000;
*DANUBE_GPIO_P1_OUT = 0x7008;
*DANUBE_GPIO_P1_DIR = 0xF3AE;
*DANUBE_GPIO_P1_ALTSEL0 = 0x83A7;
*DANUBE_GPIO_P1_ALTSEL1 = 0x0400;
gpio = (*DANUBE_GPIO_P0_IN & 0xFFFF) |
((*DANUBE_GPIO_P1_IN & 0xFFFF) << 16);
revision |= (gpio & (1 << 27)) ? (1 << 0) : 0;
revision |= (gpio & (1 << 20)) ? (1 << 1) : 0;
revision |= (gpio & (1 << 8)) ? (1 << 2) : 0;
revision |= (gpio & (1 << 6)) ? (1 << 3) : 0;
revision |= (gpio & (1 << 5)) ? (1 << 4) : 0;
revision |= (gpio & (1 << 0)) ? (1 << 5) : 0;
porta2_hw_revision = revision;
printk("PORTA2: detected HW revision %d\n", revision);
/* Set GPIO lines according to HW revision. */
/* !!! Note that we are setting SPI_CS5 (GPIO 9) to be GPIO out with value
* of HIGH since the FXO does not use the SPI CS mechanism, it does it
* manually by controlling the GPIO line. We need the CS line to be disabled
* (HIGH) until needed since it will intefere with other devices on the SPI
* bus. */
*DANUBE_GPIO_P0_OUT = 0x0200;
/*
* During the manufacturing process a different machine takes over uart0
* so set it as input (so it wouldn't drive the line)
*/
#define cCONFIG_SHC_BT_MFG_TEST 0
*DANUBE_GPIO_P0_DIR = 0x2671 | (cCONFIG_SHC_BT_MFG_TEST ? 0 : (1 << 12));
if (revision == PORTA2_HW_PASS1_SC14480 || revision == PORTA2_HW_PASS2)
*DANUBE_GPIO_P0_ALTSEL0 = 0x7873;
else
*DANUBE_GPIO_P0_ALTSEL0 = 0x3873;
*DANUBE_GPIO_P0_ALTSEL1 = 0x0001;
//###################################################################################
// Register values before patch
// P1_ALTSEL0 = 0x83A7
// P1_ALTSEL1 = 0x0400
// P1_OU T = 0x7008
// P1_DIR = 0xF3AE
// P1_OD = 0xE3Fc
printk("\nApplying Patch for CPU1 IRQ Issue\n");
*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<12); // switch P1.12 (GPIO28) to GPIO functionality
*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<12); // switch P1.12 (GPIO28) to GPIO functionality
*DANUBE_GPIO_P1_OUT &= ~(1<<12); // set P1.12 (GPIO28) to 0
*DANUBE_GPIO_P1_DIR |= (1<<12); // configure P1.12 (GPIO28) as output
*DANUBE_GPIO_P1_OD |= (1<<12); // activate Push/Pull mode
udelay(100); // wait a little bit (100us)
*DANUBE_GPIO_P1_OD &= ~(1<<12); // switch back from Push/Pull to Open Drain
// important: before! setting output to 1 (3,3V) the mode must be switched
// back to Open Drain because the reset pin of the SC14488 is internally
// pulled to 1,8V
*DANUBE_GPIO_P1_OUT |= (1<<12); // set output P1.12 (GPIO28) to 1
// Register values after patch, should be the same as before
// P1_ALTSEL0 = 0x83A7
// P1_ALTSEL1 = 0x0400
// P1_OUT = 0x7008
// P1_DIR = 0xF3AE
// P1_OD = 0xE3Fc
//###################################################################################
*DANUBE_GPIO_P1_OUT = 0x7008;
*DANUBE_GPIO_P1_DIR = 0xEBAE | (revision == PORTA2_HW_PASS2 ? 0x1000 : 0);
*DANUBE_GPIO_P1_ALTSEL0 = 0x8BA7;
*DANUBE_GPIO_P1_ALTSEL1 = 0x0400;
iounmap(mem);
}
#endif
static void __init bthomehubv2b_init(void) {
#define bthomehubv2b_USB 13
// read the board version
#ifdef USE_BTHH_GPIO_INIT
bthomehubv2b_board_prom_init();
#endif
// register extra GPPOs used by LEDs as GPO 0x200+
ltq_register_gpio_stp();
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(bthomehubv2b_gpio_leds), bthomehubv2b_gpio_leds);
bthhv2b_register_nor(&bthomehubv2b_flash_data);
xway_register_nand(bthomehubv2b_nand_partitions, ARRAY_SIZE(bthomehubv2b_nand_partitions));
ltq_register_pci(&ltq_pci_data);
ltq_register_tapi();
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(bthomehubv2b_gpio_keys), bthomehubv2b_gpio_keys);
// ltq_register_ath9k();
xway_register_dwc(bthomehubv2b_USB);
bthomehubv2b_register_ethernet();
}
MIPS_MACHINE(LANTIQ_MACH_BTHOMEHUBV2BOPENRG,
"BTHOMEHUBV2BOPENRG",
"BTHOMEHUBV2B - BT Homehub V2.0 Type B with OpenRG image retained",
bthomehubv2b_init);
MIPS_MACHINE(LANTIQ_MACH_BTHOMEHUBV2B,
"BTHOMEHUBV2B",
"BTHOMEHUBV2B - BT Homehub V2.0 Type B",
bthomehubv2b_init);

0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-easy50601.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-easy50601.c
View File

0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-easy50712.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-easy50712.c
View File

114
target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-fritz_ar9.c Normal file
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@ -0,0 +1,114 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/phy.h>
#include <linux/spi/spi_gpio.h>
#include <linux/spi/flash.h>
#include <lantiq_soc.h>
#include <irq.h>
#include "../machtypes.h"
#include "devices.h"
#include "dev-ifxhcd.h"
#include "dev-gpio-leds.h"
#include "dev-gpio-buttons.h"
static struct mtd_partition fritz7320_partitions[] = {
{
.name = "urlader",
.offset = 0x0,
.size = 0x20000,
},
{
.name = "linux",
.offset = 0x20000,
.size = 0xf60000,
},
{
.name = "tffs (1)",
.offset = 0xf80000,
.size = 0x40000,
},
{
.name = "tffs (2)",
.offset = 0xfc0000,
.size = 0x40000,
},
};
static struct physmap_flash_data fritz7320_flash_data = {
.nr_parts = ARRAY_SIZE(fritz7320_partitions),
.parts = fritz7320_partitions,
};
static struct gpio_led
fritz7320_gpio_leds[] __initdata = {
{ .name = "soc:green:power", .gpio = 44, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:internet", .gpio = 47, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:dect", .gpio = 38, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:wlan", .gpio = 37, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:dual1", .gpio = 35, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:red:dual2", .gpio = 45, .active_low = 1, .default_trigger = "default-on" },
};
static struct gpio_keys_button
fritz7320_gpio_keys[] __initdata = {
{
.desc = "wifi",
.type = EV_KEY,
.code = BTN_0,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 1,
.active_low = 1,
},
{
.desc = "dect",
.type = EV_KEY,
.code = BTN_1,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 2,
.active_low = 1,
},
};
static struct ltq_pci_data ltq_pci_data = {
.clock = PCI_CLOCK_INT,
.gpio = PCI_GNT1 | PCI_REQ1,
.irq = {
[14] = INT_NUM_IM0_IRL0 + 22,
},
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_RMII,
};
static int usb_pins[2] = { 50, 51 };
static void __init fritz7320_init(void)
{
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(fritz7320_gpio_keys), fritz7320_gpio_keys);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(fritz7320_gpio_leds), fritz7320_gpio_leds);
ltq_register_pci(&ltq_pci_data);
ltq_register_etop(&ltq_eth_data);
ltq_register_nor(&fritz7320_flash_data);
xway_register_hcd(usb_pins);
}
MIPS_MACHINE(LANTIQ_MACH_FRITZ7320,
"FRITZ7320",
"FRITZ!BOX 7320",
fritz7320_init);

163
target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-fritz_vr9.c Normal file
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@ -0,0 +1,163 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/phy.h>
#include <linux/spi/spi_gpio.h>
#include <linux/spi/flash.h>
#include <lantiq_soc.h>
#include <irq.h>
#include "../machtypes.h"
#include "devices.h"
#include "dev-ifxhcd.h"
#include "dev-gpio-leds.h"
#include "dev-gpio-buttons.h"
static struct mtd_partition fritz3370_partitions[] = {
{
.name = "linux",
.offset = 0x0,
.size = 0x400000,
},
{
.name = "filesystem",
.offset = 0x400000,
.size = 0x3000000,
},
{
.name = "reserved-kernel",
.offset = 0x3400000,
.size = 0x400000,
},
{
.name = "reserved",
.offset = 0x3800000,
.size = 0x3000000,
},
{
.name = "config",
.offset = 0x6800000,
.size = 0x200000,
},
{
.name = "nand-filesystem",
.offset = 0x6a00000,
.size = 0x1600000,
},
};
static struct mtd_partition spi_flash_partitions[] = {
{
.name = "urlader",
.offset = 0x0,
.size = 0x20000,
},
{
.name = "tffs",
.offset = 0x20000,
.size = 0x10000,
},
{
.name = "tffs",
.offset = 0x30000,
.size = 0x10000,
},
};
static struct gpio_led
fritz3370_gpio_leds[] __initdata = {
{ .name = "soc:green:1", .gpio = 32, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:red:2", .gpio = 33, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:red:3", .gpio = 34, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:4", .gpio = 35, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:5", .gpio = 36, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:green:6", .gpio = 47, .active_low = 1, .default_trigger = "default-on" },
};
static struct gpio_keys_button
fritz3370_gpio_keys[] __initdata = {
{
.desc = "wifi",
.type = EV_KEY,
.code = BTN_0,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 29,
.active_low = 1,
},
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_RMII,
};
static int usb_pins[2] = { 5, 14 };
#define SPI_GPIO_MRST 16
#define SPI_GPIO_MTSR 17
#define SPI_GPIO_CLK 18
#define SPI_GPIO_CS0 10
static struct spi_gpio_platform_data spi_gpio_data = {
.sck = SPI_GPIO_CLK,
.mosi = SPI_GPIO_MTSR,
.miso = SPI_GPIO_MRST,
.num_chipselect = 2,
};
static struct platform_device spi_gpio_device = {
.name = "spi_gpio",
.dev.platform_data = &spi_gpio_data,
};
static struct flash_platform_data spi_flash_data = {
.name = "SPL",
.parts = spi_flash_partitions,
.nr_parts = ARRAY_SIZE(spi_flash_partitions),
};
static struct spi_board_info spi_flash __initdata = {
.modalias = "m25p80",
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000,
.mode = SPI_MODE_3,
.chip_select = 0,
.controller_data = (void *) SPI_GPIO_CS0,
.platform_data = &spi_flash_data
};
static void __init
spi_gpio_init(void)
{
spi_register_board_info(&spi_flash, 1);
platform_device_register(&spi_gpio_device);
}
static void __init fritz3370_init(void)
{
spi_gpio_init();
platform_device_register_simple("pcie-xway", 0, NULL, 0);
xway_register_nand(fritz3370_partitions, ARRAY_SIZE(fritz3370_partitions));
xway_register_hcd(usb_pins);
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(fritz3370_gpio_leds), fritz3370_gpio_leds);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL,
ARRAY_SIZE(fritz3370_gpio_keys), fritz3370_gpio_keys);
ltq_register_vrx200(&ltq_eth_data);
}
MIPS_MACHINE(LANTIQ_MACH_FRITZ3370,
"FRITZ3370",
"FRITZ!BOX 3370",
fritz3370_init);

166
target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-gigasx76x.c Normal file
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@ -0,0 +1,166 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2011 Andrej Vlašić
* Copyright (C) 2011 Luka Perkov
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/ath5k_platform.h>
#include <linux/pci.h>
#include <linux/phy.h>
#include <linux/io.h>
#include <linux/if_ether.h>
#include <linux/etherdevice.h>
#include <linux/string.h>
#include <irq.h>
#include <lantiq_soc.h>
#include <lantiq_platform.h>
#include <dev-gpio-leds.h>
#include <dev-gpio-buttons.h>
#include "../machtypes.h"
#include "dev-wifi-athxk.h"
#include "devices.h"
#include "dev-dwc_otg.h"
#include "mach-gigasx76x.h"
static u8 ltq_ethaddr[6] = { 0 };
static int __init setup_ethaddr(char *str)
{
if (!mac_pton(str, ltq_ethaddr))
memset(ltq_ethaddr, 0, 6);
return 0;
}
__setup("ethaddr=", setup_ethaddr);
enum {
UNKNOWN = 0,
SX761,
SX762,
SX763,
};
static u8 board = SX763;
static int __init setup_board(char *str)
{
if (!strcmp(str, "sx761"))
board = SX761;
else if (!strcmp(str, "sx762"))
board = SX762;
else if (!strcmp(str, "sx763"))
board = SX763;
else
board = UNKNOWN;
return 0;
}
__setup("board=", setup_board);
static struct mtd_partition gigasx76x_partitions[] =
{
{
.name = "uboot",
.offset = 0x0,
.size = 0x10000,
},
{
.name = "uboot_env",
.offset = 0x10000,
.size = 0x10000,
},
{
.name = "linux",
.offset = 0x20000,
.size = 0x7e0000,
},
};
static struct gpio_led
gigasx76x_gpio_leds[] __initdata = {
{ .name = "soc:green:voip", .gpio = 216, },
{ .name = "soc:green:adsl", .gpio = 217, },
{ .name = "soc:green:usb", .gpio = 218, },
{ .name = "soc:green:wifi", .gpio = 219, },
{ .name = "soc:green:phone2", .gpio = 220, },
{ .name = "soc:green:phone1", .gpio = 221, },
{ .name = "soc:green:line", .gpio = 222, },
{ .name = "soc:green:online", .gpio = 223, },
};
static struct gpio_keys_button
gigasx76x_gpio_keys[] __initdata = {
{
.desc = "wps",
.type = EV_KEY,
.code = KEY_WPS_BUTTON,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 22,
.active_low = 1,
},
{
.desc = "reset",
.type = EV_KEY,
.code = BTN_0,
.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
.gpio = 14,
.active_low = 0,
},
};
static struct physmap_flash_data gigasx76x_flash_data = {
.nr_parts = ARRAY_SIZE(gigasx76x_partitions),
.parts = gigasx76x_partitions,
};
static struct ltq_pci_data ltq_pci_data = {
.clock = PCI_CLOCK_INT,
.gpio = PCI_GNT1 | PCI_REQ1,
.irq = { [14] = INT_NUM_IM0_IRL0 + 22, },
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_MII,
};
static void __init gigasx76x_init(void)
{
#define GIGASX76X_USB 29
ltq_register_gpio_stp();
ltq_register_nor(&gigasx76x_flash_data);
ltq_register_pci(&ltq_pci_data);
ltq_register_tapi();
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(gigasx76x_gpio_leds), gigasx76x_gpio_leds);
ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(gigasx76x_gpio_keys), gigasx76x_gpio_keys);
xway_register_dwc(GIGASX76X_USB);
if (!is_valid_ether_addr(ltq_ethaddr))
random_ether_addr(ltq_ethaddr);
memcpy(&ltq_eth_data.mac.sa_data, ltq_ethaddr, 6);
ltq_register_etop(&ltq_eth_data);
if (board == SX762)
ltq_register_ath5k(sx762_eeprom_data, ltq_ethaddr);
else
ltq_register_ath5k(sx763_eeprom_data, ltq_ethaddr);
}
MIPS_MACHINE(LANTIQ_MACH_GIGASX76X,
"GIGASX76X",
"GIGASX76X - Gigaset SX761,SX762,SX763",
gigasx76x_init);

9
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-gigasx76x.h → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-gigasx76x.h
View File

@ -8,9 +8,12 @@
*
*/
#ifndef _MACH_GIGASX76X_H__
#define _MACH_GIGASX76X_H__
static u16 sx763_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]=
{
0x5aa5,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100,
0x0013,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100,
0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xf165,0x7fbe,0x0003,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
@ -108,7 +111,7 @@ static u16 sx763_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]=
static u16 sx762_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]=
{
0x5aa5,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100,
0x001a,0x168c,0x0200,0x0001,0x0000,0x5001,0x0000,0x2051,0x2051,0x1c0a,0x0100,
0x0000,0x01c2,0x0002,0xc606,0x0001,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xf165,0x7fbe,0x0003,0x0000,
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
@ -201,3 +204,5 @@ static u16 sx762_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS]=
0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,
0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,
0xffff,0xffff};
#endif

34
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-netgear.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-netgear.c
View File

@ -14,6 +14,7 @@
#include <linux/input.h>
#include <linux/phy.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <lantiq_soc.h>
#include <irq.h>
@ -33,11 +34,38 @@ static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_MII,
};
struct spi_board_info spi_info = {
static struct mtd_partition easy98000_nor_partitions[] =
{
{
.name = "uboot",
.offset = 0x0,
.size = 0x40000,
},
{
.name = "uboot_env",
.offset = 0x40000,
.size = 0x40000, /* 2 sectors for redundant env. */
},
{
.name = "linux",
.offset = 0x80000,
.size = 0xF80000, /* map only 16 MiB */
},
};
static struct flash_platform_data easy98000_spi_flash_platform_data = {
.name = "sflash",
.parts = easy98000_nor_partitions,
.nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
};
static struct spi_board_info spi_info __initdata = {
.modalias = "m25p80",
.bus_num = 0,
.chip_select = 3,
.max_speed_hz = 25000000,
.modalias = "mx25l12805d",
.max_speed_hz = 10 * 1000 * 1000,
.mode = SPI_MODE_3,
.platform_data = &easy98000_spi_flash_platform_data
};
struct ltq_spi_platform_data ltq_spi_data = {

106
target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-p2601hnf1.c Normal file
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@ -0,0 +1,106 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/gpio_buttons.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/etherdevice.h>
#include <linux/mdio-gpio.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <lantiq_soc.h>
#include <lantiq_platform.h>
#include "../machtypes.h"
#include "devices.h"
#include "../dev-gpio-leds.h"
#include "dev-dwc_otg.h"
static struct mtd_partition p2601hnf1_partitions[] __initdata =
{
{
.name = "uboot",
.offset = 0x0,
.size = 0x20000,
},
/* {
.name = "uboot_env",
.offset = 0x20000,
.size = 0x20000,
},
*/ {
.name = "linux",
.offset = 0x020000,
.size = 0xfc0000,
},
{
.name = "board_config",
.offset = 0xfe0000,
.size = 0x20000,
},
};
static struct physmap_flash_data p2601hnf1_flash_data __initdata = {
.nr_parts = ARRAY_SIZE(p2601hnf1_partitions),
.parts = p2601hnf1_partitions,
};
static struct gpio_led p2601hnf1_leds_gpio[] __initdata = {
{ .name = "soc:red:power", .gpio = 29, .active_low = 1, .default_trigger = "default-off" },
{ .name = "soc:yellow:phone", .gpio = 64, .active_low = 1, .default_trigger = "default-off" },
{ .name = "soc:green:phone", .gpio = 65, .active_low = 1, .default_trigger = "default-off" },
{ .name = "soc:yellow:wlan", .gpio = 66, .active_low = 1, .default_trigger = "default-off" },
{ .name = "soc:green:power", .gpio = 67, .active_low = 1, .default_trigger = "default-on" },
{ .name = "soc:red:internet", .gpio = 68, .active_low = 1, .default_trigger = "default-off" },
{ .name = "soc:green:internet", .gpio = 69, .active_low = 1, .default_trigger = "default-off" },
{ .name = "soc:green:dsl", .gpio = 70, .active_low = 1, .default_trigger = "default-off" },
{ .name = "soc:green:wlan", .gpio = 71, .active_low = 1, .default_trigger = "default-off" },
};
static struct gpio_button
p2601hnf1_gpio_buttons[] /*__initdata*/ = {
{ .desc = "reset", .type = EV_KEY, .code = BTN_0, .threshold = 3, .gpio = 53, .active_low = 1, },
{ .desc = "wlan", .type = EV_KEY, .code = BTN_1, .threshold = 1, .gpio = 54, .active_low = 1, },
};
static struct ltq_eth_data ltq_eth_data = {
.mii_mode = PHY_INTERFACE_MODE_RMII,
};
static void __init
p2601hnf1_init(void)
{
#define P2601HNF1_USB 9
ltq_register_gpio_stp();
ltq_add_device_gpio_leds(-1, ARRAY_SIZE(p2601hnf1_leds_gpio), p2601hnf1_leds_gpio);
ltq_register_gpio_buttons(p2601hnf1_gpio_buttons, ARRAY_SIZE(p2601hnf1_gpio_buttons));
ltq_register_nor(&p2601hnf1_flash_data);
ltq_register_etop(&ltq_eth_data);
xway_register_dwc(P2601HNF1_USB);
// enable the ethernet ports on the SoC
// ltq_w32((ltq_r32(LTQ_GPORT_P0_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P0_CTL);
// ltq_w32((ltq_r32(LTQ_GPORT_P1_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P1_CTL);
// ltq_w32((ltq_r32(LTQ_GPORT_P2_CTL) & ~(1 << 17)) | (1 << 18), LTQ_GPORT_P2_CTL);
}
MIPS_MACHINE(LANTIQ_MACH_P2601HNF1,
"P2601HNF1",
"ZyXEL P-2601HN-F1",
p2601hnf1_init);

0
target/linux/lantiq/files-3.1/arch/mips/lantiq/xway/mach-wbmr.c → target/linux/lantiq/files-3.2/arch/mips/lantiq/xway/mach-wbmr.c
View File

90
target/linux/lantiq/image/Makefile
View File

@ -1,5 +1,5 @@
#
# Copyright (C) 2010 OpenWrt.org
# Copyright (C) 2010-2012 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
@ -12,6 +12,7 @@ JFFS2_BLOCKSIZE = 64k 128k 256k
ase_cmdline=-console=ttyLTQ0,115200 rootfstype=squashfs,jffs2
xway_cmdline=-console=ttyLTQ1,115200 rootfstype=squashfs,jffs2
falcon_cmdline=-console=ttyLTQ0,115200 rootfstype=squashfs,jffs2
sx76x_cmdline=console=ttyLTQ1,115200 rootfstype=squashfs,jffs2
define CompressLzma
$(STAGING_DIR_HOST)/bin/lzma e $(1) $(2)
@ -35,12 +36,23 @@ define MkImageLzma
-d $(KDIR)/vmlinux-$(1).lzma $(KDIR)/uImage-$(1)
endef
define MkImageEVA
lzma2eva 0x80002000 0x80002000 $(KDIR)/vmlinux-$(1).lzma $(KDIR)/$(1).eva.prealign
dd if=$(KDIR)/$(1).eva.prealign of=$(KDIR)/$(1).eva bs=64k conv=sync
cat ./eva.dummy.squashfs >> $(KDIR)/$(1).eva
endef
define Image/Build/squashfs
cat $(KDIR)/uImage-$(2) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image
$(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image)
$(if $(3),$(call MkBrnImage,$(3),$(4),$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3)-brnImage,$(2),$(1),$(5)))
endef
define Image/BuildEVA/squashfs
cat $(KDIR)/$(2).eva $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image.eva
$(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image.eva)
endef
define Image/Build/jffs2-64k
dd if=$(KDIR)/uImage-$(2) of=$(KDIR)/uImage-$(2)-$(1) bs=64k conv=sync
cat $(KDIR)/uImage-$(2)-$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image
@ -62,6 +74,12 @@ define Image/BuildKernel/Template
$(CP) $(KDIR)/uImage-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage
endef
define Image/BuildKernelEVA/Template
$(call PatchKernelLzma,$(1),$(if $(2),$(2) machtype=$(1),))
$(call MkImageEVA,$(1))
$(CP) $(KDIR)/$(1).eva $(BIN_DIR)/$(IMG_PREFIX)-$(1).eva
endef
ifeq ($(CONFIG_TARGET_lantiq_danube),y)
define Image/BuildKernel/Profile/EASY50712
$(call Image/BuildKernel/Template,EASY50712,$(xway_cmdline))
@ -103,6 +121,14 @@ define Image/Build/Profile/ARV4518PW
$(call Image/Build/$(1),$(1),ARV4518PW)
endef
define Image/BuildKernel/Profile/ARV4519PW
$(call Image/BuildKernel/Template,ARV4519PW,$(xway_cmdline))
endef
define Image/Build/Profile/ARV4519PW
$(call Image/Build/$(1),$(1),ARV4519PW,BRNDA4519,0x12345678,memsize=32)
endef
define Image/BuildKernel/Profile/ARV4520PW
$(call Image/BuildKernel/Template,ARV4520PW,$(xway_cmdline))
endef
@ -140,7 +166,7 @@ define Image/BuildKernel/Profile/ARV7518PW
endef
define Image/Build/Profile/ARV7518PW
$(call Image/Build/$(1),$(1),ARV7518PW)
$(call Image/Build/$(1),$(1),ARV7518PW,BRNDA7519,0x12345678,memsize=64)
endef
define Image/BuildKernel/Profile/ARV752DPW
@ -160,13 +186,29 @@ define Image/Build/Profile/ARV752DPW22
endef
define Image/BuildKernel/Profile/GIGASX76X
$(call Image/BuildKernel/Template,GIGASX76X,$(xway_cmdline))
$(call Image/BuildKernel/Template,GIGASX76X,$(sx76x_cmdline))
endef
define Image/Build/Profile/GIGASX76X
$(call Image/Build/$(1),$(1),GIGASX76X)
endef
define Image/BuildKernel/Profile/BTHOMEHUBV2B
$(call Image/BuildKernel/Template,BTHOMEHUBV2B,$(xway_cmdline))
endef
define Image/Build/Profile/BTHOMEHUBV2B
$(call Image/Build/$(1),$(1),BTHOMEHUBV2B)
endef
define Image/BuildKernel/Profile/BTHOMEHUBV2BOPENRG
$(call Image/BuildKernel/Template,BTHOMEHUBV2BOPENRG,$(xway_cmdline))
endef
define Image/Build/Profile/BTHOMEHUBV2BOPENRG
$(call Image/Build/$(1),$(1),BTHOMEHUBV2BOPENRG)
endef
define Image/BuildKernel/Profile/Generic
$(call Image/BuildKernel/Template,EASY4010,$(xway_cmdline))
$(call Image/BuildKernel/Template,EASY50712,$(xway_cmdline))
@ -174,6 +216,7 @@ define Image/BuildKernel/Profile/Generic
$(call Image/BuildKernel/Template,ARV3527P,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV4510PW,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV4518PW,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV4519PW,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV4520PW,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV452CPW,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV4525PW,$(xway_cmdline))
@ -182,6 +225,8 @@ define Image/BuildKernel/Profile/Generic
$(call Image/BuildKernel/Template,ARV752DPW,$(xway_cmdline))
$(call Image/BuildKernel/Template,ARV752DPW22,$(xway_cmdline))
$(call Image/BuildKernel/Template,GIGASX76X,$(xway_cmdline))
$(call Image/BuildKernel/Template,BTHOMEHUBV2B,$(xway_cmdline))
$(call Image/BuildKernel/Template,BTHOMEHUBV2BOPENRG,$(xway_cmdline))
$(call Image/BuildKernel/Template,NONE)
endef
@ -192,14 +237,17 @@ define Image/Build/Profile/Generic
$(call Image/Build/$(1),$(1),ARV3527P)
$(call Image/Build/$(1),$(1),ARV4510PW)
$(call Image/Build/$(1),$(1),ARV4518PW)
$(call Image/Build/$(1),$(1),ARV4519PW,BRNDA4519,0x12345678,memsize=32)
$(call Image/Build/$(1),$(1),ARV4520PW)
$(call Image/Build/$(1),$(1),ARV452CPW)
$(call Image/Build/$(1),$(1),ARV4525PW)
$(call Image/Build/$(1),$(1),ARV4525PW,BRNDTW502,0x12345678,memsize=32)
$(call Image/Build/$(1),$(1),ARV7525PW)
$(call Image/Build/$(1),$(1),ARV7518PW)
$(call Image/Build/$(1),$(1),ARV7518PW,BRNDA7519,0x12345678,memsize=32)
$(call Image/Build/$(1),$(1),ARV752DPW)
$(call Image/Build/$(1),$(1),ARV752DPW22)
$(call Image/Build/$(1),$(1),GIGASX76X)
$(call Image/Build/$(1),$(1),BTHOMEHUBV2B)
$(call Image/Build/$(1),$(1),BTHOMEHUBV2BOPENRG)
$(call Image/Build/$(1),$(1),NONE)
$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs
endef
@ -222,15 +270,25 @@ define Image/Build/Profile/DGN3500B
$(call Image/Build/$(1),$(1),DGN3500B)
endef
define Image/BuildKernel/Profile/FRITZ7320
$(call Image/BuildKernelEVA/Template,FRITZ7320,$(xway_cmdline))
endef
define Image/Build/Profile/FRITZ7320
$(call Image/BuildEVA/$(1),$(1),FRITZ7320)
endef
define Image/BuildKernel/Profile/Generic
$(call Image/BuildKernel/Template,WBMR,$(xway_cmdline))
$(call Image/BuildKernel/Template,DGN3500B,$(xway_cmdline))
$(call Image/BuildKernelEVA/Template,FRITZ7320,$(xway_cmdline))
$(call Image/BuildKernel/Template,NONE)
endef
define Image/Build/Profile/Generic
$(call Image/Build/$(1),$(1),WBMR)
$(call Image/Build/$(1),$(1),DGN3500B)
$(call Image/BuildEVA/$(1),$(1),FRITZ7320)
$(call Image/Build/$(1),$(1),NONE)
$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs
endef
@ -288,6 +346,28 @@ define Image/Build/Profile/Generic
endef
endif
ifeq ($(CONFIG_TARGET_lantiq_vr9),y)
define Image/BuildKernel/Profile/FRITZ3370
$(call Image/BuildKernel/Template,FRITZ3370,$(xway_cmdline))
$(call Image/BuildKernelEVA/Template,FRITZ3370,$(xway_cmdline))
endef
define Image/Build/Profile/FRITZ3370
$(call Image/Build/$(1),$(1),FRITZ3370)
endef
define Image/BuildKernel/Profile/Generic
$(call Image/BuildKernel/Template,FRITZ3370,$(xway_cmdline))
$(call Image/BuildKernel/Template,NONE)
endef
define Image/Build/Profile/Generic
$(call Image/Build/$(1),$(1),FRITZ3370)
$(call Image/Build/$(1),$(1),NONE)
$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs
endef
endif
define Image/BuildKernel
$(call Image/BuildKernel/Profile/$(PROFILE))
endef

BIN
target/linux/lantiq/image/eva.dummy.squashfs Normal file
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Binary file not shown.

35
target/linux/lantiq/modules.mk
View File

@ -29,7 +29,7 @@ USB_MENU:=USB Support
define KernelPackage/usb-dwc-otg
TITLE:=Synopsis DWC_OTG support
SUBMENU:=$(USB_MENU)
DEPENDS+=@(TARGET_lantiq_danube||TARGET_lantiq_ar9||TARGET_lantiq_vr9) +kmod-usb-core
DEPENDS+=@(TARGET_lantiq_danube||TARGET_lantiq_ar9) +kmod-usb-core
KCONFIG:=CONFIG_DWC_OTG \
CONFIG_DWC_OTG_DEBUG=n \
CONFIG_DWC_OTG_LANTIQ=y \
@ -45,6 +45,39 @@ endef
$(eval $(call KernelPackage,usb-dwc-otg))
define KernelPackage/usb-ifxhcd
TITLE:=IFXHCD usb driver
SUBMENU:=$(USB_MENU)
DEPENDS+=@(TARGET_lantiq_vr9||TARGET_lantiq_ar9) +kmod-usb-core
ifeq ($(CONFIG_TARGET_lantiq_ar9),)
KCONFIG:=CONFIG_USB_HOST_IFX \
CONFIG_USB_HOST_IFX_B=y \
CONFIG_IFX_VR9=y \
CONFIG_IFX_AR9=n \
CONFIG_USB_HOST_IFX_FORCE_USB11=n \
CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST=n \
CONFIG_USB_HOST_IFX_WITH_ISO=n \
CONFIG_USB_HOST_IFX_UNALIGNED_ADJ=y
else
KCONFIG:=CONFIG_USB_HOST_IFX \
CONFIG_USB_HOST_IFX_B=y \
CONFIG_IFX_AR9=y \
CONFIG_IFX_VR9=n \
CONFIG_USB_HOST_IFX_FORCE_USB11=n \
CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST=n \
CONFIG_USB_HOST_IFX_WITH_ISO=n \
CONFIG_USB_HOST_IFX_UNALIGNED_ADJ=y
endif
FILES:=$(LINUX_DIR)/drivers/usb/ifxhcd/ifxusb_host.ko
AUTOLOAD:=$(call AutoLoad,50,ifxusb_host)
endef
define KernelPackage/usb-ifxhcd/description
Kernel support for Synopsis USB on XWAY
endef
$(eval $(call KernelPackage,usb-ifxhcd))
I2C_FALCON_MODULES:= \
CONFIG_I2C_FALCON:drivers/i2c/busses/i2c-falcon

144
target/linux/lantiq/patches-3.2/0001-GPIO-add-bindings-for-managed-devices.patch Normal file
View File

@ -0,0 +1,144 @@
From 282f1ca84b35f3be68abc4fd8b52e229f3cb6bb7 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 13:23:53 +0100
Subject: [PATCH 01/70] GPIO: add bindings for managed devices
This patch adds 2 functions that allow managed devices to request GPIOs.
These GPIOs will then be managed by drivers/base/devres.c.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---
drivers/gpio/Makefile | 2 +-
drivers/gpio/devres.c | 90 ++++++++++++++++++++++++++++++++++++++++++++
include/asm-generic/gpio.h | 4 ++
3 files changed, 95 insertions(+), 1 deletions(-)
create mode 100644 drivers/gpio/devres.c
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4e018d6..76dbd3f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -2,7 +2,7 @@
ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG
-obj-$(CONFIG_GPIOLIB) += gpiolib.o
+obj-$(CONFIG_GPIOLIB) += gpiolib.o devres.o
# Device drivers. Generally keep list sorted alphabetically
obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
diff --git a/drivers/gpio/devres.c b/drivers/gpio/devres.c
new file mode 100644
index 0000000..3dd2939
--- /dev/null
+++ b/drivers/gpio/devres.c
@@ -0,0 +1,90 @@
+/*
+ * drivers/gpio/devres.c - managed gpio resources
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is based on kernel/irq/devres.c
+ *
+ * Copyright (c) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/device.h>
+#include <linux/gfp.h>
+
+static void devm_gpio_release(struct device *dev, void *res)
+{
+ unsigned *gpio = res;
+
+ gpio_free(*gpio);
+}
+
+static int devm_gpio_match(struct device *dev, void *res, void *data)
+{
+ unsigned *this = res, *gpio = data;
+
+ return *this == *gpio;
+}
+
+/**
+ * devm_gpio_request - request a gpio for a managed device
+ * @dev: device to request the gpio for
+ * @gpio: gpio to allocate
+ * @label: the name of the requested gpio
+ *
+ * Except for the extra @dev argument, this function takes the
+ * same arguments and performs the same function as
+ * gpio_request(). GPIOs requested with this function will be
+ * automatically freed on driver detach.
+ *
+ * If an GPIO allocated with this function needs to be freed
+ * separately, devm_gpio_free() must be used.
+ */
+
+int devm_gpio_request(struct device *dev, unsigned gpio, const char *label)
+{
+ unsigned *dr;
+ int rc;
+
+ dr = devres_alloc(devm_gpio_release, sizeof(unsigned), GFP_KERNEL);
+ if (!dr)
+ return -ENOMEM;
+
+ rc = gpio_request(gpio, label);
+ if (rc) {
+ devres_free(dr);
+ return rc;
+ }
+
+ *dr = gpio;
+ devres_add(dev, dr);
+
+ return 0;
+}
+EXPORT_SYMBOL(devm_gpio_request);
+
+/**
+ * devm_gpio_free - free an interrupt
+ * @dev: device to free gpio for
+ * @gpio: gpio to free
+ *
+ * Except for the extra @dev argument, this function takes the
+ * same arguments and performs the same function as gpio_free().
+ * This function instead of gpio_free() should be used to manually
+ * free GPIOs allocated with devm_gpio_request().
+ */
+void devm_gpio_free(struct device *dev, unsigned int gpio)
+{
+
+ WARN_ON(devres_destroy(dev, devm_gpio_release, devm_gpio_match,
+ &gpio));
+ gpio_free(gpio);
+}
+EXPORT_SYMBOL(devm_gpio_free);
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 8c86210..8601a02 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -175,6 +175,10 @@ extern int gpio_request_one(unsigned gpio, unsigned long flags, const char *labe
extern int gpio_request_array(const struct gpio *array, size_t num);
extern void gpio_free_array(const struct gpio *array, size_t num);
+/* bindings for managed devices that want to request gpios */
+int devm_gpio_request(struct device *dev, unsigned gpio, const char *label);
+void devm_gpio_free(struct device *dev, unsigned int gpio);
+
#ifdef CONFIG_GPIO_SYSFS
/*
--
1.7.7.1

25
target/linux/lantiq/patches-3.2/0002-MIPS-remove-unused-prototype-kgdb_config.patch Normal file
View File

@ -0,0 +1,25 @@
From b859096bdc4b029357217af98874d6feec3ff4bd Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 16 Mar 2012 16:27:35 +0100
Subject: [PATCH 02/70] MIPS: remove unused prototype kgdb_config
---
arch/mips/include/asm/mips-boards/generic.h | 4 ----
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 46c0856..6e23ceb 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -93,8 +93,4 @@ extern void mips_pcibios_init(void);
#define mips_pcibios_init() do { } while (0)
#endif
-#ifdef CONFIG_KGDB
-extern void kgdb_config(void);
-#endif
-
#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
--
1.7.7.1

39
target/linux/lantiq/patches-3.2/0003-MTD-MIPS-lantiq-reintroduce-support-for-cmdline-part.patch Normal file
View File

@ -0,0 +1,39 @@
From 63e9d017ce90dc1cd0822bace72e4e391feafdab Mon Sep 17 00:00:00 2001
From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Date: Fri, 17 Feb 2012 22:32:18 +0100
Subject: [PATCH 03/70] MTD: MIPS: lantiq: reintroduce support for cmdline
partitions
Since commit ca97dec2ab5c87e9fbdf7e882e1820004a3966fa the
command line parsing of MTD partitions does not work anymore.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mtd/maps/lantiq-flash.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 4f10e27..764d468 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -45,6 +45,7 @@ struct ltq_mtd {
};
static char ltq_map_name[] = "ltq_nor";
+static const char *ltq_probe_types[] __devinitconst = { "cmdlinepart", NULL };
static map_word
ltq_read16(struct map_info *map, unsigned long adr)
@@ -168,7 +169,7 @@ ltq_mtd_probe(struct platform_device *pdev)
cfi->addr_unlock1 ^= 1;
cfi->addr_unlock2 ^= 1;
- err = mtd_device_parse_register(ltq_mtd->mtd, NULL, 0,
+ err = mtd_device_parse_register(ltq_mtd->mtd, ltq_probe_types, 0,
ltq_mtd_data->parts, ltq_mtd_data->nr_parts);
if (err) {
dev_err(&pdev->dev, "failed to add partitions\n");
--
1.7.7.1

24
target/linux/lantiq/patches-3.2/0004-MTD-add-m25p80-id-for-mx25l2005a.patch Normal file
View File

@ -0,0 +1,24 @@
From e4e27fbcaf2caa2a3e3ef45c736b4bb14f91ecfe Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 13 Mar 2012 18:03:33 +0100
Subject: [PATCH 04/70] MTD: add m25p80 id for mx25l2005a
---
drivers/mtd/devices/m25p80.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 884904d..3f37f5f 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -676,6 +676,7 @@ static const struct spi_device_id m25p_ids[] = {
{ "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
/* Macronix */
+ { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 8, SECT_4K) },
{ "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
{ "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
--
1.7.7.1

114
target/linux/lantiq/patches/0004-MIPS-lantiq-reorganize-xway-code.patch → target/linux/lantiq/patches-3.2/0005-MIPS-lantiq-reorganize-xway-code.patch
View File

@ -1,7 +1,7 @@
From d90739a8962b541969b4c5f7ef1df8fec9c7f153 Mon Sep 17 00:00:00 2001
From cf7086d4c2f7caeccd019c0a57bf1566c72c13ee Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 10 Aug 2011 14:57:04 +0200
Subject: [PATCH 04/24] MIPS: lantiq: reorganize xway code
Subject: [PATCH 05/70] MIPS: lantiq: reorganize xway code
Inside the folder arch/mips/lantiq/xway, there were alot of small files with
lots of duplicated code. This patch adds a wrapper function for inserting and
@ -11,35 +11,35 @@ This patch makes the xway code consistent with the falcon support added later
in this series.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Cc: linux-mips@linux-mips.org
---
arch/mips/include/asm/mach-lantiq/lantiq.h | 14 +---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 14 ++++
arch/mips/lantiq/clk.c | 25 +------
arch/mips/lantiq/devices.c | 30 ++------
arch/mips/lantiq/devices.h | 4 +
arch/mips/lantiq/prom.c | 50 +++++++++++--
arch/mips/lantiq/prom.c | 51 +++++++++++--
arch/mips/lantiq/prom.h | 4 +
arch/mips/lantiq/xway/Makefile | 6 +-
arch/mips/lantiq/xway/devices.c | 42 ++---------
arch/mips/lantiq/xway/dma.c | 21 ++----
arch/mips/lantiq/xway/ebu.c | 53 --------------
arch/mips/lantiq/xway/pmu.c | 70 ------------------
arch/mips/lantiq/xway/prom-ase.c | 9 +++
arch/mips/lantiq/xway/dma.c | 21 +----
arch/mips/lantiq/xway/ebu.c | 52 -------------
arch/mips/lantiq/xway/pmu.c | 69 -----------------
arch/mips/lantiq/xway/prom-ase.c | 9 ++
arch/mips/lantiq/xway/prom-xway.c | 10 +++
arch/mips/lantiq/xway/reset.c | 21 ++----
arch/mips/lantiq/xway/reset.c | 21 +----
arch/mips/lantiq/xway/setup-ase.c | 19 -----
arch/mips/lantiq/xway/setup-xway.c | 20 -----
arch/mips/lantiq/xway/sysctrl.c | 77 ++++++++++++++++++++
arch/mips/lantiq/xway/sysctrl.c | 78 ++++++++++++++++++++
drivers/watchdog/lantiq_wdt.c | 2 +-
19 files changed, 197 insertions(+), 294 deletions(-)
19 files changed, 199 insertions(+), 292 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/ebu.c
delete mode 100644 arch/mips/lantiq/xway/pmu.c
delete mode 100644 arch/mips/lantiq/xway/setup-ase.c
delete mode 100644 arch/mips/lantiq/xway/setup-xway.c
create mode 100644 arch/mips/lantiq/xway/sysctrl.c
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index ce2f029..66d7300 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -9,6 +9,7 @@
@ -66,7 +66,7 @@ Cc: linux-mips@linux-mips.org
extern unsigned int ltq_get_cpu_ver(void);
extern unsigned int ltq_get_soc_type(void);
@@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_da
@@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_data *data);
/* find out what caused the last cpu reset */
extern int ltq_reset_cause(void);
@ -77,9 +77,11 @@ Cc: linux-mips@linux-mips.org
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 8a3c6be..9b7ee366 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -65,6 +65,8 @@
@@ -61,6 +61,8 @@
#define LTQ_CGU_BASE_ADDR 0x1F103000
#define LTQ_CGU_SIZE 0x1000
@ -88,7 +90,7 @@ Cc: linux-mips@linux-mips.org
/* ICU - interrupt control unit */
#define LTQ_ICU_BASE_ADDR 0x1F880200
#define LTQ_ICU_SIZE 0x100
@@ -101,6 +103,8 @@
@@ -97,6 +99,8 @@
#define LTQ_WDT_BASE_ADDR 0x1F8803F0
#define LTQ_WDT_SIZE 0x10
@ -97,7 +99,7 @@ Cc: linux-mips@linux-mips.org
/* STP - serial to parallel conversion unit */
#define LTQ_STP_BASE_ADDR 0x1E100BB0
#define LTQ_STP_SIZE 0x40
@@ -125,11 +129,21 @@
@@ -121,11 +125,21 @@
#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
@ -119,6 +121,8 @@ Cc: linux-mips@linux-mips.org
static inline int ltq_is_ar9(void)
{
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 77ed70f..39eef7f 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -22,6 +22,7 @@
@ -152,12 +156,12 @@ Cc: linux-mips@linux-mips.org
- if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
- panic("Failed to insert cgu memory\n");
+ ltq_soc_init();
-
- if (request_mem_region(ltq_cgu_resource.start,
- resource_size(&ltq_cgu_resource), "cgu") < 0)
- panic("Failed to request cgu memory\n");
-
+ ltq_soc_init();
- ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
- resource_size(&ltq_cgu_resource));
- if (!ltq_cgu_membase) {
@ -170,6 +174,8 @@ Cc: linux-mips@linux-mips.org
+ pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
clk_put(clk);
}
diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c
index de1cb2b..7193d78 100644
--- a/arch/mips/lantiq/devices.c
+++ b/arch/mips/lantiq/devices.c
@@ -27,12 +27,8 @@
@ -187,7 +193,7 @@ Cc: linux-mips@linux-mips.org
static struct platform_device ltq_nor = {
.name = "ltq_nor",
@@ -47,12 +43,8 @@ void __init ltq_register_nor(struct phys
@@ -47,12 +43,8 @@ void __init ltq_register_nor(struct physmap_flash_data *data)
}
/* watchdog */
@ -229,6 +235,8 @@ Cc: linux-mips@linux-mips.org
IRQ_RES(tx, LTQ_ASC_TIR(1)),
IRQ_RES(rx, LTQ_ASC_RIR(1)),
IRQ_RES(err, LTQ_ASC_EIR(1)),
diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h
index 2947bb1..a03c23f 100644
--- a/arch/mips/lantiq/devices.h
+++ b/arch/mips/lantiq/devices.h
@@ -14,6 +14,10 @@
@ -242,6 +250,8 @@ Cc: linux-mips@linux-mips.org
extern void ltq_register_nor(struct physmap_flash_data *data);
extern void ltq_register_wdt(void);
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index e34fcfd..e3b1e25 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -16,6 +16,10 @@
@ -255,7 +265,7 @@ Cc: linux-mips@linux-mips.org
static struct ltq_soc_info soc_info;
unsigned int ltq_get_cpu_ver(void)
@@ -57,16 +61,50 @@ static void __init prom_init_cmdline(voi
@@ -55,16 +59,51 @@ static void __init prom_init_cmdline(void)
}
}
@ -265,23 +275,23 @@ Cc: linux-mips@linux-mips.org
- struct clk *clk;
+ __iomem void *ret = NULL;
+ struct resource *lookup = lookup_resource(&iomem_resource, res->start);
+
+ if (lookup && strcmp(lookup->name, res->name)) {
+ panic("conflicting memory range %s\n", res->name);
+ pr_err("conflicting memory range %s\n", res->name);
+ return NULL;
+ }
+ if (!lookup) {
+ if (insert_resource(&iomem_resource, res) < 0) {
+ panic("Failed to insert %s memory\n", res->name);
+ pr_err("Failed to insert %s memory\n", res->name);
+ return NULL;
+ }
+ }
+ if (request_mem_region(res->start,
+ resource_size(res), res->name) < 0) {
+ panic("Failed to request %s memory\n", res->name);
+ pr_err("Failed to request %s memory\n", res->name);
+ goto err_res;
+ }
+
+ ret = ioremap_nocache(res->start, resource_size(res));
+ if (!ret)
+ goto err_mem;
@ -298,6 +308,7 @@ Cc: linux-mips@linux-mips.org
+ release_resource(res);
+ return NULL;
+}
+EXPORT_SYMBOL(ltq_remap_resource);
+
+void __init prom_init(void)
+{
@ -312,6 +323,8 @@ Cc: linux-mips@linux-mips.org
soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
pr_info("SoC: %s\n", soc_info.sys_type);
prom_init_cmdline();
diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
index b4229d9..51dba1b 100644
--- a/arch/mips/lantiq/prom.h
+++ b/arch/mips/lantiq/prom.h
@@ -9,17 +9,21 @@
@ -336,6 +349,8 @@ Cc: linux-mips@linux-mips.org
extern void ltq_soc_setup(void);
#endif
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index c517f2e..6678402 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1,7 @@
@ -349,6 +364,8 @@ Cc: linux-mips@linux-mips.org
obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
index d614aa7..f97e565 100644
--- a/arch/mips/lantiq/xway/devices.c
+++ b/arch/mips/lantiq/xway/devices.c
@@ -31,22 +31,9 @@
@ -421,9 +438,11 @@ Cc: linux-mips@linux-mips.org
static struct platform_device ltq_etop = {
.name = "ltq_etop",
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index cbb6ae5..60cd11f 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -23,6 +23,8 @@
@@ -24,6 +24,8 @@
#include <lantiq_soc.h>
#include <xway_dma.h>
@ -432,7 +451,7 @@ Cc: linux-mips@linux-mips.org
#define LTQ_DMA_CTRL 0x10
#define LTQ_DMA_CPOLL 0x14
#define LTQ_DMA_CS 0x18
@@ -54,12 +56,8 @@
@@ -55,12 +57,8 @@
#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
ltq_dma_membase + (z))
@ -447,7 +466,7 @@ Cc: linux-mips@linux-mips.org
static void __iomem *ltq_dma_membase;
@@ -219,17 +217,8 @@ ltq_dma_init(void)
@@ -220,17 +218,8 @@ ltq_dma_init(void)
{
int i;
@ -466,6 +485,9 @@ Cc: linux-mips@linux-mips.org
if (!ltq_dma_membase)
panic("Failed to remap dma memory\n");
diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
deleted file mode 100644
index 033b318..0000000
--- a/arch/mips/lantiq/xway/ebu.c
+++ /dev/null
@@ -1,52 +0,0 @@
@ -521,6 +543,9 @@ Cc: linux-mips@linux-mips.org
-}
-
-postcore_initcall(lantiq_ebu_init);
diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
deleted file mode 100644
index 39f0d26..0000000
--- a/arch/mips/lantiq/xway/pmu.c
+++ /dev/null
@@ -1,69 +0,0 @@
@ -593,6 +618,8 @@ Cc: linux-mips@linux-mips.org
-}
-
-core_initcall(ltq_pmu_init);
diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
index ae4959a..3f86a3b 100644
--- a/arch/mips/lantiq/xway/prom-ase.c
+++ b/arch/mips/lantiq/xway/prom-ase.c
@@ -13,6 +13,7 @@
@ -603,7 +630,7 @@ Cc: linux-mips@linux-mips.org
#include "../prom.h"
#define SOC_AMAZON_SE "Amazon_SE"
@@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_so
@@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
{
i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
@ -611,7 +638,7 @@ Cc: linux-mips@linux-mips.org
switch (i->partnum) {
case SOC_ID_AMAZON_SE:
i->name = SOC_AMAZON_SE;
@@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_so
@@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
break;
}
}
@ -622,6 +649,8 @@ Cc: linux-mips@linux-mips.org
+ ltq_register_gpio();
+ ltq_register_wdt();
+}
diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
index 2228133..d823a92 100644
--- a/arch/mips/lantiq/xway/prom-xway.c
+++ b/arch/mips/lantiq/xway/prom-xway.c
@@ -13,6 +13,7 @@
@ -632,7 +661,7 @@ Cc: linux-mips@linux-mips.org
#include "../prom.h"
#define SOC_DANUBE "Danube"
@@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_so
@@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
{
i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
@ -640,7 +669,7 @@ Cc: linux-mips@linux-mips.org
switch (i->partnum) {
case SOC_ID_DANUBE1:
case SOC_ID_DANUBE2:
@@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_so
@@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
break;
}
}
@ -652,6 +681,8 @@ Cc: linux-mips@linux-mips.org
+ ltq_register_gpio();
+ ltq_register_wdt();
+}
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 3d41f0b..ca2212a 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -15,6 +15,8 @@
@ -697,6 +728,9 @@ Cc: linux-mips@linux-mips.org
if (!ltq_rcu_membase)
panic("Failed to remap rcu memory\n");
diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
deleted file mode 100644
index f6f3267..0000000
--- a/arch/mips/lantiq/xway/setup-ase.c
+++ /dev/null
@@ -1,19 +0,0 @@
@ -719,6 +753,9 @@ Cc: linux-mips@linux-mips.org
- ltq_register_gpio();
- ltq_register_wdt();
-}
diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
deleted file mode 100644
index c292f64..0000000
--- a/arch/mips/lantiq/xway/setup-xway.c
+++ /dev/null
@@ -1,20 +0,0 @@
@ -742,9 +779,12 @@ Cc: linux-mips@linux-mips.org
- ltq_register_gpio();
- ltq_register_wdt();
-}
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
new file mode 100644
index 0000000..8fd13a1
--- /dev/null
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -0,0 +1,77 @@
@@ -0,0 +1,78 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -754,6 +794,7 @@ Cc: linux-mips@linux-mips.org
+ */
+
+#include <linux/ioport.h>
+#include <linux/export.h>
+
+#include <lantiq_soc.h>
+
@ -822,6 +863,8 @@ Cc: linux-mips@linux-mips.org
+ /* make sure to unprotect the memory region where flash is located */
+ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
+}
diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index 102aed0..179bf98 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -16,7 +16,7 @@
@ -833,3 +876,6 @@ Cc: linux-mips@linux-mips.org
/* Section 3.4 of the datasheet
* The password sequence protects the WDT control register from unintended
--
1.7.7.1

149
target/linux/lantiq/patches-3.2/0006-MIPS-lantiq-change-ltq_request_gpio-call-signature.patch Normal file
View File

@ -0,0 +1,149 @@
From 35f0a707698fc8f20e4164a704d7ac6af3342fb8 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 11 Nov 2011 12:45:24 +0100
Subject: [PATCH 06/70] MIPS: lantiq: change ltq_request_gpio() call signature
ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins.
This was XWAY specific. In order to also accomodate SoCs that require more bits
we use a 32bit mask instead. This way the call signature is consistent between
XWAY and FALC-ON.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +-
arch/mips/lantiq/xway/gpio.c | 8 ++--
arch/mips/lantiq/xway/gpio_stp.c | 6 ++--
arch/mips/pci/pci-lantiq.c | 36 +++++++++----------
4 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 9b7ee366..87f6d24 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -135,8 +135,8 @@ extern __iomem void *ltq_ebu_membase;
extern __iomem void *ltq_cgu_membase;
/* request a non-gpio and set the PIO config */
-extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
- unsigned int alt1, unsigned int dir, const char *name);
+extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name);
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
extern void ltq_cgu_enable(unsigned int clk);
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index d2fa98f..f204f6c 100644
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio)
}
EXPORT_SYMBOL(irq_to_gpio);
-int ltq_gpio_request(unsigned int pin, unsigned int alt0,
- unsigned int alt1, unsigned int dir, const char *name)
+int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name)
{
int id = 0;
@@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
pin -= PINS_PER_PORT;
id++;
}
- if (alt0)
+ if (mux & 0x2)
ltq_gpio_setbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL0, pin);
else
ltq_gpio_clearbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL0, pin);
- if (alt1)
+ if (mux & 0x1)
ltq_gpio_setbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL1, pin);
else
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index ff9991c..2c78660 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = {
static int ltq_stp_hw_init(void)
{
/* the 3 pins used to control the external stp */
- ltq_gpio_request(4, 1, 0, 1, "stp-st");
- ltq_gpio_request(5, 1, 0, 1, "stp-d");
- ltq_gpio_request(6, 1, 0, 1, "stp-sh");
+ ltq_gpio_request(4, 2, 1, "stp-st");
+ ltq_gpio_request(5, 2, 1, "stp-d");
+ ltq_gpio_request(6, 2, 1, "stp-sh");
/* sane defaults */
ltq_stp_w32(0, LTQ_STP_AR);
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index be1e1af..c001c5a 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -70,28 +70,27 @@
struct ltq_pci_gpio_map {
int pin;
- int alt0;
- int alt1;
+ int mux;
int dir;
char *name;
};
/* the pci core can make use of the following gpios */
static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
- { 0, 1, 0, 0, "pci-exin0" },
- { 1, 1, 0, 0, "pci-exin1" },
- { 2, 1, 0, 0, "pci-exin2" },
- { 39, 1, 0, 0, "pci-exin3" },
- { 10, 1, 0, 0, "pci-exin4" },
- { 9, 1, 0, 0, "pci-exin5" },
- { 30, 1, 0, 1, "pci-gnt1" },
- { 23, 1, 0, 1, "pci-gnt2" },
- { 19, 1, 0, 1, "pci-gnt3" },
- { 38, 1, 0, 1, "pci-gnt4" },
- { 29, 1, 0, 0, "pci-req1" },
- { 31, 1, 0, 0, "pci-req2" },
- { 3, 1, 0, 0, "pci-req3" },
- { 37, 1, 0, 0, "pci-req4" },
+ { 0, 2, 0, "pci-exin0" },
+ { 1, 2, 0, "pci-exin1" },
+ { 2, 2, 0, "pci-exin2" },
+ { 39, 2, 0, "pci-exin3" },
+ { 10, 2, 0, "pci-exin4" },
+ { 9, 2, 0, "pci-exin5" },
+ { 30, 2, 1, "pci-gnt1" },
+ { 23, 2, 1, "pci-gnt2" },
+ { 19, 2, 1, "pci-gnt3" },
+ { 38, 2, 1, "pci-gnt4" },
+ { 29, 2, 0, "pci-req1" },
+ { 31, 2, 0, "pci-req2" },
+ { 3, 2, 0, "pci-req3" },
+ { 37, 2, 0, "pci-req4" },
};
__iomem void *ltq_pci_mapped_cfg;
@@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio)
for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
if (gpio & (1 << i)) {
ltq_gpio_request(ltq_pci_gpio_map[i].pin,
- ltq_pci_gpio_map[i].alt0,
- ltq_pci_gpio_map[i].alt1,
+ ltq_pci_gpio_map[i].mux,
ltq_pci_gpio_map[i].dir,
ltq_pci_gpio_map[i].name);
}
}
- ltq_gpio_request(21, 0, 0, 1, "pci-reset");
+ ltq_gpio_request(21, 0, 1, "pci-reset");
ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
}
--
1.7.7.1

23
target/linux/lantiq/patches/0005-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch → target/linux/lantiq/patches-3.2/0007-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch
View File

@ -1,7 +1,7 @@
From d9355bb07878f9aa40856cc437c43cedc87662fc Mon Sep 17 00:00:00 2001
From 03f55cae0f5d9a4c30f935abf8d621ced64ae425 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 11 Aug 2011 12:25:55 +0200
Subject: [PATCH 05/24] MIPS: lantiq: make irq.c support the FALC-ON
Subject: [PATCH 07/70] MIPS: lantiq: make irq.c support the FALC-ON
There are minor differences in how irqs work on xway and falcon socs.
Xway needs 2 quirks that we need to disable for falcon to also work with
@ -10,16 +10,17 @@ this code.
* EBU irq does not need to send a special ack to the EBU
* The EIU does not exist
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/irq.c | 24 +++++++++++++-----------
1 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index f9737bb..17c057f 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int modul
@@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int module)
do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
/* if this is a EBU irq, we need to ack it or get a deadlock */
@ -37,15 +38,14 @@ Cc: linux-mips@linux-mips.org
+ if (LTQ_EIU_BASE_ADDR) {
+ if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
+ panic("Failed to insert eiu memory\n");
+
+ if (request_mem_region(ltq_eiu_resource.start,
+ resource_size(&ltq_eiu_resource), "eiu") < 0)
+ panic("Failed to request eiu memory\n");
- if (request_mem_region(ltq_eiu_resource.start,
- resource_size(&ltq_eiu_resource), "eiu") < 0)
- panic("Failed to request eiu memory\n");
-
+ if (request_mem_region(ltq_eiu_resource.start,
+ resource_size(&ltq_eiu_resource), "eiu") < 0)
+ panic("Failed to request eiu memory\n");
- ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
+ ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
resource_size(&ltq_eiu_resource));
@ -68,3 +68,6 @@ Cc: linux-mips@linux-mips.org
irq_set_chip_and_handler(i, &ltq_eiu_type,
handle_level_irq);
/* EIU3-5 only exist on ar9 and vr9 */
--
1.7.7.1

123
target/linux/lantiq/patches/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch → target/linux/lantiq/patches-3.2/0008-MIPS-lantiq-add-basic-support-for-FALC-ON.patch
View File

@ -1,18 +1,16 @@
From ff57bc17a9964d24708759c6d78a51e337563d5f Mon Sep 17 00:00:00 2001
From d54a53bc8bc25bf2f9076013f89b30cb9103f99f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 11 Aug 2011 14:33:04 +0200
Subject: [PATCH 06/24] MIPS: lantiq: add basic support for FALC-ON
Subject: [PATCH 08/70] MIPS: lantiq: add basic support for FALC-ON
Adds support for the FALC-ON SoC. This SoC is from the fiber to the home GPON
series.
Adds support for the FALC-ON SoC. This SoC is from the FTTH/GPON SoC family.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++
arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++
.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 140 ++++++++++
.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 143 +++++++++++
arch/mips/include/asm/mach-lantiq/lantiq.h | 1 +
arch/mips/lantiq/Kconfig | 4 +
arch/mips/lantiq/Makefile | 1 +
@ -21,10 +19,10 @@ Cc: linux-mips@linux-mips.org
arch/mips/lantiq/falcon/clk.c | 44 ++++
arch/mips/lantiq/falcon/devices.c | 87 +++++++
arch/mips/lantiq/falcon/devices.h | 18 ++
arch/mips/lantiq/falcon/prom.c | 72 ++++++
arch/mips/lantiq/falcon/prom.c | 93 +++++++
arch/mips/lantiq/falcon/reset.c | 87 +++++++
arch/mips/lantiq/falcon/sysctrl.c | 181 +++++++++++++
14 files changed, 923 insertions(+), 0 deletions(-)
arch/mips/lantiq/falcon/sysctrl.c | 183 +++++++++++++
14 files changed, 949 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@ -36,6 +34,9 @@ Cc: linux-mips@linux-mips.org
create mode 100644 arch/mips/lantiq/falcon/reset.c
create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
new file mode 100644
index 0000000..4dc6466
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
@@ -0,0 +1,268 @@
@ -307,6 +308,9 @@ Cc: linux-mips@linux-mips.org
+#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31)
+
+#endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
new file mode 100644
index 0000000..2caccd9
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
@@ -0,0 +1,18 @@
@ -328,9 +332,12 @@ Cc: linux-mips@linux-mips.org
+#include_next <irq.h>
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
new file mode 100644
index 0000000..b074748
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -0,0 +1,140 @@
@@ -0,0 +1,143 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -361,8 +368,10 @@ Cc: linux-mips@linux-mips.org
+#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
+#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
+
+/* during early_printk no ioremap possible at this early stage
+ lets use KSEG1 instead */
+/*
+ * during early_printk no ioremap possible at this early stage
+ * lets use KSEG1 instead
+ */
+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
+
+/* ICU - interrupt control unit */
@ -407,6 +416,7 @@ Cc: linux-mips@linux-mips.org
+#define LTQ_STATUS_BASE_ADDR 0x1E802000
+
+#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
+#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
+#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
+
+/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
@ -457,7 +467,7 @@ Cc: linux-mips@linux-mips.org
+ ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
+
+/* gpio_request wrapper to help configure the pin */
+extern int ltq_gpio_request(unsigned int pin, unsigned int val,
+extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name);
+extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
+
@ -471,9 +481,11 @@ Cc: linux-mips@linux-mips.org
+
+#endif /* CONFIG_SOC_FALCON */
+#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 66d7300..188de0f 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(voi
@@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(void);
/* clock speeds */
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
@ -481,6 +493,8 @@ Cc: linux-mips@linux-mips.org
#define CLOCK_111M 111111111
#define CLOCK_133M 133333333
#define CLOCK_167M 166666667
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 3fccf21..cb6b39f 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -16,8 +16,12 @@ config SOC_XWAY
@ -496,13 +510,17 @@ Cc: linux-mips@linux-mips.org
+source "arch/mips/lantiq/falcon/Kconfig"
endif
diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
index e5dae0e..7e9c69e 100644
--- a/arch/mips/lantiq/Makefile
+++ b/arch/mips/lantiq/Makefile
@@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devi
@@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devices.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
+obj-$(CONFIG_SOC_FALCON) += falcon/
diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
index f3dff05..b3ec498 100644
--- a/arch/mips/lantiq/Platform
+++ b/arch/mips/lantiq/Platform
@@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/
@ -510,10 +528,16 @@ Cc: linux-mips@linux-mips.org
load-$(CONFIG_LANTIQ) = 0xffffffff80002000
cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
+cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
new file mode 100644
index 0000000..e9c7455
--- /dev/null
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -0,0 +1 @@
+obj-y := clk.o prom.o reset.o sysctrl.o devices.o
diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
new file mode 100644
index 0000000..afe1b52
--- /dev/null
+++ b/arch/mips/lantiq/falcon/clk.c
@@ -0,0 +1,44 @@
@ -527,7 +551,7 @@ Cc: linux-mips@linux-mips.org
+ */
+
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/export.h>
+
+#include <lantiq_soc.h>
+
@ -561,6 +585,9 @@ Cc: linux-mips@linux-mips.org
+ return CLOCK_100M;
+}
+EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
new file mode 100644
index 0000000..c4606f2
--- /dev/null
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -0,0 +1,87 @@
@ -651,6 +678,9 @@ Cc: linux-mips@linux-mips.org
+{
+ platform_device_register(&ltq_flash_nand);
+}
diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
new file mode 100644
index 0000000..e802a7c
--- /dev/null
+++ b/arch/mips/lantiq/falcon/devices.h
@@ -0,0 +1,18 @@
@ -672,9 +702,12 @@ Cc: linux-mips@linux-mips.org
+extern void falcon_register_nand(void);
+
+#endif
diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
new file mode 100644
index 0000000..b50d6f9
--- /dev/null
+++ b/arch/mips/lantiq/falcon/prom.c
@@ -0,0 +1,72 @@
@@ -0,0 +1,93 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -691,6 +724,9 @@ Cc: linux-mips@linux-mips.org
+#include "../prom.h"
+
+#define SOC_FALCON "Falcon"
+#define SOC_FALCON_D "Falcon-D"
+#define SOC_FALCON_V "Falcon-V"
+#define SOC_FALCON_M "Falcon-M"
+
+#define PART_SHIFT 12
+#define PART_MASK 0x0FFFF000
@ -698,6 +734,8 @@ Cc: linux-mips@linux-mips.org
+#define REV_MASK 0xF0000000
+#define SREV_SHIFT 22
+#define SREV_MASK 0x03C00000
+#define TYPE_SHIFT 26
+#define TYPE_MASK 0x3C000000
+
+#define MUXC_SIF_RX_PIN 112
+#define MUXC_SIF_TX_PIN 113
@ -731,14 +769,30 @@ Cc: linux-mips@linux-mips.org
+void __init
+ltq_soc_detect(struct ltq_soc_info *i)
+{
+ u32 type;
+ i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
+ i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
+ i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT;
+ i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
+ sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
+ i->rev & 0x7, i->srev & 0x3);
+ i->rev & 0x7, (i->srev & 0x3) + 1);
+
+ switch (i->partnum) {
+ case SOC_ID_FALCON:
+ type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
+ switch (type) {
+ case 0:
+ i->name = SOC_FALCON_D;
+ break;
+ case 1:
+ i->name = SOC_FALCON_V;
+ break;
+ case 2:
+ i->name = SOC_FALCON_M;
+ break;
+ default:
+ i->name = SOC_FALCON;
+ break;
+ }
+ i->type = SOC_TYPE_FALCON;
+ break;
+
@ -747,6 +801,9 @@ Cc: linux-mips@linux-mips.org
+ break;
+ }
+}
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
new file mode 100644
index 0000000..cbcadc5
--- /dev/null
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -0,0 +1,87 @@
@ -763,7 +820,7 @@ Cc: linux-mips@linux-mips.org
+#include <linux/io.h>
+#include <linux/pm.h>
+#include <asm/reboot.h>
+#include <linux/module.h>
+#include <linux/export.h>
+
+#include <lantiq_soc.h>
+
@ -837,9 +894,12 @@ Cc: linux-mips@linux-mips.org
+}
+
+arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
new file mode 100644
index 0000000..905a142
--- /dev/null
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -0,0 +1,181 @@
@@ -0,0 +1,183 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -850,6 +910,7 @@ Cc: linux-mips@linux-mips.org
+ */
+
+#include <linux/ioport.h>
+#include <linux/export.h>
+#include <asm/delay.h>
+
+#include <lantiq_soc.h>
@ -905,11 +966,12 @@ Cc: linux-mips@linux-mips.org
+#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x))
+
+static inline void
+ltq_sysctl_wait(int module, unsigned int mask, unsigned int test)
+ltq_sysctl_wait(int module, unsigned int mask,
+ unsigned int test, unsigned int reg)
+{
+ int err = 1000000;
+
+ do {} while (--err && ((ltq_reg_r32(module, LTQ_SYSCTL_ACTS)
+ do {} while (--err && ((ltq_reg_r32(module, reg)
+ & mask) != test));
+ if (!err)
+ pr_err("module de/activation failed %d %08X %08X\n",
@ -924,7 +986,7 @@ Cc: linux-mips@linux-mips.org
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
+ ltq_sysctl_wait(module, mask, mask);
+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+}
+EXPORT_SYMBOL(ltq_sysctl_activate);
+
@ -936,7 +998,7 @@ Cc: linux-mips@linux-mips.org
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
+ ltq_sysctl_wait(module, mask, 0);
+ ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS);
+}
+EXPORT_SYMBOL(ltq_sysctl_deactivate);
+
@ -947,7 +1009,7 @@ Cc: linux-mips@linux-mips.org
+ return;
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
+ ltq_sysctl_wait(module, mask, mask);
+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS);
+}
+EXPORT_SYMBOL(ltq_sysctl_clken);
+
@ -958,7 +1020,7 @@ Cc: linux-mips@linux-mips.org
+ return;
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
+ ltq_sysctl_wait(module, mask, 0);
+ ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS);
+}
+EXPORT_SYMBOL(ltq_sysctl_clkdis);
+
@ -974,7 +1036,7 @@ Cc: linux-mips@linux-mips.org
+ if ((~act & mask) != 0)
+ ltq_sysctl_activate(module, ~act & mask);
+ ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
+ ltq_sysctl_wait(module, mask, mask);
+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+}
+EXPORT_SYMBOL(ltq_sysctl_reboot);
+
@ -1021,3 +1083,6 @@ Cc: linux-mips@linux-mips.org
+
+ ltq_gpe_enable();
+}
--
1.7.7.1

28
target/linux/lantiq/patches/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch → target/linux/lantiq/patches-3.2/0009-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch
View File

@ -1,27 +1,30 @@
From 02d9df56be1ba23c7bec51c94e5d2ac0d13d2d78 Mon Sep 17 00:00:00 2001
From 95e7c9e7b37b06462c8b3b8431dc64d60369eb38 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 11 Aug 2011 14:35:02 +0200
Subject: [PATCH 07/24] MIPS: lantiq: add support for FALC-ON GPIOs
Subject: [PATCH 09/70] MIPS: lantiq: add support for FALC-ON GPIOs
FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds
the new driver.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/lantiq/falcon/Makefile | 2 +-
arch/mips/lantiq/falcon/devices.c | 41 ++++
arch/mips/lantiq/falcon/devices.h | 2 +
arch/mips/lantiq/falcon/gpio.c | 398 +++++++++++++++++++++++++++++++++++++
4 files changed, 442 insertions(+), 1 deletions(-)
arch/mips/lantiq/falcon/gpio.c | 399 +++++++++++++++++++++++++++++++++++++
4 files changed, 443 insertions(+), 1 deletions(-)
create mode 100644 arch/mips/lantiq/falcon/gpio.c
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
index e9c7455..de72209 100644
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1 +1 @@
-obj-y := clk.o prom.o reset.o sysctrl.o devices.o
+obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
index c4606f2..4f47b44 100644
--- a/arch/mips/lantiq/falcon/devices.c
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -9,6 +9,7 @@
@ -76,6 +79,8 @@ Cc: linux-mips@linux-mips.org
+ ltq_sysctl_activate(SYSCTL_SYS1,
+ ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
+}
diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
index e802a7c..18be8b6 100644
--- a/arch/mips/lantiq/falcon/devices.h
+++ b/arch/mips/lantiq/falcon/devices.h
@@ -14,5 +14,7 @@
@ -86,9 +91,12 @@ Cc: linux-mips@linux-mips.org
+extern void falcon_register_gpio_extra(void);
#endif
diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
new file mode 100644
index 0000000..28f8639
--- /dev/null
+++ b/arch/mips/lantiq/falcon/gpio.c
@@ -0,0 +1,398 @@
@@ -0,0 +1,399 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -101,6 +109,7 @@ Cc: linux-mips@linux-mips.org
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+
+#include <lantiq_soc.h>
@ -187,7 +196,7 @@ Cc: linux-mips@linux-mips.org
+}
+EXPORT_SYMBOL(ltq_gpio_mux_set);
+
+int ltq_gpio_request(unsigned int pin, unsigned int val,
+int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name)
+{
+ int port = pin / 100;
@ -206,7 +215,7 @@ Cc: linux-mips@linux-mips.org
+ else
+ gpio_direction_input(pin);
+
+ return ltq_gpio_mux_set(pin, val);
+ return ltq_gpio_mux_set(pin, mux);
+}
+EXPORT_SYMBOL(ltq_gpio_request);
+
@ -487,3 +496,6 @@ Cc: linux-mips@linux-mips.org
+}
+
+postcore_initcall(falcon_gpio_init);
--
1.7.7.1

18
target/linux/lantiq/patches/0008-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch → target/linux/lantiq/patches-3.2/0010-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch
View File

@ -1,14 +1,13 @@
From ec6ba0f79c010a878d679c057fb6306b50a201b0 Mon Sep 17 00:00:00 2001
From 9397aa9584bade07ae667ecd5135653f9c04e236 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 11 Aug 2011 14:09:35 +0200
Subject: [PATCH 08/24] MIPS: lantiq: add support for the EASY98000 evaluation
Subject: [PATCH 10/70] MIPS: lantiq: add support for the EASY98000 evaluation
board
This patch adds the machine code for the EASY9800 evaluation board.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/lantiq/falcon/Kconfig | 11 +++
arch/mips/lantiq/falcon/Makefile | 1 +
@ -18,6 +17,9 @@ Cc: linux-mips@linux-mips.org
create mode 100644 arch/mips/lantiq/falcon/Kconfig
create mode 100644 arch/mips/lantiq/falcon/mach-easy98000.c
diff --git a/arch/mips/lantiq/falcon/Kconfig b/arch/mips/lantiq/falcon/Kconfig
new file mode 100644
index 0000000..03e999d
--- /dev/null
+++ b/arch/mips/lantiq/falcon/Kconfig
@@ -0,0 +1,11 @@
@ -32,11 +34,16 @@ Cc: linux-mips@linux-mips.org
+endmenu
+
+endif
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
index de72209..56b22eb 100644
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1 +1,2 @@
obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c
new file mode 100644
index 0000000..361b8f0
--- /dev/null
+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
@@ -0,0 +1,110 @@
@ -150,6 +157,8 @@ Cc: linux-mips@linux-mips.org
+ "EASY98000NAND",
+ "EASY98000 Eval Board (NAND Flash)",
+ easy98000nand_init);
diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h
index 7e01b8c..dfc6af7 100644
--- a/arch/mips/lantiq/machtypes.h
+++ b/arch/mips/lantiq/machtypes.h
@@ -15,6 +15,11 @@ enum lantiq_mach_type {
@ -164,3 +173,6 @@ Cc: linux-mips@linux-mips.org
};
#endif
--
1.7.7.1

30
target/linux/lantiq/patches/0001-MIPS-lantiq-fix-early-printk.patch → target/linux/lantiq/patches-3.2/0011-MIPS-lantiq-fix-early-printk.patch
View File

@ -1,33 +1,38 @@
From 91f8d0c8fbb9ea70bf78a291e312157177be8ee3 Mon Sep 17 00:00:00 2001
From 68e9e86dda22c491e5e3c44271a91aefcf636434 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 20 Aug 2011 18:55:13 +0200
Subject: [PATCH 01/24] MIPS: lantiq: fix early printk
Subject: [PATCH 11/70] MIPS: lantiq: fix early printk
The code was using a 32bit write operation in the early_printk code. This
resulted in 3 zero bytes also being written to the serial port. Change the
memory access to 8bit.
The code was using a 32bit write operations in the early_printk code. This
resulted in 3 zero bytes also being written to the serial port. This patch
changes the memory access to 8bit.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 ++++
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 ++++++
arch/mips/lantiq/early_printk.c | 14 ++++++++------
2 files changed, 12 insertions(+), 6 deletions(-)
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 87f6d24..e31f52d 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -34,6 +34,10 @@
@@ -34,6 +34,12 @@
#define LTQ_ASC1_BASE_ADDR 0x1E100C00
#define LTQ_ASC_SIZE 0x400
+/* during early_printk no ioremap is possible
+ lets use KSEG1 instead */
+/*
+ * during early_printk no ioremap is possible
+ * lets use KSEG1 instead
+ */
+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
+
/* RCU - reset control unit */
#define LTQ_RCU_BASE_ADDR 0x1F203000
#define LTQ_RCU_SIZE 0x1000
diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
index 972e05f..5089075 100644
--- a/arch/mips/lantiq/early_printk.c
+++ b/arch/mips/lantiq/early_printk.c
@@ -12,11 +12,13 @@
@ -58,3 +63,6 @@ Cc: linux-mips@linux-mips.org
+ ltq_w8(c, LTQ_ASC_TBUF);
local_irq_restore(flags);
}
--
1.7.7.1

12
target/linux/lantiq/patches/0002-MIPS-lantiq-fix-cmdline-parsing.patch → target/linux/lantiq/patches-3.2/0012-MIPS-lantiq-fix-cmdline-parsing.patch
View File

@ -1,21 +1,22 @@
From b85d5204f2fe8c3b5e6172f7cc1741ad6e849334 Mon Sep 17 00:00:00 2001
From 3be934b64f874e6cd2af7945f4fc441c7fadb34f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 12 Aug 2011 16:27:38 +0200
Subject: [PATCH 02/24] MIPS: lantiq: fix cmdline parsing
Subject: [PATCH 12/70] MIPS: lantiq: fix cmdline parsing
The code tested if the KSEG1 mapped address of argv was != 0. We need to use
CPHYSADDR instead to make the conditional actually work.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/lantiq/prom.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index e3b1e25..acb8921 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -45,10 +45,12 @@ static void __init prom_init_cmdline(voi
@@ -49,10 +49,12 @@ static void __init prom_init_cmdline(void)
char **argv = (char **) KSEG1ADDR(fw_arg1);
int i;
@ -30,3 +31,6 @@ Cc: linux-mips@linux-mips.org
strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
}
--
1.7.7.1

10
target/linux/lantiq/patches/0024-MIPS-lantiq-fixes-STP-based-gpios.patch → target/linux/lantiq/patches-3.2/0013-MIPS-lantiq-fix-STP-gpio-groups.patch
View File

@ -1,9 +1,10 @@
From 2dfa2b3e50c5ac49052233d15fa427a9b9136df8 Mon Sep 17 00:00:00 2001
From 556ba7f7149a0350a47ecf26185aed99c8d87176 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 27 Oct 2011 20:06:05 +0200
Subject: [PATCH 10/22] MIPS: lantiq: fixes STP based gpios
Subject: [PATCH 13/70] MIPS: lantiq: fix STP gpio groups
The STP engine has 3 groups of 8 pins. Only the first was activated by default.
This patch activates the 2 missing groups.
Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
@ -11,6 +12,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
arch/mips/lantiq/xway/gpio_stp.c | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index 2c78660..cb6f170 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -35,6 +35,8 @@
@ -34,3 +37,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
/* stp are update periodically by the FPI bus */
ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
--
1.7.7.1

17
target/linux/lantiq/patches/0025-MIPS-lantiq-activate-pull-up-resistors-when-gpio-is-.patch → target/linux/lantiq/patches-3.2/0014-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch
View File

@ -1,10 +1,10 @@
From 6efd9a5f303c4561eee14ae429b8c0fafa6c5a83 Mon Sep 17 00:00:00 2001
From e97f45d255f4a223d38e2f39c1ddf7a3e0766527 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 27 Oct 2011 20:06:30 +0200
Subject: [PATCH 11/22] MIPS: lantiq: activate pull up resistors when gpio is
a input
Subject: [PATCH 14/70] MIPS: lantiq: fix pull gpio up resistors usage
The register that enables a gpios internal pullups was not set.
The register that enables a gpios internal pullups was not used. This patch
makes sure the pullups are activated correctly.
Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
@ -12,6 +12,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
arch/mips/lantiq/xway/gpio.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index f204f6c..14ff7c7 100644
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -21,6 +21,8 @@
@ -23,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#define PINS_PER_PORT 16
#define MAX_PORTS 3
@@ -106,6 +108,8 @@ static int ltq_gpio_direction_input(stru
@@ -106,6 +108,8 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
@ -32,7 +34,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
return 0;
}
@@ -117,6 +121,8 @@ static int ltq_gpio_direction_output(str
@@ -117,6 +121,8 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip,
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
@ -41,3 +43,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
ltq_gpio_set(chip, offset, value);
return 0;
--
1.7.7.1

247
target/linux/lantiq/patches-3.2/0015-MIPS-lantiq-add-default-configs.patch Normal file
View File

@ -0,0 +1,247 @@
From 9946990028431fc732d1244c6ccdfface1ee5640 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 11 Nov 2011 22:02:27 +0100
Subject: [PATCH 15/70] MIPS: lantiq: add default configs
This patch adds the default config for 3 Lantiq SoCs
* Danube/AR9 (xway)
* Amazon-SE
* Falc-ON
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/configs/ase_defconfig | 67 +++++++++++++++++++++++++++++++++
arch/mips/configs/falcon_defconfig | 72 ++++++++++++++++++++++++++++++++++++
arch/mips/configs/xway_defconfig | 66 +++++++++++++++++++++++++++++++++
3 files changed, 205 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/configs/ase_defconfig
create mode 100644 arch/mips/configs/falcon_defconfig
create mode 100644 arch/mips/configs/xway_defconfig
diff --git a/arch/mips/configs/ase_defconfig b/arch/mips/configs/ase_defconfig
new file mode 100644
index 0000000..5bb1d93
--- /dev/null
+++ b/arch/mips/configs/ase_defconfig
@@ -0,0 +1,67 @@
+CONFIG_LANTIQ=y
+CONFIG_SOC_AMAZON_SE=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_DEFAULT_HOSTNAME="amazon_se"
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_ROOT_GID=1000
++# CONFIG_RD_GZIP is not set
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MISC_DEVICES=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_LANTIQ_ETOP=y
+CONFIG_PHYLIB=y
+CONFIG_SERIAL_LANTIQ=y
+CONFIG_PINCTRL=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_WATCHDOG=y
+CONFIG_LANTIQ_WDT=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/mips/configs/falcon_defconfig b/arch/mips/configs/falcon_defconfig
new file mode 100644
index 0000000..ce242a8
--- /dev/null
+++ b/arch/mips/configs/falcon_defconfig
@@ -0,0 +1,72 @@
+CONFIG_LANTIQ=y
+CONFIG_SOC_FALCON=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_DEFAULT_HOSTNAME="falcon"
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_ROOT_GID=1000
++# CONFIG_RD_GZIP is not set
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MTD_M25P80=y
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT24=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_SERIAL_LANTIQ=y
+CONFIG_I2C=y
+CONFIG_I2C_FALCON=y
+CONFIG_SPI=y
+CONFIG_SPI_FALCON=y
+CONFIG_PINCTRL=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_WATCHDOG=y
+CONFIG_LANTIQ_WDT=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/mips/configs/xway_defconfig b/arch/mips/configs/xway_defconfig
new file mode 100644
index 0000000..510a964
--- /dev/null
+++ b/arch/mips/configs/xway_defconfig
@@ -0,0 +1,66 @@
+CONFIG_LANTIQ=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_DEFAULT_HOSTNAME="danube"
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_ROOT_GID=1000
+# CONFIG_RD_GZIP is not set
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MISC_DEVICES=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_LANTIQ_ETOP=y
+CONFIG_PHYLIB=y
+CONFIG_SERIAL_LANTIQ=y
+CONFIG_PINCTRL=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_WATCHDOG=y
+CONFIG_LANTIQ_WDT=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
--
1.7.7.1

38
target/linux/lantiq/patches-3.2/0016-MAINTAINERS-add-entry-for-Lantiq-related-files.patch Normal file
View File

@ -0,0 +1,38 @@
From c68f8bdcd4c58a0c1d92e20230a943e8089d865a Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 10 Nov 2011 19:32:37 +0100
Subject: [PATCH 16/70] MAINTAINERS: add entry for Lantiq related files
Adds new entry to MAINTAINERS file for Lantiq SoC related code.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
MAINTAINERS | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 62f1cd3..c04defd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4348,6 +4348,18 @@ S: Supported
F: Documentation/mips/
F: arch/mips/
+MIPS/LANTIQ
+M: John Crispin <blogic@openwrt.org>
+M: Thomas Langer <thomas.langer@lantiq.com>
+S: Maintained
+F: arch/mips/lantiq/*
+F: drivers/i2c/busses/i2c-falcon.c
+F: drivers/mtd/maps/lantiq-flash.c
+F: drivers/net/ethernet/lantiq_etop.c
+F: drivers/spi/spi-falcon.c
+F: drivers/tty/serial/lantiq.c
+F: drivers/watchdog/lantiq_wdt.c
+
MISCELLANEOUS MCA-SUPPORT
M: James Bottomley <James.Bottomley@HansenPartnership.com>
S: Maintained
--
1.7.7.1

55
target/linux/lantiq/patches-3.2/0017-MIPS-make-oprofile-use-cp0_perfcount_irq-if-it-is-se.patch Normal file
View File

@ -0,0 +1,55 @@
From bc3a07e6c5149a82a22239a43e9f98514c2010d9 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 24 Aug 2011 13:24:11 +0200
Subject: [PATCH 17/70] MIPS: make oprofile use cp0_perfcount_irq if it is set
The patch makes the oprofile code use the performance counters irq.
This patch is written by Felix Fietkau.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/oprofile/op_model_mipsxx.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1..86cf234 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -298,6 +298,11 @@ static void reset_counters(void *arg)
}
}
+static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
+{
+ return mipsxx_perfcount_handler();
+}
+
static int __init mipsxx_init(void)
{
int counters;
@@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
save_perf_irq = perf_irq;
perf_irq = mipsxx_perfcount_handler;
+ if (cp0_perfcount_irq >= 0)
+ return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
+ IRQF_SHARED, "Perfcounter", save_perf_irq);
+
return 0;
}
@@ -381,6 +390,9 @@ static void mipsxx_exit(void)
{
int counters = op_model_mipsxx_ops.num_counters;
+ if (cp0_perfcount_irq >= 0)
+ free_irq(cp0_perfcount_irq, save_perf_irq);
+
counters = counters_per_cpu_to_total(counters);
on_each_cpu(reset_counters, (void *)(long)counters, 1);
--
1.7.7.1

18
target/linux/lantiq/patches/0010-MIPS-enable-oprofile-support-on-lantiq-targets.patch → target/linux/lantiq/patches-3.2/0018-MIPS-lantiq-enable-oprofile-support-on-lantiq-target.patch
View File

@ -1,20 +1,23 @@
From cc4b9cdff8665a414ae51101d3a0ca6ed7444a27 Mon Sep 17 00:00:00 2001
From e0bd3f1b16fbce1f0f7900a0dd624f9dc8a47f78 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 24 Aug 2011 13:28:55 +0200
Subject: [PATCH 10/24] MIPS: enable oprofile support on lantiq targets
Subject: [PATCH 18/70] MIPS: lantiq: enable oprofile support on lantiq
targets
This patch sets the performance counters irq and HAVE_OPROFILE flag.
This patch sets the performance counters irq and HAVE_OPROFILE flag for Lantiq
SoCs.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/Kconfig | 1 +
arch/mips/lantiq/irq.c | 5 +++++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d46f1da..c1ceadb 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -230,6 +230,7 @@ config LANTIQ
@@ -226,6 +226,7 @@ config LANTIQ
select SWAP_IO_SPACE
select BOOT_RAW
select HAVE_CLK
@ -22,6 +25,8 @@ Cc: linux-mips@linux-mips.org
select MIPS_MACHINE
config LASAT
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 17c057f..0b2ed87 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -40,6 +40,9 @@
@ -43,3 +48,6 @@ Cc: linux-mips@linux-mips.org
}
unsigned int __cpuinit get_c0_compare_int(void)
--
1.7.7.1

93
target/linux/lantiq/patches/0015-MIPS-lantiq-adds-etop-support-for-ase-ar9.patch → target/linux/lantiq/patches-3.2/0019-NET-MIPS-lantiq-make-etop-ethernet-work-on-ase-ar9.patch
View File

@ -1,25 +1,26 @@
From c7881d8d2b3aed9a90aa37dcf797328a9cfbe7b6 Mon Sep 17 00:00:00 2001
From 4b24c79196e5777baff0f5d53b62cf2a964e26ff Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 10 Aug 2011 15:32:16 +0200
Subject: [PATCH 15/24] MIPS: lantiq: adds etop support for ase/ar9
Subject: [PATCH 19/70] NET: MIPS: lantiq: make etop ethernet work on ase/ar9
Extend the driver to handle the different DMA channel layout for AR9 and
SoCs. The patch also adds support for the integrated PHY found on Amazon-SE
and the gigabit switch found inside the AR9.
Amazon-SE SoCs. The patch also adds support for the integrated PHY found
on Amazon-SE and the gigabit switch found inside the AR9.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Cc: netdev@vger.kernel.org
---
.../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 22 +---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 10 ++
arch/mips/lantiq/xway/devices.c | 11 +-
arch/mips/lantiq/xway/mach-easy50601.c | 5 +
drivers/net/lantiq_etop.c | 172 ++++++++++++++++++--
5 files changed, 180 insertions(+), 40 deletions(-)
drivers/net/ethernet/lantiq_etop.c | 171 ++++++++++++++++++--
4 files changed, 174 insertions(+), 40 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index b4465a8..2a8d5ad 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -40,26 +40,8 @@
@@ -38,26 +38,8 @@
#define MIPS_CPU_TIMER_IRQ 7
@ -48,17 +49,19 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index e31f52d..6983d75 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -80,6 +80,7 @@
@@ -82,6 +82,7 @@
#define LTQ_PMU_SIZE 0x1000
#define PMU_DMA 0x0020
+#define PMU_EPHY 0x0080
#define PMU_USB 0x8041
#define PMU_SPI 0x0100
#define PMU_LED 0x0800
@@ -92,6 +93,10 @@
#define PMU_GPT 0x1000
@@ -93,6 +94,10 @@
#define LTQ_ETOP_BASE_ADDR 0x1E180000
#define LTQ_ETOP_SIZE 0x40000
@ -69,7 +72,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
/* DMA */
#define LTQ_DMA_BASE_ADDR 0x1E104100
#define LTQ_DMA_SIZE 0x800
@@ -146,6 +151,11 @@ extern void ltq_pmu_enable(unsigned int
@@ -147,6 +152,11 @@ extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
extern void ltq_cgu_enable(unsigned int clk);
@ -81,6 +84,8 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
static inline int ltq_is_ar9(void)
{
return (ltq_get_soc_type() == SOC_TYPE_AR9);
diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
index f97e565..eab4644d 100644
--- a/arch/mips/lantiq/xway/devices.c
+++ b/arch/mips/lantiq/xway/devices.c
@@ -74,18 +74,23 @@ void __init ltq_register_ase_asc(void)
@ -110,23 +115,18 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
if (eth) {
ltq_etop.dev.platform_data = eth;
platform_device_register(&ltq_etop);
--- a/drivers/net/lantiq_etop.c
+++ b/drivers/net/lantiq_etop.c
@@ -34,6 +34,7 @@
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/dma-mapping.h>
#include <asm/checksum.h>
@@ -69,10 +70,43 @@
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 0b3567a..d3d4931 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -71,10 +71,43 @@
#define ETOP_MII_REVERSE 0xe
#define ETOP_PLEN_UNDER 0x40
#define ETOP_CGEN 0x800
+#define ETOP_CFG_MII0 0x01
-
-/* use 2 static channels for TX/RX */
+#define ETOP_CFG_MII0 0x01
+
+#define LTQ_GBIT_MDIO_CTL 0xCC
+#define LTQ_GBIT_MDIO_DATA 0xd0
+#define LTQ_GBIT_GCTL0 0x68
@ -166,7 +166,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
@@ -81,9 +115,15 @@
@@ -83,9 +116,15 @@
#define ltq_etop_w32_mask(x, y, z) \
ltq_w32_mask(x, y, ltq_etop_membase + (z))
@ -182,7 +182,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
struct ltq_etop_chan {
int idx;
@@ -108,6 +148,9 @@ struct ltq_etop_priv {
@@ -110,6 +149,9 @@ struct ltq_etop_priv {
spinlock_t lock;
};
@ -192,7 +192,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
static int
ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
{
@@ -209,7 +252,7 @@ static irqreturn_t
@@ -211,7 +253,7 @@ static irqreturn_t
ltq_etop_dma_irq(int irq, void *_priv)
{
struct ltq_etop_priv *priv = _priv;
@ -201,7 +201,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
napi_schedule(&priv->ch[ch].napi);
return IRQ_HANDLED;
@@ -242,26 +285,66 @@ ltq_etop_hw_exit(struct net_device *dev)
@@ -244,15 +286,43 @@ ltq_etop_hw_exit(struct net_device *dev)
ltq_etop_free_channel(dev, &priv->ch[i]);
}
@ -210,8 +210,8 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+{
+ ltq_pmu_enable(PMU_SWITCH);
+
+ ltq_gpio_request(42, 1, 0, 1, "MDIO");
+ ltq_gpio_request(43, 1, 0, 1, "MDC");
+ ltq_gpio_request(42, 2, 1, "MDIO");
+ ltq_gpio_request(43, 2, 1, "MDC");
+
+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
+ /** Disable MDIO auto polling mode */
@ -238,19 +238,15 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
- switch (priv->pldata->mii_mode) {
+ if (ltq_has_gbit()) {
+ ltq_etop_gbit_init();
+ /* force the etops link to the gbit to MII */
+ mii_mode = PHY_INTERFACE_MODE_MII;
+ }
+
+ switch (mii_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RMII:
ltq_etop_w32_mask(ETOP_MII_MASK,
ETOP_MII_REVERSE, LTQ_ETOP_CFG);
break;
+ case PHY_INTERFACE_MODE_GMII:
case PHY_INTERFACE_MODE_MII:
ltq_etop_w32_mask(ETOP_MII_MASK,
ETOP_MII_NORMAL, LTQ_ETOP_CFG);
@@ -264,6 +334,18 @@ ltq_etop_hw_init(struct net_device *dev)
break;
default:
@ -269,7 +265,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
netdev_err(dev, "unknown mii mode %d\n",
priv->pldata->mii_mode);
return -ENOTSUPP;
@@ -273,7 +356,7 @@ ltq_etop_hw_init(struct net_device *dev)
@@ -275,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev)
ltq_dma_init_port(DMA_PORT_ETOP);
for (i = 0; i < MAX_DMA_CHAN; i++) {
@ -278,7 +274,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
struct ltq_etop_chan *ch = &priv->ch[i];
ch->idx = ch->dma.nr = i;
@@ -337,6 +420,39 @@ static const struct ethtool_ops ltq_etop
@@ -339,6 +421,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
};
static int
@ -318,7 +314,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
{
u32 val = MDIO_REQUEST |
@@ -377,14 +493,11 @@ ltq_etop_mdio_probe(struct net_device *d
@@ -379,14 +494,11 @@ ltq_etop_mdio_probe(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
struct phy_device *phydev = NULL;
@ -337,7 +333,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
if (!phydev) {
netdev_err(dev, "no PHY found\n");
@@ -406,6 +519,9 @@ ltq_etop_mdio_probe(struct net_device *d
@@ -408,6 +520,9 @@ ltq_etop_mdio_probe(struct net_device *dev)
| SUPPORTED_Autoneg
| SUPPORTED_MII
| SUPPORTED_TP);
@ -347,7 +343,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
phydev->advertising = phydev->supported;
priv->phydev = phydev;
@@ -431,8 +547,13 @@ ltq_etop_mdio_init(struct net_device *de
@@ -433,8 +548,13 @@ ltq_etop_mdio_init(struct net_device *dev)
}
priv->mii_bus->priv = dev;
@ -363,7 +359,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
priv->mii_bus->name = "ltq_mii";
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
@@ -522,9 +643,9 @@ ltq_etop_tx(struct sk_buff *skb, struct
@@ -524,9 +644,9 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
struct ltq_etop_priv *priv = netdev_priv(dev);
struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
@ -374,7 +370,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
@@ -698,7 +819,7 @@ ltq_etop_probe(struct platform_device *p
@@ -700,7 +820,7 @@ ltq_etop_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct ltq_etop_priv *priv;
@ -383,7 +379,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
int err;
int i;
@@ -726,6 +847,23 @@ ltq_etop_probe(struct platform_device *p
@@ -728,6 +848,23 @@ ltq_etop_probe(struct platform_device *pdev)
goto err_out;
}
@ -407,3 +403,6 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
strcpy(dev->name, "eth%d");
dev->netdev_ops = &ltq_eth_netdev_ops;
--
1.7.7.1

67
target/linux/lantiq/patches-3.2/0020-NET-MIPS-lantiq-non-existing-phy-was-not-handled-gra.patch Normal file
View File

@ -0,0 +1,67 @@
From d9cddd0b4062e66f350297b4b855ef4db3a1c16b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 15 Nov 2011 14:52:21 +0100
Subject: [PATCH 20/70] NET: MIPS: lantiq: non existing phy was not handled
gracefully
The code blindly assumed that that a PHY device was present causing a BadVA.
In addition the driver should not fail to load incase no PHY was found.
Instead we print the following line and continue with no attached PHY.
etop: mdio probe failed
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: netdev@vger.kernel.org
---
drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index d3d4931..9fd6779 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -612,7 +612,8 @@ ltq_etop_open(struct net_device *dev)
ltq_dma_open(&ch->dma);
napi_enable(&ch->napi);
}
- phy_start(priv->phydev);
+ if (priv->phydev)
+ phy_start(priv->phydev);
netif_tx_start_all_queues(dev);
return 0;
}
@@ -624,7 +625,8 @@ ltq_etop_stop(struct net_device *dev)
int i;
netif_tx_stop_all_queues(dev);
- phy_stop(priv->phydev);
+ if (priv->phydev)
+ phy_stop(priv->phydev);
for (i = 0; i < MAX_DMA_CHAN; i++) {
struct ltq_etop_chan *ch = &priv->ch[i];
@@ -770,9 +772,10 @@ ltq_etop_init(struct net_device *dev)
if (err)
goto err_netdev;
ltq_etop_set_multicast_list(dev);
- err = ltq_etop_mdio_init(dev);
- if (err)
- goto err_netdev;
+ if (!ltq_etop_mdio_init(dev))
+ dev->ethtool_ops = &ltq_etop_ethtool_ops;
+ else
+ pr_warn("etop: mdio probe failed\n");;
return 0;
err_netdev:
@@ -868,7 +871,6 @@ ltq_etop_probe(struct platform_device *pdev)
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
strcpy(dev->name, "eth%d");
dev->netdev_ops = &ltq_eth_netdev_ops;
- dev->ethtool_ops = &ltq_etop_ethtool_ops;
priv = netdev_priv(dev);
priv->res = res;
priv->pldata = dev_get_platdata(&pdev->dev);
--
1.7.7.1

71
target/linux/lantiq/patches-3.2/0021-NET-MIPS-lantiq-return-value-of-request_irq-was-not-.patch Normal file
View File

@ -0,0 +1,71 @@
From 6916ef9742e45213d524b69700d937976098d1e6 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 15 Nov 2011 15:56:06 +0100
Subject: [PATCH 21/70] NET: MIPS: lantiq: return value of request_irq was not
handled gracefully
The return values of request_irq() were not checked leading to the following
error message.
drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_hw_init':
drivers/net/ethernet/lantiq_etop.c:368:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result
drivers/net/ethernet/lantiq_etop.c:377:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: netdev@vger.kernel.org
---
drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 9fd6779..dddb9fe 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -312,6 +312,7 @@ ltq_etop_hw_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned int mii_mode = priv->pldata->mii_mode;
+ int err = 0;
int i;
ltq_pmu_enable(PMU_PPE);
@@ -356,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev)
ltq_dma_init_port(DMA_PORT_ETOP);
- for (i = 0; i < MAX_DMA_CHAN; i++) {
+ for (i = 0; i < MAX_DMA_CHAN && !err; i++) {
int irq = LTQ_DMA_ETOP + i;
struct ltq_etop_chan *ch = &priv->ch[i];
@@ -364,21 +365,22 @@ ltq_etop_hw_init(struct net_device *dev)
if (IS_TX(i)) {
ltq_dma_alloc_tx(&ch->dma);
- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+ err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
"etop_tx", priv);
} else if (IS_RX(i)) {
ltq_dma_alloc_rx(&ch->dma);
for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
ch->dma.desc++)
if (ltq_etop_alloc_skb(ch))
- return -ENOMEM;
+ err = -ENOMEM;
ch->dma.desc = 0;
- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+ err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
"etop_rx", priv);
}
- ch->dma.irq = irq;
+ if (!err)
+ ch->dma.irq = irq;
}
- return 0;
+ return err;
}
static void
--
1.7.7.1

282
target/linux/lantiq/patches-3.2/0022-MIPS-lantiq-use-devres-managed-gpios.patch Normal file
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@ -0,0 +1,282 @@
From 9819317c005d57e1a5924af1faa43f73ed156a2d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 08:37:25 +0100
Subject: [PATCH 22/70] MIPS: lantiq: use devres managed gpios
3.2 introduced devm_request_gpio() to allow managed gpios.
The devres api requires a struct device pointer to work. Add a parameter to ltq_gpio_request()
so that managed gpios can work.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 +---
arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ++++
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 ---
arch/mips/lantiq/falcon/gpio.c | 4 ++--
arch/mips/lantiq/falcon/prom.c | 7 -------
arch/mips/lantiq/xway/gpio.c | 4 ++--
arch/mips/lantiq/xway/gpio_stp.c | 13 ++++++++-----
arch/mips/pci/pci-lantiq.c | 18 ++++++++++--------
drivers/net/ethernet/lantiq_etop.c | 9 ++++++---
drivers/tty/serial/lantiq.c | 12 ++++++++++++
10 files changed, 45 insertions(+), 33 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index b074748..a5dc06a 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -126,9 +126,7 @@ extern __iomem void *ltq_sys1_membase;
#define ltq_sys1_w32_mask(clear, set, reg) \
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
-/* gpio_request wrapper to help configure the pin */
-extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
- unsigned int dir, const char *name);
+/* gpio wrapper to help configure the pin muxing */
extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
/* to keep the irq code generic we need to define these to 0 as falcon
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 188de0f..924b91a 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -37,6 +37,10 @@ extern unsigned int ltq_get_soc_type(void);
/* spinlock all ebu i/o */
extern spinlock_t ebu_lock;
+/* request a non-gpio and set the PIO config */
+extern int ltq_gpio_request(struct device *dev, unsigned int pin,
+ unsigned int mux, unsigned int dir, const char *name);
+
/* some irq helpers */
extern void ltq_disable_irq(struct irq_data *data);
extern void ltq_mask_and_ack_irq(struct irq_data *data);
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 6983d75..6c5b705 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -145,9 +145,6 @@
extern __iomem void *ltq_ebu_membase;
extern __iomem void *ltq_cgu_membase;
-/* request a non-gpio and set the PIO config */
-extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
- unsigned int dir, const char *name);
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
extern void ltq_cgu_enable(unsigned int clk);
diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
index 28f8639..a44f71b 100644
--- a/arch/mips/lantiq/falcon/gpio.c
+++ b/arch/mips/lantiq/falcon/gpio.c
@@ -97,7 +97,7 @@ int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
}
EXPORT_SYMBOL(ltq_gpio_mux_set);
-int ltq_gpio_request(unsigned int pin, unsigned int mux,
+int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux,
unsigned int dir, const char *name)
{
int port = pin / 100;
@@ -106,7 +106,7 @@ int ltq_gpio_request(unsigned int pin, unsigned int mux,
if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
return -EINVAL;
- if (gpio_request(pin, name)) {
+ if (devm_gpio_request(dev, pin, name)) {
pr_err("failed to setup lantiq gpio: %s\n", name);
return -EBUSY;
}
diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
index b50d6f9..f98b389 100644
--- a/arch/mips/lantiq/falcon/prom.c
+++ b/arch/mips/lantiq/falcon/prom.c
@@ -27,9 +27,6 @@
#define TYPE_SHIFT 26
#define TYPE_MASK 0x3C000000
-#define MUXC_SIF_RX_PIN 112
-#define MUXC_SIF_TX_PIN 113
-
/* this parameter allows us enable/disable asc1 via commandline */
static int register_asc1;
static int __init
@@ -48,10 +45,6 @@ ltq_soc_setup(void)
falcon_register_gpio();
if (register_asc1) {
ltq_register_asc(1);
- if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
- pr_err("failed to request asc1-rx");
- if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
- pr_err("failed to request asc1-tx");
ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
}
}
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index 14ff7c7..54ec6c9 100644
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -50,14 +50,14 @@ int irq_to_gpio(unsigned int gpio)
}
EXPORT_SYMBOL(irq_to_gpio);
-int ltq_gpio_request(unsigned int pin, unsigned int mux,
+int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux,
unsigned int dir, const char *name)
{
int id = 0;
if (pin >= (MAX_PORTS * PINS_PER_PORT))
return -EINVAL;
- if (gpio_request(pin, name)) {
+ if (devm_gpio_request(dev, pin, name)) {
pr_err("failed to setup lantiq gpio: %s\n", name);
return -EBUSY;
}
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index cb6f170..e6b4809 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -80,11 +80,6 @@ static struct gpio_chip ltq_stp_chip = {
static int ltq_stp_hw_init(void)
{
- /* the 3 pins used to control the external stp */
- ltq_gpio_request(4, 2, 1, "stp-st");
- ltq_gpio_request(5, 2, 1, "stp-d");
- ltq_gpio_request(6, 2, 1, "stp-sh");
-
/* sane defaults */
ltq_stp_w32(0, LTQ_STP_AR);
ltq_stp_w32(0, LTQ_STP_CPU0);
@@ -133,6 +128,14 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to remap STP memory\n");
return -ENOMEM;
}
+
+ /* the 3 pins used to control the external stp */
+ if (ltq_gpio_request(&pdev->dev, 4, 2, 1, "stp-st") ||
+ ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") ||
+ ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) {
+ dev_err(&pdev->dev, "failed to request needed gpios\n");
+ return -EBUSY;
+ }
ret = gpiochip_add(&ltq_stp_chip);
if (!ret)
ret = ltq_stp_hw_init();
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index c001c5a..47b551c 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -150,24 +150,26 @@ static u32 ltq_calc_bar11mask(void)
return bar11mask;
}
-static void ltq_pci_setup_gpio(int gpio)
+static void ltq_pci_setup_gpio(struct device *dev)
{
+ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data;
int i;
for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
- if (gpio & (1 << i)) {
- ltq_gpio_request(ltq_pci_gpio_map[i].pin,
+ if (conf->gpio & (1 << i)) {
+ ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin,
ltq_pci_gpio_map[i].mux,
ltq_pci_gpio_map[i].dir,
ltq_pci_gpio_map[i].name);
}
}
- ltq_gpio_request(21, 0, 1, "pci-reset");
- ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
+ ltq_gpio_request(dev, 21, 0, 1, "pci-reset");
+ ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
}
-static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
+static int __devinit ltq_pci_startup(struct device *dev)
{
u32 temp_buffer;
+ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data;
/* set clock to 33Mhz */
if (ltq_is_ar9()) {
@@ -190,7 +192,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
}
/* setup pci clock and gpis used by pci */
- ltq_pci_setup_gpio(conf->gpio);
+ ltq_pci_setup_gpio(dev);
/* enable auto-switching between PCI and EBU */
ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
@@ -275,7 +277,7 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
ltq_pci_controller.io_map_base =
(unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
- ltq_pci_startup(ltq_pci_data);
+ ltq_pci_startup(&pdev->dev);
register_pci_controller(&ltq_pci_controller);
return 0;
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index dddb9fe..fcbb9c7 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -291,9 +291,6 @@ ltq_etop_gbit_init(void)
{
ltq_pmu_enable(PMU_SWITCH);
- ltq_gpio_request(42, 2, 1, "MDIO");
- ltq_gpio_request(43, 2, 1, "MDC");
-
ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
/** Disable MDIO auto polling mode */
ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
@@ -868,6 +865,12 @@ ltq_etop_probe(struct platform_device *pdev)
err = -ENOMEM;
goto err_out;
}
+ if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") ||
+ ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) {
+ dev_err(&pdev->dev, "failed to request MDIO gpios\n");
+ err = -EBUSY;
+ goto err_out;
+ }
}
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 96c1cac..5d25828 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -107,6 +107,9 @@
#define ASCFSTAT_TXFREEMASK 0x3F000000
#define ASCFSTAT_TXFREEOFF 24
+#define MUXC_SIF_RX_PIN 112
+#define MUXC_SIF_TX_PIN 113
+
static void lqasc_tx_chars(struct uart_port *port);
static struct ltq_uart_port *lqasc_port[MAXPORTS];
static struct uart_driver lqasc_reg;
@@ -529,6 +532,15 @@ lqasc_request_port(struct uart_port *port)
if (port->membase == NULL)
return -ENOMEM;
}
+ if (ltq_is_falcon() && (port->line == 1)) {
+ struct ltq_uart_port *ltq_port = lqasc_port[pdev->id];
+ if (ltq_gpio_request(&pdev->dev, MUXC_SIF_RX_PIN,
+ 3, 0, "asc1-rx"))
+ return -EBUSY;
+ if (ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN,
+ 3, 1, "asc1-tx"))
+ return -EBUSY;
+ }
return 0;
}
--
1.7.7.1

49
target/linux/lantiq/patches-3.2/0023-MIPS-add-clkdev.h.patch Normal file
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@ -0,0 +1,49 @@
From aeb5a729386db036163fa21a8f5e5e1f9a735ebf Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 Feb 2012 20:23:36 +0100
Subject: [PATCH 23/70] MIPS: add clkdev.h
For clkdev to work on MIPS we need this file
include/linux/clkdev.h:#include <asm/clkdev.h>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/clkdev.h | 25 +++++++++++++++++++++++++
1 files changed, 25 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/clkdev.h
diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h
new file mode 100644
index 0000000..2624754
--- /dev/null
+++ b/arch/mips/include/asm/clkdev.h
@@ -0,0 +1,25 @@
+/*
+ * based on arch/arm/include/asm/clkdev.h
+ *
+ * Copyright (C) 2008 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Helper for the clk API to assist looking up a struct clk.
+ */
+#ifndef __ASM_CLKDEV_H
+#define __ASM_CLKDEV_H
+
+#include <linux/slab.h>
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+ return kzalloc(size, GFP_KERNEL);
+}
+
+#endif
--
1.7.7.1

59
target/linux/lantiq/patches-3.2/0024-MIPS-lantiq-helper-functions-for-SoC-detection.patch Normal file
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@ -0,0 +1,59 @@
From 8b47a5997efb253459fa62acce9c52202cbec9da Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 21 Feb 2012 14:25:03 +0100
Subject: [PATCH 24/70] MIPS: lantiq: helper functions for SoC detection
Add additional functions for runtime soc detection. We need these for the
serial driver.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 16 ++++++++++++++--
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 5 +++++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index a5dc06a..0aa1f16 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -134,8 +134,20 @@ extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
#define LTQ_EIU_BASE_ADDR 0
#define LTQ_EBU_PCC_ISTAT 0
-#define ltq_is_ar9() 0
-#define ltq_is_vr9() 0
+static inline int ltq_is_ar9(void)
+{
+ return 0;
+}
+
+static inline int ltq_is_vr9(void)
+{
+ return 0;
+}
+
+static inline int ltq_is_falcon(void)
+{
+ return 1;
+}
#endif /* CONFIG_SOC_FALCON */
#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 6c5b705..45e480c 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -164,5 +164,10 @@ static inline int ltq_is_vr9(void)
return (ltq_get_soc_type() == SOC_TYPE_VR9);
}
+static inline int ltq_is_falcon(void)
+{
+ return 0;
+}
+
#endif /* CONFIG_SOC_TYPE_XWAY */
#endif /* _LTQ_XWAY_H__ */
--
1.7.7.1

299
target/linux/lantiq/patches-3.2/0025-MIPS-lantiq-convert-to-clkdev-api.patch Normal file
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@ -0,0 +1,299 @@
From 25db3804c7c9ed3ee5161b00b38de84b1d19f6a8 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 08:39:06 +0100
Subject: [PATCH 25/70] MIPS: lantiq: convert to clkdev api
* Change setup from HAVE_CLK -> HAVE_MACH_CLKDEV/CLKDEV_LOOKUP
* Add clk_activate/clk_deactivate
* Add better error paths to the clk_*() functions
* Change the way our static clocks are referenced
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/Kconfig | 3 +-
arch/mips/include/asm/mach-lantiq/lantiq.h | 20 ++----
arch/mips/lantiq/clk.c | 96 +++++++++++++++------------
arch/mips/lantiq/clk.h | 52 ++++++++++++++-
arch/mips/lantiq/prom.c | 1 -
5 files changed, 111 insertions(+), 61 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c1ceadb..1b78cd7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -225,7 +225,8 @@ config LANTIQ
select ARCH_REQUIRE_GPIOLIB
select SWAP_IO_SPACE
select BOOT_RAW
- select HAVE_CLK
+ select HAVE_MACH_CLKDEV
+ select CLKDEV_LOOKUP
select HAVE_OPROFILE
select MIPS_MACHINE
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 924b91a..622847f 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -9,6 +9,7 @@
#define _LANTIQ_H__
#include <linux/irq.h>
+#include <linux/clk.h>
#include <linux/ioport.h>
/* generic reg access functions */
@@ -22,18 +23,6 @@
extern unsigned int ltq_get_cpu_ver(void);
extern unsigned int ltq_get_soc_type(void);
-/* clock speeds */
-#define CLOCK_60M 60000000
-#define CLOCK_83M 83333333
-#define CLOCK_100M 100000000
-#define CLOCK_111M 111111111
-#define CLOCK_133M 133333333
-#define CLOCK_167M 166666667
-#define CLOCK_200M 200000000
-#define CLOCK_266M 266666666
-#define CLOCK_333M 333333333
-#define CLOCK_400M 400000000
-
/* spinlock all ebu i/o */
extern spinlock_t ebu_lock;
@@ -46,6 +35,13 @@ extern void ltq_disable_irq(struct irq_data *data);
extern void ltq_mask_and_ack_irq(struct irq_data *data);
extern void ltq_enable_irq(struct irq_data *data);
+/* clock handling */
+extern int clk_activate(struct clk *clk);
+extern void clk_deactivate(struct clk *clk);
+extern struct clk *clk_get_cpu(void);
+extern struct clk *clk_get_fpi(void);
+extern struct clk *clk_get_io(void);
+
/* find out what caused the last cpu reset */
extern int ltq_reset_cause(void);
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 39eef7f..84a201e 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -12,6 +12,7 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/clk.h>
+#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/list.h>
@@ -24,33 +25,29 @@
#include "clk.h"
#include "prom.h"
-struct clk {
- const char *name;
- unsigned long rate;
- unsigned long (*get_rate) (void);
-};
+/* lantiq socs have 3 static clocks */
+static struct clk cpu_clk_generic[3];
-static struct clk *cpu_clk;
-static int cpu_clk_cnt;
+void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
+{
+ cpu_clk_generic[0].rate = cpu;
+ cpu_clk_generic[1].rate = fpi;
+ cpu_clk_generic[2].rate = io;
+}
-/* lantiq socs have 3 static clocks */
-static struct clk cpu_clk_generic[] = {
- {
- .name = "cpu",
- .get_rate = ltq_get_cpu_hz,
- }, {
- .name = "fpi",
- .get_rate = ltq_get_fpi_hz,
- }, {
- .name = "io",
- .get_rate = ltq_get_io_region_clock,
- },
-};
-
-void clk_init(void)
+struct clk *clk_get_cpu(void)
+{
+ return &cpu_clk_generic[0];
+}
+
+struct clk *clk_get_fpi(void)
{
- cpu_clk = cpu_clk_generic;
- cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
+ return &cpu_clk_generic[1];
+}
+
+struct clk *clk_get_io(void)
+{
+ return &cpu_clk_generic[2];
}
static inline int clk_good(struct clk *clk)
@@ -73,36 +70,49 @@ unsigned long clk_get_rate(struct clk *clk)
}
EXPORT_SYMBOL(clk_get_rate);
-struct clk *clk_get(struct device *dev, const char *id)
+int clk_enable(struct clk *clk)
{
- int i;
+ if (unlikely(!clk_good(clk)))
+ return -1;
+
+ if (clk->enable)
+ return clk->enable(clk);
- for (i = 0; i < cpu_clk_cnt; i++)
- if (!strcmp(id, cpu_clk[i].name))
- return &cpu_clk[i];
- BUG();
- return ERR_PTR(-ENOENT);
+ return -1;
}
-EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_enable);
-void clk_put(struct clk *clk)
+void clk_disable(struct clk *clk)
{
- /* not used */
+ if (unlikely(!clk_good(clk)))
+ return;
+
+ if (clk->disable)
+ clk->disable(clk);
}
-EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_disable);
-int clk_enable(struct clk *clk)
+int clk_activate(struct clk *clk)
{
- /* not used */
- return 0;
+ if (unlikely(!clk_good(clk)))
+ return -1;
+
+ if (clk->activate)
+ return clk->activate(clk);
+
+ return -1;
}
-EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_activate);
-void clk_disable(struct clk *clk)
+void clk_deactivate(struct clk *clk)
{
- /* not used */
+ if (unlikely(!clk_good(clk)))
+ return;
+
+ if (clk->deactivate)
+ clk->deactivate(clk);
}
-EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_deactivate);
static inline u32 ltq_get_counter_resolution(void)
{
@@ -126,7 +136,7 @@ void __init plat_time_init(void)
ltq_soc_init();
- clk = clk_get(0, "cpu");
+ clk = clk_get_cpu();
mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
write_c0_compare(read_c0_count());
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
index 3328925..d047768 100644
--- a/arch/mips/lantiq/clk.h
+++ b/arch/mips/lantiq/clk.h
@@ -9,10 +9,54 @@
#ifndef _LTQ_CLK_H__
#define _LTQ_CLK_H__
-extern void clk_init(void);
+#include <linux/clkdev.h>
-extern unsigned long ltq_get_cpu_hz(void);
-extern unsigned long ltq_get_fpi_hz(void);
-extern unsigned long ltq_get_io_region_clock(void);
+/* clock speeds */
+#define CLOCK_60M 60000000
+#define CLOCK_62_5M 62500000
+#define CLOCK_83M 83333333
+#define CLOCK_83_5M 83500000
+#define CLOCK_98_304M 98304000
+#define CLOCK_100M 100000000
+#define CLOCK_111M 111111111
+#define CLOCK_125M 125000000
+#define CLOCK_133M 133333333
+#define CLOCK_150M 150000000
+#define CLOCK_166M 166666666
+#define CLOCK_167M 166666667
+#define CLOCK_196_608M 196608000
+#define CLOCK_200M 200000000
+#define CLOCK_250M 250000000
+#define CLOCK_266M 266666666
+#define CLOCK_300M 300000000
+#define CLOCK_333M 333333333
+#define CLOCK_393M 393215332
+#define CLOCK_400M 400000000
+#define CLOCK_500M 500000000
+#define CLOCK_600M 600000000
+
+struct clk {
+ struct clk_lookup cl;
+ unsigned long rate;
+ unsigned long (*get_rate) (void);
+ unsigned int module;
+ unsigned int bits;
+ int (*enable) (struct clk *clk);
+ void (*disable) (struct clk *clk);
+ int (*activate) (struct clk *clk);
+ void (*deactivate) (struct clk *clk);
+ void (*reboot) (struct clk *clk);
+};
+
+extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
+ unsigned long io);
+
+extern unsigned long ltq_danube_cpu_hz(void);
+extern unsigned long ltq_danube_fpi_hz(void);
+extern unsigned long ltq_danube_io_region_clock(void);
+
+extern unsigned long ltq_vr9_cpu_hz(void);
+extern unsigned long ltq_vr9_fpi_hz(void);
+extern unsigned long ltq_vr9_io_region_clock(void);
#endif
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index acb8921..971554b 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -103,7 +103,6 @@ EXPORT_SYMBOL(ltq_remap_resource);
void __init prom_init(void)
{
ltq_soc_detect(&soc_info);
- clk_init();
snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
soc_info.name, soc_info.rev_type);
soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
--
1.7.7.1

736
target/linux/lantiq/patches-3.2/0026-MIPS-lantiq-convert-xway-to-clkdev-api.patch Normal file
View File

@ -0,0 +1,736 @@
From 418e330dc60aaabdb5cf4509ec08cce07d63f32e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 11:18:22 +0100
Subject: [PATCH 26/70] MIPS: lantiq: convert xway to clkdev api
Unify xway/ase clock code and add clkdev hooks to sysctrl.c
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 13 --
arch/mips/lantiq/xway/Makefile | 6 +-
arch/mips/lantiq/xway/clk-ase.c | 48 ----
arch/mips/lantiq/xway/clk-xway.c | 223 -------------------
arch/mips/lantiq/xway/clk.c | 227 ++++++++++++++++++++
arch/mips/lantiq/xway/sysctrl.c | 104 ++++++++-
6 files changed, 325 insertions(+), 296 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/clk-ase.c
delete mode 100644 arch/mips/lantiq/xway/clk-xway.c
create mode 100644 arch/mips/lantiq/xway/clk.c
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 45e480c..e9d2dd4 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -81,15 +81,6 @@
#define LTQ_PMU_BASE_ADDR 0x1F102000
#define LTQ_PMU_SIZE 0x1000
-#define PMU_DMA 0x0020
-#define PMU_EPHY 0x0080
-#define PMU_USB 0x8041
-#define PMU_LED 0x0800
-#define PMU_GPT 0x1000
-#define PMU_PPE 0x2000
-#define PMU_FPI 0x4000
-#define PMU_SWITCH 0x10000000
-
/* ETOP - ethernet */
#define LTQ_ETOP_BASE_ADDR 0x1E180000
#define LTQ_ETOP_SIZE 0x40000
@@ -145,10 +136,6 @@
extern __iomem void *ltq_ebu_membase;
extern __iomem void *ltq_cgu_membase;
-extern void ltq_pmu_enable(unsigned int module);
-extern void ltq_pmu_disable(unsigned int module);
-extern void ltq_cgu_enable(unsigned int clk);
-
static inline int ltq_is_ase(void)
{
return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 6678402..4dcb96f 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1,7 @@
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
+obj-$(CONFIG_SOC_XWAY) += prom-xway.o
+obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
deleted file mode 100644
index 6522583..0000000
--- a/arch/mips/lantiq/xway/clk-ase.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/time.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <lantiq_soc.h>
-
-/* cgu registers */
-#define LTQ_CGU_SYS 0x0010
-
-unsigned int ltq_get_io_region_clock(void)
-{
- return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int ltq_get_fpi_bus_clock(int fpi)
-{
- return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
-
-unsigned int ltq_get_cpu_hz(void)
-{
- if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
- return CLOCK_266M;
- else
- return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int ltq_get_fpi_hz(void)
-{
- return CLOCK_133M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
deleted file mode 100644
index 696b1a3..0000000
--- a/arch/mips/lantiq/xway/clk-xway.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/time.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
-
-#include <lantiq_soc.h>
-
-static unsigned int ltq_ram_clocks[] = {
- CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
-#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
-
-#define BASIC_FREQUENCY_1 35328000
-#define BASIC_FREQUENCY_2 36000000
-#define BASIS_REQUENCY_USB 12000000
-
-#define GET_BITS(x, msb, lsb) \
- (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-
-#define LTQ_CGU_PLL0_CFG 0x0004
-#define LTQ_CGU_PLL1_CFG 0x0008
-#define LTQ_CGU_PLL2_CFG 0x000C
-#define LTQ_CGU_SYS 0x0010
-#define LTQ_CGU_UPDATE 0x0014
-#define LTQ_CGU_IF_CLK 0x0018
-#define LTQ_CGU_OSC_CON 0x001C
-#define LTQ_CGU_SMD 0x0020
-#define LTQ_CGU_CT1SR 0x0028
-#define LTQ_CGU_CT2SR 0x002C
-#define LTQ_CGU_PCMCR 0x0030
-#define LTQ_CGU_PCI_CR 0x0034
-#define LTQ_CGU_PD_PC 0x0038
-#define LTQ_CGU_FMR 0x003C
-
-#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
-#define CGU_PLL0_BYPASS \
- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
-#define CGU_PLL0_CFG_DSMSEL \
- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
-#define CGU_PLL0_CFG_FRAC_EN \
- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
-#define CGU_PLL1_SRC \
- (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
-#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
- (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
-#define CGU_SYS_FPI_SEL (1 << 6)
-#define CGU_SYS_DDR_SEL 0x3
-#define CGU_PLL0_SRC (1 << 29)
-
-#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
-#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
-#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
-#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
-#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
-
-static unsigned int ltq_get_pll0_fdiv(void);
-
-static inline unsigned int get_input_clock(int pll)
-{
- switch (pll) {
- case 0:
- if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
- return BASIS_REQUENCY_USB;
- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
- return BASIC_FREQUENCY_1;
- else
- return BASIC_FREQUENCY_2;
- case 1:
- if (CGU_PLL1_SRC)
- return BASIS_REQUENCY_USB;
- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
- return BASIC_FREQUENCY_1;
- else
- return BASIC_FREQUENCY_2;
- case 2:
- switch (CGU_PLL2_SRC) {
- case 0:
- return ltq_get_pll0_fdiv();
- case 1:
- return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
- BASIC_FREQUENCY_1 :
- BASIC_FREQUENCY_2;
- case 2:
- return BASIS_REQUENCY_USB;
- }
- default:
- return 0;
- }
-}
-
-static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
-{
- u64 res, clock = get_input_clock(pll);
-
- res = num * clock;
- do_div(res, den);
- return res;
-}
-
-static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
- unsigned int K)
-{
- unsigned int num = ((N + 1) << 10) + K;
- unsigned int den = (M + 1) << 10;
-
- return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
- unsigned int K)
-{
- unsigned int num = ((N + 1) << 11) + K + 512;
- unsigned int den = (M + 1) << 11;
-
- return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
- unsigned int K)
-{
- unsigned int num = K >= 512 ?
- ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
- unsigned int den = (M + 1) << 12;
-
- return cal_dsm(pll, num, den);
-}
-
-static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
- unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
-{
- if (!dsmsel)
- return mash_dsm(pll, M, N, K);
- else if (!phase_div_en)
- return mash_dsm(pll, M, N, K);
- else
- return ssff_dsm_2(pll, M, N, K);
-}
-
-static inline unsigned int ltq_get_pll0_fosc(void)
-{
- if (CGU_PLL0_BYPASS)
- return get_input_clock(0);
- else
- return !CGU_PLL0_CFG_FRAC_EN
- ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
- CGU_PLL0_CFG_DSMSEL,
- CGU_PLL0_PHASE_DIVIDER_ENABLE)
- : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
- CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
- CGU_PLL0_PHASE_DIVIDER_ENABLE);
-}
-
-static unsigned int ltq_get_pll0_fdiv(void)
-{
- unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
-
- return (ltq_get_pll0_fosc() + (div >> 1)) / div;
-}
-
-unsigned int ltq_get_io_region_clock(void)
-{
- unsigned int ret = ltq_get_pll0_fosc();
-
- switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
- default:
- case 0:
- return (ret + 1) / 2;
- case 1:
- return (ret * 2 + 2) / 5;
- case 2:
- return (ret + 1) / 3;
- case 3:
- return (ret + 2) / 4;
- }
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int ltq_get_fpi_bus_clock(int fpi)
-{
- unsigned int ret = ltq_get_io_region_clock();
-
- if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
- ret >>= 1;
- return ret;
-}
-EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
-
-unsigned int ltq_get_cpu_hz(void)
-{
- switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
- case 0:
- return CLOCK_333M;
- case 4:
- return DDR_HZ;
- case 8:
- return DDR_HZ << 1;
- default:
- return DDR_HZ >> 1;
- }
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int ltq_get_fpi_hz(void)
-{
- unsigned int ddr_clock = DDR_HZ;
-
- if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
- return ddr_clock >> 1;
- return ddr_clock;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
new file mode 100644
index 0000000..f3b50fc
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk.c
@@ -0,0 +1,227 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <lantiq_soc.h>
+
+#include "../clk.h"
+
+static unsigned int ltq_ram_clocks[] = {
+ CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
+#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
+
+#define BASIC_FREQUENCY_1 35328000
+#define BASIC_FREQUENCY_2 36000000
+#define BASIS_REQUENCY_USB 12000000
+
+#define GET_BITS(x, msb, lsb) \
+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
+
+/* legacy xway clock */
+#define LTQ_CGU_PLL0_CFG 0x0004
+#define LTQ_CGU_PLL1_CFG 0x0008
+#define LTQ_CGU_PLL2_CFG 0x000C
+#define LTQ_CGU_SYS 0x0010
+#define LTQ_CGU_UPDATE 0x0014
+#define LTQ_CGU_IF_CLK 0x0018
+#define LTQ_CGU_OSC_CON 0x001C
+#define LTQ_CGU_SMD 0x0020
+#define LTQ_CGU_CT1SR 0x0028
+#define LTQ_CGU_CT2SR 0x002C
+#define LTQ_CGU_PCMCR 0x0030
+#define LTQ_CGU_PCI_CR 0x0034
+#define LTQ_CGU_PD_PC 0x0038
+#define LTQ_CGU_FMR 0x003C
+
+#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
+#define CGU_PLL0_BYPASS \
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
+#define CGU_PLL0_CFG_DSMSEL \
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
+#define CGU_PLL0_CFG_FRAC_EN \
+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
+#define CGU_PLL1_SRC \
+ (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
+#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
+ (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
+#define CGU_SYS_FPI_SEL (1 << 6)
+#define CGU_SYS_DDR_SEL 0x3
+#define CGU_PLL0_SRC (1 << 29)
+
+#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
+#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
+#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
+#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
+#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
+
+/* vr9 clock */
+#define LTQ_CGU_SYS_VR9 0x0c
+#define LTQ_CGU_IF_CLK_VR9 0x24
+
+
+static unsigned int ltq_get_pll0_fdiv(void);
+
+static inline unsigned int get_input_clock(int pll)
+{
+ switch (pll) {
+ case 0:
+ if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
+ return BASIS_REQUENCY_USB;
+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+ return BASIC_FREQUENCY_1;
+ else
+ return BASIC_FREQUENCY_2;
+ case 1:
+ if (CGU_PLL1_SRC)
+ return BASIS_REQUENCY_USB;
+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+ return BASIC_FREQUENCY_1;
+ else
+ return BASIC_FREQUENCY_2;
+ case 2:
+ switch (CGU_PLL2_SRC) {
+ case 0:
+ return ltq_get_pll0_fdiv();
+ case 1:
+ return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
+ BASIC_FREQUENCY_1 :
+ BASIC_FREQUENCY_2;
+ case 2:
+ return BASIS_REQUENCY_USB;
+ }
+ default:
+ return 0;
+ }
+}
+
+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
+{
+ u64 res, clock = get_input_clock(pll);
+
+ res = num * clock;
+ do_div(res, den);
+ return res;
+}
+
+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
+ unsigned int K)
+{
+ unsigned int num = ((N + 1) << 10) + K;
+ unsigned int den = (M + 1) << 10;
+
+ return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
+ unsigned int K)
+{
+ unsigned int num = ((N + 1) << 11) + K + 512;
+ unsigned int den = (M + 1) << 11;
+
+ return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
+ unsigned int K)
+{
+ unsigned int num = K >= 512 ?
+ ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
+ unsigned int den = (M + 1) << 12;
+
+ return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
+ unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
+{
+ if (!dsmsel)
+ return mash_dsm(pll, M, N, K);
+ else if (!phase_div_en)
+ return mash_dsm(pll, M, N, K);
+ else
+ return ssff_dsm_2(pll, M, N, K);
+}
+
+static inline unsigned int ltq_get_pll0_fosc(void)
+{
+ if (CGU_PLL0_BYPASS)
+ return get_input_clock(0);
+ else
+ return !CGU_PLL0_CFG_FRAC_EN
+ ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
+ CGU_PLL0_CFG_DSMSEL,
+ CGU_PLL0_PHASE_DIVIDER_ENABLE)
+ : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
+ CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
+ CGU_PLL0_PHASE_DIVIDER_ENABLE);
+}
+
+static unsigned int ltq_get_pll0_fdiv(void)
+{
+ unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
+
+ return (ltq_get_pll0_fosc() + (div >> 1)) / div;
+}
+
+unsigned long ltq_danube_io_region_clock(void)
+{
+ unsigned int ret = ltq_get_pll0_fosc();
+
+ switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
+ default:
+ case 0:
+ return (ret + 1) / 2;
+ case 1:
+ return (ret * 2 + 2) / 5;
+ case 2:
+ return (ret + 1) / 3;
+ case 3:
+ return (ret + 2) / 4;
+ }
+}
+
+unsigned long ltq_danube_fpi_bus_clock(int fpi)
+{
+ unsigned long ret = ltq_danube_io_region_clock();
+
+ if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
+ ret >>= 1;
+ return ret;
+}
+
+unsigned long ltq_danube_cpu_hz(void)
+{
+ switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
+ case 0:
+ return CLOCK_333M;
+ case 4:
+ return DDR_HZ;
+ case 8:
+ return DDR_HZ << 1;
+ default:
+ return DDR_HZ >> 1;
+ }
+}
+
+unsigned long ltq_danube_fpi_hz(void)
+{
+ unsigned long ddr_clock = DDR_HZ;
+
+ if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
+ return ddr_clock >> 1;
+ return ddr_clock;
+}
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 8fd13a1..c5782b5 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -8,17 +8,48 @@
#include <linux/ioport.h>
#include <linux/export.h>
+#include <linux/clkdev.h>
#include <lantiq_soc.h>
+#include "../clk.h"
#include "../devices.h"
/* clock control register */
#define LTQ_CGU_IFCCR 0x0018
+/* system clock register */
+#define LTQ_CGU_SYS 0x0010
/* the enable / disable registers */
#define LTQ_PMU_PWDCR 0x1C
#define LTQ_PMU_PWDSR 0x20
+#define LTQ_PMU_PWDCR1 0x24
+#define LTQ_PMU_PWDSR1 0x28
+
+#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR))
+#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR))
+
+/* CGU - clock generation unit */
+#define CGU_EPHY 0x10
+
+/* PMU - power management unit */
+#define PMU_DMA 0x0020
+#define PMU_SPI 0x0100
+#define PMU_EPHY 0x0080
+#define PMU_USB 0x8041
+#define PMU_STP 0x0800
+#define PMU_GPT 0x1000
+#define PMU_PPE 0x2000
+#define PMU_FPI 0x4000
+#define PMU_SWITCH 0x10000000
+#define PMU_AHBS 0x2000
+#define PMU_AHBM 0x8000
+#define PMU_PCIE_CLK 0x80000000
+
+#define PMU1_PCIE_PHY 0x0001
+#define PMU1_PCIE_CTL 0x0002
+#define PMU1_PCIE_MSI 0x0020
+#define PMU1_PCIE_PDI 0x0010
#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
@@ -36,28 +67,64 @@ void __iomem *ltq_cgu_membase;
void __iomem *ltq_ebu_membase;
static void __iomem *ltq_pmu_membase;
-void ltq_cgu_enable(unsigned int clk)
+static int ltq_cgu_enable(struct clk *clk)
{
- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR);
+ return 0;
}
-void ltq_pmu_enable(unsigned int module)
+static void ltq_cgu_disable(struct clk *clk)
+{
+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR);
+}
+
+static int ltq_pmu_enable(struct clk *clk)
{
int err = 1000000;
- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
- do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
+ ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits,
+ PWDCR(clk->module));
+ do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits));
if (!err)
panic("activating PMU module failed!\n");
+
+ return 0;
}
-EXPORT_SYMBOL(ltq_pmu_enable);
-void ltq_pmu_disable(unsigned int module)
+static void ltq_pmu_disable(struct clk *clk)
{
- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
+ ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR);
+}
+
+static inline void clkdev_add_pmu(const char *dev, const char *con,
+ unsigned int module, unsigned int bits)
+{
+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+ clk->cl.dev_id = dev;
+ clk->cl.con_id = con;
+ clk->cl.clk = clk;
+ clk->enable = ltq_pmu_enable;
+ clk->disable = ltq_pmu_disable;
+ clk->module = module;
+ clk->bits = bits;
+ clkdev_add(&clk->cl);
+}
+
+static inline void clkdev_add_cgu(const char *dev, const char *con,
+ unsigned int bits)
+{
+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+ clk->cl.dev_id = dev;
+ clk->cl.con_id = con;
+ clk->cl.clk = clk;
+ clk->enable = ltq_cgu_enable;
+ clk->disable = ltq_cgu_disable;
+ clk->bits = bits;
+ clkdev_add(&clk->cl);
}
-EXPORT_SYMBOL(ltq_pmu_disable);
void __init ltq_soc_init(void)
{
@@ -75,4 +142,23 @@ void __init ltq_soc_init(void)
/* make sure to unprotect the memory region where flash is located */
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
+
+ /* add our clocks */
+ clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
+ clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
+ clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
+ clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
+ if (ltq_is_ase()) {
+ if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
+ clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
+ else
+ clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
+ clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
+ clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
+ } else {
+ clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
+ ltq_danube_io_region_clock());
+ if (ltq_is_ar9())
+ clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
+ }
}
--
1.7.7.1

244
target/linux/lantiq/patches-3.2/0027-MIPS-lantiq-convert-falcon-to-clkdev-api.patch Normal file
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@ -0,0 +1,244 @@
From 07c4da1cf419022e5874c881511f051bb81e984e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 11:19:11 +0100
Subject: [PATCH 27/70] MIPS: lantiq: convert falcon to clkdev api
Unify sysctrl/clock code and add clkdev hooks to sysctrl.c
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 8 +-
arch/mips/lantiq/falcon/Makefile | 2 +-
arch/mips/lantiq/falcon/sysctrl.c | 129 ++++++++++++--------
3 files changed, 80 insertions(+), 59 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index 0aa1f16..120c56c 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -95,6 +95,7 @@
/* Activation Status Register */
#define ACTS_ASC1_ACT 0x00000800
+#define ACTS_I2C_ACT 0x00004000
#define ACTS_P0 0x00010000
#define ACTS_P1 0x00010000
#define ACTS_P2 0x00020000
@@ -106,13 +107,6 @@
#define ACTS_PADCTRL3 0x00200000
#define ACTS_PADCTRL4 0x00400000
-extern void ltq_sysctl_activate(int module, unsigned int mask);
-extern void ltq_sysctl_deactivate(int module, unsigned int mask);
-extern void ltq_sysctl_clken(int module, unsigned int mask);
-extern void ltq_sysctl_clkdis(int module, unsigned int mask);
-extern void ltq_sysctl_reboot(int module, unsigned int mask);
-extern int ltq_gpe_is_activated(unsigned int mask);
-
/* global register ranges */
extern __iomem void *ltq_ebu_membase;
extern __iomem void *ltq_sys1_membase;
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
index 56b22eb..3634154 100644
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1,2 +1,2 @@
-obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
+obj-y := prom.o reset.o sysctrl.o devices.o gpio.o
obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 905a142..900f0e5 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -9,11 +9,13 @@
#include <linux/ioport.h>
#include <linux/export.h>
+#include <linux/clkdev.h>
#include <asm/delay.h>
#include <lantiq_soc.h>
#include "devices.h"
+#include "../clk.h"
/* infrastructure control register */
#define SYS1_INFRAC 0x00bc
@@ -38,6 +40,10 @@
#define LTQ_SYSCTL_DEACT 0x0028
/* reboot Register */
#define LTQ_SYSCTL_RBT 0x002c
+/* CPU0 Clock Control Register */
+#define LTQ_SYS1_CPU0CC 0x0040
+/* clock divider bit */
+#define LTQ_CPU0CC_CPUDIV 0x0001
static struct resource ltq_sysctl_res[] = {
MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
@@ -64,79 +70,67 @@ void __iomem *ltq_ebu_membase;
#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x))
static inline void
-ltq_sysctl_wait(int module, unsigned int mask,
+ltq_sysctl_wait(struct clk *clk,
unsigned int test, unsigned int reg)
{
int err = 1000000;
- do {} while (--err && ((ltq_reg_r32(module, reg)
- & mask) != test));
+ do {} while (--err && ((ltq_reg_r32(clk->module, reg)
+ & clk->bits) != test));
if (!err)
- pr_err("module de/activation failed %d %08X %08X\n",
- module, mask, test);
+ pr_err("module de/activation failed %d %08X %08X %08X\n",
+ clk->module, clk->bits, test,
+ ltq_reg_r32(clk->module, reg) & clk->bits);
}
-void
-ltq_sysctl_activate(int module, unsigned int mask)
+static int
+ltq_sysctl_activate(struct clk *clk)
{
- if (module > SYSCTL_SYSGPE)
- return;
-
- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
- ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
- ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT);
+ ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
+ return 0;
}
-EXPORT_SYMBOL(ltq_sysctl_activate);
-void
-ltq_sysctl_deactivate(int module, unsigned int mask)
+static void
+ltq_sysctl_deactivate(struct clk *clk)
{
- if (module > SYSCTL_SYSGPE)
- return;
-
- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
- ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
- ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS);
+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT);
+ ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS);
}
-EXPORT_SYMBOL(ltq_sysctl_deactivate);
-void
-ltq_sysctl_clken(int module, unsigned int mask)
+static int
+ltq_sysctl_clken(struct clk *clk)
{
- if (module > SYSCTL_SYSGPE)
- return;
-
- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
- ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS);
+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN);
+ ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS);
+ return 0;
}
-EXPORT_SYMBOL(ltq_sysctl_clken);
-void
-ltq_sysctl_clkdis(int module, unsigned int mask)
+static void
+ltq_sysctl_clkdis(struct clk *clk)
{
- if (module > SYSCTL_SYSGPE)
- return;
-
- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
- ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS);
+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR);
+ ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS);
}
-EXPORT_SYMBOL(ltq_sysctl_clkdis);
-void
-ltq_sysctl_reboot(int module, unsigned int mask)
+static void
+ltq_sysctl_reboot(struct clk *clk)
{
unsigned int act;
-
- if (module > SYSCTL_SYSGPE)
- return;
-
- act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
- if ((~act & mask) != 0)
- ltq_sysctl_activate(module, ~act & mask);
- ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
- ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+ unsigned int bits;
+
+ act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT);
+ bits = ~act & clk->bits;
+ if (bits != 0) {
+ ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN);
+ ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT);
+ ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS);
+ }
+ ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT);
+ ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS);
}
-EXPORT_SYMBOL(ltq_sysctl_reboot);
/* enable the ONU core */
static void
@@ -167,6 +161,24 @@ ltq_gpe_enable(void)
udelay(1);
}
+static inline void
+clkdev_add_sys(const char *dev, unsigned int module,
+ unsigned int bits)
+{
+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+ clk->cl.dev_id = dev;
+ clk->cl.con_id = NULL;
+ clk->cl.clk = clk;
+ clk->module = module;
+ clk->activate = ltq_sysctl_activate;
+ clk->deactivate = ltq_sysctl_deactivate;
+ clk->enable = ltq_sysctl_clken;
+ clk->disable = ltq_sysctl_clkdis;
+ clk->reboot = ltq_sysctl_reboot;
+ clkdev_add(&clk->cl);
+}
+
void __init
ltq_soc_init(void)
{
@@ -180,4 +192,19 @@ ltq_soc_init(void)
ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
ltq_gpe_enable();
+
+ /* get our 3 static rates for cpu, fpi and io clocks */
+ if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
+ clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
+ else
+ clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
+
+ /* add our clock domains */
+ clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0);
+ clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
+ clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2);
+ clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3);
+ clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4);
+ clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT);
+ clkdev_add_sys("falcon_i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
}
--
1.7.7.1

65
target/linux/lantiq/patches-3.2/0028-MIPS-lantiq-convert-dma-driver-to-clkdev-api.patch Normal file
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@ -0,0 +1,65 @@
From e6a19ba12790d04267a9f052a3dc64fa1a8cac16 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 11:21:08 +0100
Subject: [PATCH 28/70] MIPS: lantiq: convert dma driver to clkdev api
Update from old pmu_{dis,en}able() to ckldev api.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/Makefile.rej | 11 +++++++++++
arch/mips/lantiq/xway/dma.c | 6 +++++-
2 files changed, 16 insertions(+), 1 deletions(-)
create mode 100644 arch/mips/lantiq/xway/Makefile.rej
diff --git a/arch/mips/lantiq/xway/Makefile.rej b/arch/mips/lantiq/xway/Makefile.rej
new file mode 100644
index 0000000..c0d5b52
--- /dev/null
+++ b/arch/mips/lantiq/xway/Makefile.rej
@@ -0,0 +1,11 @@
+--- arch/mips/lantiq/xway/Makefile
++++ arch/mips/lantiq/xway/Makefile
+@@ -1,7 +1,4 @@
+-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
+-
+-obj-$(CONFIG_SOC_XWAY) += prom-xway.o
+-obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
++obj-y := prom.o sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
+
+ obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
+ obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 60cd11f..388f1aa 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -20,6 +20,7 @@
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/export.h>
+#include <linux/clk.h>
#include <lantiq_soc.h>
#include <xway_dma.h>
@@ -216,6 +217,7 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port);
int __init
ltq_dma_init(void)
{
+ struct clk *clk;
int i;
/* remap dma register range */
@@ -224,7 +226,9 @@ ltq_dma_init(void)
panic("Failed to remap dma memory\n");
/* power up and reset the dma engine */
- ltq_pmu_enable(PMU_DMA);
+ clk = clk_get_sys("ltq_dma", NULL);
+ WARN_ON(!clk);
+ clk_enable(clk);
ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
/* disable all interrupts */
--
1.7.7.1

60
target/linux/lantiq/patches-3.2/0029-MIPS-lantiq-convert-gpio_stp-driver-to-clkdev-api.patch Normal file
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@ -0,0 +1,60 @@
From 81cf50fd6cfff13e06cd587094f5094dec32d57d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 11:21:33 +0100
Subject: [PATCH 29/70] MIPS: lantiq: convert gpio_stp driver to clkdev api
Update from old pmu_{dis,en}able() to ckldev api.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/gpio_stp.c | 12 +++++++++---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index e6b4809..da91c5e 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -15,6 +15,8 @@
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#include <lantiq_soc.h>
@@ -78,8 +80,10 @@ static struct gpio_chip ltq_stp_chip = {
.owner = THIS_MODULE,
};
-static int ltq_stp_hw_init(void)
+static int ltq_stp_hw_init(struct device *dev)
{
+ struct clk *clk;
+
/* sane defaults */
ltq_stp_w32(0, LTQ_STP_AR);
ltq_stp_w32(0, LTQ_STP_CPU0);
@@ -105,7 +109,9 @@ static int ltq_stp_hw_init(void)
*/
ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
- ltq_pmu_enable(PMU_LED);
+ clk = clk_get(dev, NULL);
+ WARN_ON(IS_ERR(clk));
+ clk_enable(clk);
return 0;
}
@@ -138,7 +144,7 @@ static int __devinit ltq_stp_probe(struct platform_device *pdev)
}
ret = gpiochip_add(&ltq_stp_chip);
if (!ret)
- ret = ltq_stp_hw_init();
+ ret = ltq_stp_hw_init(&pdev->dev);
return ret;
}
--
1.7.7.1

73
target/linux/lantiq/patches-3.2/0030-MIPS-lantiq-convert-falcon-gpio-to-clkdev-api.patch Normal file
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@ -0,0 +1,73 @@
From 3cb13f9992ae1948b6ca05c88d2bd25cf9e7cd41 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 11:22:03 +0100
Subject: [PATCH 30/70] MIPS: lantiq: convert falcon gpio to clkdev api
The falcon gpio clocks used to be enabled when registering the platform device.
Move this code into the driver and use clkdev api.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/falcon/devices.c | 5 -----
arch/mips/lantiq/falcon/gpio.c | 10 ++++++++++
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
index 4f47b44..6cd7a88 100644
--- a/arch/mips/lantiq/falcon/devices.c
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -111,9 +111,6 @@ falcon_register_gpio(void)
falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
platform_device_register_simple("falcon_gpio", 2,
falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
- ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
- ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 |
- ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2);
}
void __init
@@ -123,6 +120,4 @@ falcon_register_gpio_extra(void)
falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
platform_device_register_simple("falcon_gpio", 4,
falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
- ltq_sysctl_activate(SYSCTL_SYS1,
- ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
}
diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
index a44f71b..4147d61 100644
--- a/arch/mips/lantiq/falcon/gpio.c
+++ b/arch/mips/lantiq/falcon/gpio.c
@@ -11,6 +11,7 @@
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/export.h>
+#include <linux/err.h>
#include <linux/platform_device.h>
#include <lantiq_soc.h>
@@ -71,6 +72,7 @@ struct falcon_gpio_port {
void __iomem *port;
unsigned int irq_base;
unsigned int chained_irq;
+ struct clk *clk;
};
static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
@@ -332,6 +334,14 @@ falcon_gpio_probe(struct platform_device *pdev)
goto err;
}
+ gpio_port->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(gpio_port->clk)) {
+ dev_err(&pdev->dev, "Could not get clock\n");
+ ret = PTR_ERR(gpio_port->clk);;
+ goto err;
+ }
+ clk_enable(gpio_port->clk);
+
if (irq > 0) {
/* irq_chip support */
gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
--
1.7.7.1

41
target/linux/lantiq/patches-3.2/0031-SERIAL-MIPS-lantiq-convert-serial-driver-to-clkdev-a.patch Normal file
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@ -0,0 +1,41 @@
From 1fdd8c04b65bd55730e6931a520cc1dabfc4d190 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 Feb 2012 20:17:16 +0100
Subject: [PATCH 31/70] SERIAL: MIPS: lantiq: convert serial driver to clkdev
api
Reference the FPI clock via its new access function.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-serial@vger.kernel.org
---
drivers/tty/serial/lantiq.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 5d25828..1542ad6 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -540,6 +540,10 @@ lqasc_request_port(struct uart_port *port)
if (ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN,
3, 1, "asc1-tx"))
return -EBUSY;
+ ltq_port->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(ltq_port->clk))
+ return PTR_ERR(ltq_port->clk);
+ clk_enable(ltq_port->clk);
}
return 0;
}
@@ -698,7 +702,7 @@ lqasc_probe(struct platform_device *pdev)
if (lqasc_port[pdev->id] != NULL)
return -EBUSY;
- clk = clk_get(&pdev->dev, "fpi");
+ clk = clk_get_fpi();
if (IS_ERR(clk)) {
pr_err("failed to get fpi clk\n");
return -ENOENT;
--
1.7.7.1

73
target/linux/lantiq/patches-3.2/0032-MIPS-lantiq-convert-falcon-debug-uart-to-clkdev-api.patch Normal file
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@ -0,0 +1,73 @@
From 005044f41ed9884ee23d756a5950e38679d31cc7 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 21 Feb 2012 14:25:21 +0100
Subject: [PATCH 32/70] MIPS: lantiq: convert falcon debug uart to clkdev api
On Falcon SoCs we have a secondary serial port that can be used to help
debug the voice core. For the port to work several clocking bits need to
be activated. We convert the code to clkdev api.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/falcon/prom.c | 4 +---
drivers/tty/serial/lantiq.c | 7 ++++---
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
index f98b389..2a4eea1 100644
--- a/arch/mips/lantiq/falcon/prom.c
+++ b/arch/mips/lantiq/falcon/prom.c
@@ -43,10 +43,8 @@ ltq_soc_setup(void)
ltq_register_asc(0);
ltq_register_wdt();
falcon_register_gpio();
- if (register_asc1) {
+ if (register_asc1)
ltq_register_asc(1);
- ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
- }
}
void __init
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 1542ad6..82956de 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -117,6 +117,7 @@ static DEFINE_SPINLOCK(ltq_asc_lock);
struct ltq_uart_port {
struct uart_port port;
+ struct clk *fpiclk;
struct clk *clk;
unsigned int tx_irq;
unsigned int rx_irq;
@@ -319,7 +320,7 @@ lqasc_startup(struct uart_port *port)
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
int retval;
- port->uartclk = clk_get_rate(ltq_port->clk);
+ port->uartclk = clk_get_rate(ltq_port->fpiclk);
ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
port->membase + LTQ_ASC_CLC);
@@ -646,7 +647,7 @@ lqasc_console_setup(struct console *co, char *options)
port = &ltq_port->port;
- port->uartclk = clk_get_rate(ltq_port->clk);
+ port->uartclk = clk_get_rate(ltq_port->fpiclk);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -731,7 +732,7 @@ lqasc_probe(struct platform_device *pdev)
port->irq = tx_irq; /* unused, just to be backward-compatibe */
port->mapbase = mmres->start;
- ltq_port->clk = clk;
+ ltq_port->fpiclk = clk;
ltq_port->tx_irq = tx_irq;
ltq_port->rx_irq = rx_irq;
--
1.7.7.1

123
target/linux/lantiq/patches-3.2/0033-NET-MIPS-lantiq-convert-etop-driver-to-clkdev-api.patch Normal file
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@ -0,0 +1,123 @@
From c96f5cae05788c326f63c8b769e53c6e15215e70 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 11:23:00 +0100
Subject: [PATCH 33/70] NET: MIPS: lantiq: convert etop driver to clkdev api
Update from old pmu_{dis,en}able() to ckldev api.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: netdev@vger.kernel.org
---
drivers/net/ethernet/lantiq_etop.c | 49 ++++++++++++++++++++++++++++++-----
1 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index fcbb9c7..a084d74 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -36,6 +36,7 @@
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
+#include <linux/clk.h>
#include <asm/checksum.h>
@@ -147,6 +148,11 @@ struct ltq_etop_priv {
int tx_free[MAX_DMA_CHAN >> 1];
spinlock_t lock;
+
+ struct clk *clk_ppe;
+ struct clk *clk_switch;
+ struct clk *clk_ephy;
+ struct clk *clk_ephycgu;
};
static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
@@ -280,16 +286,27 @@ ltq_etop_hw_exit(struct net_device *dev)
struct ltq_etop_priv *priv = netdev_priv(dev);
int i;
- ltq_pmu_disable(PMU_PPE);
+ clk_disable(priv->clk_ppe);
+
+ if (ltq_has_gbit())
+ clk_disable(priv->clk_switch);
+
+ if (ltq_is_ase()) {
+ clk_disable(priv->clk_ephy);
+ clk_disable(priv->clk_ephycgu);
+ }
+
for (i = 0; i < MAX_DMA_CHAN; i++)
if (IS_TX(i) || IS_RX(i))
ltq_etop_free_channel(dev, &priv->ch[i]);
}
static void
-ltq_etop_gbit_init(void)
+ltq_etop_gbit_init(struct net_device *dev)
{
- ltq_pmu_enable(PMU_SWITCH);
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+
+ clk_enable(priv->clk_switch);
ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
/** Disable MDIO auto polling mode */
@@ -312,10 +329,10 @@ ltq_etop_hw_init(struct net_device *dev)
int err = 0;
int i;
- ltq_pmu_enable(PMU_PPE);
+ clk_enable(priv->clk_ppe);
if (ltq_has_gbit()) {
- ltq_etop_gbit_init();
+ ltq_etop_gbit_init(dev);
/* force the etops link to the gbit to MII */
mii_mode = PHY_INTERFACE_MODE_MII;
}
@@ -333,11 +350,11 @@ ltq_etop_hw_init(struct net_device *dev)
default:
if (ltq_is_ase()) {
- ltq_pmu_enable(PMU_EPHY);
+ clk_enable(priv->clk_ephy);
/* disable external MII */
ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
/* enable clock for internal PHY */
- ltq_cgu_enable(CGU_EPHY);
+ clk_enable(priv->clk_ephycgu);
/* we need to write this magic to the internal phy to
make it work */
ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
@@ -880,6 +897,24 @@ ltq_etop_probe(struct platform_device *pdev)
priv->res = res;
priv->pldata = dev_get_platdata(&pdev->dev);
priv->netdev = dev;
+
+ priv->clk_ppe = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(priv->clk_ppe))
+ return PTR_ERR(priv->clk_ppe);
+ if (ltq_has_gbit()) {
+ priv->clk_switch = clk_get(&pdev->dev, "switch");
+ if (IS_ERR(priv->clk_switch))
+ return PTR_ERR(priv->clk_switch);
+ }
+ if (ltq_is_ase()) {
+ priv->clk_ephy = clk_get(&pdev->dev, "ephy");
+ if (IS_ERR(priv->clk_ephy))
+ return PTR_ERR(priv->clk_ephy);
+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
+ if (IS_ERR(priv->clk_ephycgu))
+ return PTR_ERR(priv->clk_ephycgu);
+ }
+
spin_lock_init(&priv->lock);
for (i = 0; i < MAX_DMA_CHAN; i++) {
--
1.7.7.1

30
target/linux/lantiq/patches-3.2/0034-WDT-MIPS-lantiq-convert-watchdog-driver-to-clkdev-ap.patch Normal file
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@ -0,0 +1,30 @@
From ac9ded7942720231ed139ac0660e60a3a2f82b86 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 Feb 2012 20:17:50 +0100
Subject: [PATCH 34/70] WDT: MIPS: lantiq: convert watchdog driver to clkdev
api
Refrence the IO region clock via its new access function.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-watchdog@vger.kernel.org
---
drivers/watchdog/lantiq_wdt.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index 179bf98..da2b09f 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev)
}
/* we do not need to enable the clock as it is always running */
- clk = clk_get(&pdev->dev, "io");
+ clk = clk_get_io();
WARN_ON(!clk);
ltq_io_region_clk_rate = clk_get_rate(clk);
clk_put(clk);
--
1.7.7.1

262
target/linux/lantiq/patches-3.2/0035-MIPS-lantiq-unify-xway-prom-code.patch Normal file
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@ -0,0 +1,262 @@
From cab49331fac138102493dea8f1b1d8c28cae6db5 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 11:44:55 +0100
Subject: [PATCH 35/70] MIPS: lantiq: unify xway prom code
The xway prom-ase.c and prom-xway.c files are redundant. Unify the 2 files.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/Makefile | 5 +--
arch/mips/lantiq/xway/Makefile.rej | 11 -----
arch/mips/lantiq/xway/prom-ase.c | 48 ----------------------
arch/mips/lantiq/xway/prom-xway.c | 64 -----------------------------
arch/mips/lantiq/xway/prom.c | 79 ++++++++++++++++++++++++++++++++++++
5 files changed, 80 insertions(+), 127 deletions(-)
delete mode 100644 arch/mips/lantiq/xway/Makefile.rej
delete mode 100644 arch/mips/lantiq/xway/prom-ase.c
delete mode 100644 arch/mips/lantiq/xway/prom-xway.c
create mode 100644 arch/mips/lantiq/xway/prom.c
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 4dcb96f..9d1a0a2 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1,4 @@
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
-
-obj-$(CONFIG_SOC_XWAY) += prom-xway.o
-obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o
obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/Makefile.rej b/arch/mips/lantiq/xway/Makefile.rej
deleted file mode 100644
index c0d5b52..0000000
--- a/arch/mips/lantiq/xway/Makefile.rej
+++ /dev/null
@@ -1,11 +0,0 @@
---- arch/mips/lantiq/xway/Makefile
-+++ arch/mips/lantiq/xway/Makefile
-@@ -1,7 +1,4 @@
--obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
--
--obj-$(CONFIG_SOC_XWAY) += prom-xway.o
--obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o
-+obj-y := prom.o sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o
-
- obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
- obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
deleted file mode 100644
index 3f86a3b..0000000
--- a/arch/mips/lantiq/xway/prom-ase.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/export.h>
-#include <linux/clk.h>
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-
-#include <lantiq_soc.h>
-
-#include "devices.h"
-#include "../prom.h"
-
-#define SOC_AMAZON_SE "Amazon_SE"
-
-#define PART_SHIFT 12
-#define PART_MASK 0x0FFFFFFF
-#define REV_SHIFT 28
-#define REV_MASK 0xF0000000
-
-void __init ltq_soc_detect(struct ltq_soc_info *i)
-{
- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
- sprintf(i->rev_type, "1.%d", i->rev);
- switch (i->partnum) {
- case SOC_ID_AMAZON_SE:
- i->name = SOC_AMAZON_SE;
- i->type = SOC_TYPE_AMAZON_SE;
- break;
-
- default:
- unreachable();
- break;
- }
-}
-
-void __init ltq_soc_setup(void)
-{
- ltq_register_ase_asc();
- ltq_register_gpio();
- ltq_register_wdt();
-}
diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
deleted file mode 100644
index d823a92..0000000
--- a/arch/mips/lantiq/xway/prom-xway.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/export.h>
-#include <linux/clk.h>
-#include <asm/bootinfo.h>
-#include <asm/time.h>
-
-#include <lantiq_soc.h>
-
-#include "devices.h"
-#include "../prom.h"
-
-#define SOC_DANUBE "Danube"
-#define SOC_TWINPASS "Twinpass"
-#define SOC_AR9 "AR9"
-
-#define PART_SHIFT 12
-#define PART_MASK 0x0FFFFFFF
-#define REV_SHIFT 28
-#define REV_MASK 0xF0000000
-
-void __init ltq_soc_detect(struct ltq_soc_info *i)
-{
- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
- sprintf(i->rev_type, "1.%d", i->rev);
- switch (i->partnum) {
- case SOC_ID_DANUBE1:
- case SOC_ID_DANUBE2:
- i->name = SOC_DANUBE;
- i->type = SOC_TYPE_DANUBE;
- break;
-
- case SOC_ID_TWINPASS:
- i->name = SOC_TWINPASS;
- i->type = SOC_TYPE_DANUBE;
- break;
-
- case SOC_ID_ARX188:
- case SOC_ID_ARX168:
- case SOC_ID_ARX182:
- i->name = SOC_AR9;
- i->type = SOC_TYPE_AR9;
- break;
-
- default:
- unreachable();
- break;
- }
-}
-
-void __init ltq_soc_setup(void)
-{
- ltq_register_asc(0);
- ltq_register_asc(1);
- ltq_register_gpio();
- ltq_register_wdt();
-}
diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
new file mode 100644
index 0000000..0929acb
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom.c
@@ -0,0 +1,79 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/export.h>
+#include <linux/clk.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+#include "devices.h"
+
+#define SOC_DANUBE "Danube"
+#define SOC_TWINPASS "Twinpass"
+#define SOC_AR9 "AR9"
+#define SOC_VR9 "VR9"
+
+#define PART_SHIFT 12
+#define PART_MASK 0x0FFFFFFF
+#define REV_SHIFT 28
+#define REV_MASK 0xF0000000
+
+#define SOC_AMAZON_SE "Amazon_SE"
+
+void __init ltq_soc_detect(struct ltq_soc_info *i)
+{
+ i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+ i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
+ sprintf(i->rev_type, "1.%d", i->rev);
+ switch (i->partnum) {
+ case SOC_ID_DANUBE1:
+ case SOC_ID_DANUBE2:
+ i->name = SOC_DANUBE;
+ i->type = SOC_TYPE_DANUBE;
+ break;
+
+ case SOC_ID_TWINPASS:
+ i->name = SOC_TWINPASS;
+ i->type = SOC_TYPE_DANUBE;
+ break;
+
+ case SOC_ID_ARX188:
+ case SOC_ID_ARX168:
+ case SOC_ID_ARX182:
+ i->name = SOC_AR9;
+ i->type = SOC_TYPE_AR9;
+ break;
+
+ case SOC_ID_AMAZON_SE:
+ i->name = SOC_AMAZON_SE;
+ i->type = SOC_TYPE_AMAZON_SE;
+#ifdef CONFIG_PCI
+ panic("ase is only supported for non pci kernels");
+#endif
+ break;
+
+ default:
+ unreachable();
+ break;
+ }
+}
+
+void __init ltq_soc_setup(void)
+{
+ if (ltq_is_ase()) {
+ ltq_register_ase_asc();
+ } else {
+ ltq_register_asc(0);
+ ltq_register_asc(1);
+ }
+ ltq_register_gpio();
+ ltq_register_wdt();
+}
--
1.7.7.1

172
target/linux/lantiq/patches-3.2/0036-MIPS-lantiq-add-vr9-support.patch Normal file
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@ -0,0 +1,172 @@
From 27c4128ab1835a2aff1a0ce6413bb21cfa614d93 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 21 Feb 2012 09:48:11 +0100
Subject: [PATCH 36/70] MIPS: lantiq: add vr9 support
VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9.
This patch adds the clkdev init code and SoC detection for the VR9.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
arch/mips/lantiq/xway/clk.c | 83 ++++++++++++++++++++
arch/mips/lantiq/xway/prom.c | 6 ++
arch/mips/lantiq/xway/sysctrl.c | 12 +++-
4 files changed, 103 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index e9d2dd4..5d11eb7 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -21,6 +21,9 @@
#define SOC_ID_ARX188 0x16C
#define SOC_ID_ARX168 0x16D
#define SOC_ID_ARX182 0x16F
+#define SOC_ID_VRX288 0x1C0 /* VRX288 v1.1 */
+#define SOC_ID_VRX268 0x1C2 /* VRX268 v1.1 */
+#define SOC_ID_GRX288 0x1C9 /* GRX288 v1.1 */
/* SoC Types */
#define SOC_TYPE_DANUBE 0x01
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
index f3b50fc..3635c9f 100644
--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
@@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void)
return ddr_clock >> 1;
return ddr_clock;
}
+
+unsigned long ltq_vr9_cpu_hz(void)
+{
+ unsigned int cpu_sel;
+ unsigned long clk;
+
+ cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
+
+ switch (cpu_sel) {
+ case 0:
+ clk = CLOCK_600M;
+ break;
+ case 1:
+ clk = CLOCK_500M;
+ break;
+ case 2:
+ clk = CLOCK_393M;
+ break;
+ case 3:
+ clk = CLOCK_333M;
+ break;
+ case 5:
+ case 6:
+ clk = CLOCK_196_608M;
+ break;
+ case 7:
+ clk = CLOCK_167M;
+ break;
+ case 4:
+ case 8:
+ case 9:
+ clk = CLOCK_125M;
+ break;
+ default:
+ clk = 0;
+ break;
+ }
+
+ return clk;
+}
+
+unsigned long ltq_vr9_fpi_hz(void)
+{
+ unsigned int ocp_sel, cpu_clk;
+ unsigned long clk;
+
+ cpu_clk = ltq_vr9_cpu_hz();
+ ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
+
+ switch (ocp_sel) {
+ case 0:
+ /* OCP ratio 1 */
+ clk = cpu_clk;
+ break;
+ case 2:
+ /* OCP ratio 2 */
+ clk = cpu_clk / 2;
+ break;
+ case 3:
+ /* OCP ratio 2.5 */
+ clk = (cpu_clk * 2) / 5;
+ break;
+ case 4:
+ /* OCP ratio 3 */
+ clk = cpu_clk / 3;
+ break;
+ default:
+ clk = 0;
+ break;
+ }
+
+ return clk;
+}
+
+unsigned long ltq_vr9_io_region_clock(void)
+{
+ return ltq_vr9_fpi_hz();
+}
+
+unsigned long ltq_vr9_fpi_bus_clock(int fpi)
+{
+ return ltq_vr9_fpi_hz();
+}
diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
index 0929acb..b6f56b7 100644
--- a/arch/mips/lantiq/xway/prom.c
+++ b/arch/mips/lantiq/xway/prom.c
@@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
#endif
break;
+ case SOC_ID_VRX268:
+ case SOC_ID_VRX288:
+ i->name = SOC_VR9;
+ i->type = SOC_TYPE_VR9;
+ break;
+
default:
unreachable();
break;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index c5782b5..38f02f9 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -147,7 +147,8 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
- clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
+ if (!ltq_is_vr9())
+ clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
if (ltq_is_ase()) {
if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
@@ -155,6 +156,15 @@ void __init ltq_soc_init(void)
clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
+ } else if (ltq_is_vr9()) {
+ clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
+ ltq_vr9_io_region_clock());
+ clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
+ clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
+ clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
+ clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
+ clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
+ clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
} else {
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
ltq_danube_io_region_clock());
--
1.7.7.1

124
target/linux/lantiq/patches-3.2/0037-MIPS-lantiq-add-ipi-handlers-to-make-vsmp-work.patch Normal file
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@ -0,0 +1,124 @@
From 58d1ae79d144e6725a68fab99ef6a9b20b25a765 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 21 Feb 2012 21:09:01 +0100
Subject: [PATCH 37/70] MIPS: lantiq: add ipi handlers to make vsmp work
Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work
on lantiq SoCs.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/irq.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++
arch/mips/lantiq/prom.c | 5 ++++
2 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 0b2ed87..770a10c 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -9,6 +9,7 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
+#include <linux/sched.h>
#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>
@@ -54,6 +55,14 @@
#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
+/* our 2 ipi interrupts for VSMP */
+#define MIPS_CPU_IPI_RESCHED_IRQ 0
+#define MIPS_CPU_IPI_CALL_IRQ 1
+
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
+int gic_present;
+#endif
+
static unsigned short ltq_eiu_irq[MAX_EIU] = {
LTQ_EIU_IR0,
LTQ_EIU_IR1,
@@ -219,6 +228,47 @@ static void ltq_hw5_irqdispatch(void)
do_IRQ(MIPS_CPU_TIMER_IRQ);
}
+#ifdef CONFIG_MIPS_MT_SMP
+void __init arch_init_ipiirq(int irq, struct irqaction *action)
+{
+ setup_irq(irq, action);
+ irq_set_handler(irq, handle_percpu_irq);
+}
+
+static void ltq_sw0_irqdispatch(void)
+{
+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
+}
+
+static void ltq_sw1_irqdispatch(void)
+{
+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
+}
+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
+{
+ scheduler_ipi();
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
+{
+ smp_call_function_interrupt();
+ return IRQ_HANDLED;
+}
+
+static struct irqaction irq_resched = {
+ .handler = ipi_resched_interrupt,
+ .flags = IRQF_PERCPU,
+ .name = "IPI_resched"
+};
+
+static struct irqaction irq_call = {
+ .handler = ipi_call_interrupt,
+ .flags = IRQF_PERCPU,
+ .name = "IPI_call"
+};
+#endif
+
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
@@ -314,6 +364,17 @@ void __init arch_init_irq(void)
irq_set_chip_and_handler(i, &ltq_irq_type,
handle_level_irq);
+#if defined(CONFIG_MIPS_MT_SMP)
+ if (cpu_has_vint) {
+ pr_info("Setting up IPI vectored interrupts\n");
+ set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
+ set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
+ }
+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
+ &irq_resched);
+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
+#endif
+
#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 971554b..00ad59c 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -108,4 +108,9 @@ void __init prom_init(void)
soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
pr_info("SoC: %s\n", soc_info.sys_type);
prom_init_cmdline();
+
+#if defined(CONFIG_MIPS_MT_SMP)
+ if (register_vsmp_smp_ops())
+ panic("failed to register_vsmp_smp_ops()");
+#endif
}
--
1.7.7.1

156
target/linux/lantiq/patches-3.2/0038-MIPS-lantiq-add-additional-soc-ids.patch Normal file
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@ -0,0 +1,156 @@
From 655f264da58e9e49d61bf26374f877e2175125e4 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 12 Mar 2012 15:23:39 +0100
Subject: [PATCH 38/70] MIPS: lantiq: add additional soc ids
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 38 +++++++++++++++----
arch/mips/lantiq/xway/prom.c | 35 ++++++++++++++++--
2 files changed, 61 insertions(+), 12 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 5d11eb7..3f22acb 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -17,20 +17,32 @@
#define SOC_ID_DANUBE1 0x129
#define SOC_ID_DANUBE2 0x12B
#define SOC_ID_TWINPASS 0x12D
-#define SOC_ID_AMAZON_SE 0x152
+#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
+#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
#define SOC_ID_ARX188 0x16C
-#define SOC_ID_ARX168 0x16D
+#define SOC_ID_ARX168_1 0x16D
+#define SOC_ID_ARX168_2 0x16E
#define SOC_ID_ARX182 0x16F
-#define SOC_ID_VRX288 0x1C0 /* VRX288 v1.1 */
-#define SOC_ID_VRX268 0x1C2 /* VRX268 v1.1 */
-#define SOC_ID_GRX288 0x1C9 /* GRX288 v1.1 */
+#define SOC_ID_GRX188 0x170
+#define SOC_ID_GRX168 0x171
+
+#define SOC_ID_VRX288 0x1C0 /* v1.1 */
+#define SOC_ID_VRX282 0x1C1 /* v1.1 */
+#define SOC_ID_VRX268 0x1C2 /* v1.1 */
+#define SOC_ID_GRX268 0x1C8 /* v1.1 */
+#define SOC_ID_GRX288 0x1C9 /* v1.1 */
+#define SOC_ID_VRX288_2 0x00B /* v1.2 */
+#define SOC_ID_VRX268_2 0x00C /* v1.2 */
+#define SOC_ID_GRX288_2 0x00D /* v1.2 */
+#define SOC_ID_GRX282_2 0x00E /* v1.2 */
/* SoC Types */
#define SOC_TYPE_DANUBE 0x01
#define SOC_TYPE_TWINPASS 0x02
#define SOC_TYPE_AR9 0x03
-#define SOC_TYPE_VR9 0x04
-#define SOC_TYPE_AMAZON_SE 0x05
+#define SOC_TYPE_VR9_1 0x04 /* v1.1 */
+#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
+#define SOC_TYPE_AMAZON_SE 0x06
/* ASC0/1 - serial port */
#define LTQ_ASC0_BASE_ADDR 0x1E100400
@@ -149,9 +161,19 @@ static inline int ltq_is_ar9(void)
return (ltq_get_soc_type() == SOC_TYPE_AR9);
}
+static inline int ltq_is_vr9_1(void)
+{
+ return (ltq_get_soc_type() == SOC_TYPE_VR9_1);
+}
+
+static inline int ltq_is_vr9_2(void)
+{
+ return (ltq_get_soc_type() == SOC_TYPE_VR9_2);
+}
+
static inline int ltq_is_vr9(void)
{
- return (ltq_get_soc_type() == SOC_TYPE_VR9);
+ return (ltq_is_vr9_1() || ltq_is_vr9_2());
}
static inline int ltq_is_falcon(void)
diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
index b6f56b7..e3dcbbd 100644
--- a/arch/mips/lantiq/xway/prom.c
+++ b/arch/mips/lantiq/xway/prom.c
@@ -18,7 +18,9 @@
#define SOC_DANUBE "Danube"
#define SOC_TWINPASS "Twinpass"
+#define SOC_AMAZON_SE "Amazon_SE"
#define SOC_AR9 "AR9"
+#define SOC_GR9 "GR9"
#define SOC_VR9 "VR9"
#define PART_SHIFT 12
@@ -26,7 +28,6 @@
#define REV_SHIFT 28
#define REV_MASK 0xF0000000
-#define SOC_AMAZON_SE "Amazon_SE"
void __init ltq_soc_detect(struct ltq_soc_info *i)
{
@@ -46,13 +47,21 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
break;
case SOC_ID_ARX188:
- case SOC_ID_ARX168:
+ case SOC_ID_ARX168_1:
+ case SOC_ID_ARX168_2:
case SOC_ID_ARX182:
i->name = SOC_AR9;
i->type = SOC_TYPE_AR9;
break;
- case SOC_ID_AMAZON_SE:
+ case SOC_ID_GRX188:
+ case SOC_ID_GRX168:
+ i->name = SOC_GR9;
+ i->type = SOC_TYPE_AR9;
+ break;
+
+ case SOC_ID_AMAZON_SE_1:
+ case SOC_ID_AMAZON_SE_2:
i->name = SOC_AMAZON_SE;
i->type = SOC_TYPE_AMAZON_SE;
#ifdef CONFIG_PCI
@@ -60,12 +69,30 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
#endif
break;
+ case SOC_ID_VRX282:
case SOC_ID_VRX268:
case SOC_ID_VRX288:
i->name = SOC_VR9;
- i->type = SOC_TYPE_VR9;
+ i->type = SOC_TYPE_VR9_1;
break;
+ case SOC_ID_GRX268:
+ case SOC_ID_GRX288:
+ i->name = SOC_GR9;
+ i->type = SOC_TYPE_VR9_1;
+ break;
+
+ case SOC_ID_VRX268_2:
+ case SOC_ID_VRX288_2:
+ i->name = SOC_VR9;
+ i->type = SOC_TYPE_VR9_2;
+ break;
+
+ case SOC_ID_GRX282_2:
+ case SOC_ID_GRX288_2:
+ i->name = SOC_GR9;
+ i->type = SOC_TYPE_VR9_2;
+
default:
unreachable();
break;
--
1.7.7.1

110
target/linux/lantiq/patches/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch → target/linux/lantiq/patches-3.2/0039-SPI-MIPS-lantiq-add-FALC-ON-spi-driver.patch
View File

@ -1,43 +1,34 @@
From 2bd534c30688bcb3f70f1816fbcff813fc746103 Mon Sep 17 00:00:00 2001
From 0ebdb2202a06d096114aa7676f02d5f426a20366 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 27 Aug 2011 18:12:26 +0200
Subject: [PATCH 13/24] MIPS: lantiq: adds FALC-ON spi driver
Subject: [PATCH 39/70] SPI: MIPS: lantiq: add FALC-ON spi driver
The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is
designed for serial flash access.
designed for serial flash access. This driver has only been tested with m25p80
type chips. The hardware has no support for other types of spi peripherals.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: spi-devel-general@lists.sourceforge.net
---
arch/mips/lantiq/falcon/devices.c | 12 +-
arch/mips/lantiq/falcon/devices.c | 13 +
arch/mips/lantiq/falcon/devices.h | 4 +
arch/mips/lantiq/falcon/mach-easy98000.c | 27 ++
drivers/spi/Kconfig | 4 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-falcon.c | 477 ++++++++++++++++++++++++++++++
6 files changed, 523 insertions(+), 2 deletions(-)
drivers/spi/spi-falcon.c | 483 ++++++++++++++++++++++++++++++
6 files changed, 532 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi-falcon.c
diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
index 6cd7a88..92ec571 100644
--- a/arch/mips/lantiq/falcon/devices.c
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -129,7 +129,7 @@ falcon_register_gpio_extra(void)
/* i2c */
static struct resource falcon_i2c_resources[] = {
- MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
+ MEM_RES("i2c", LTQ_I2C_BASE_ADDR, LTQ_I2C_SIZE),
IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
@@ -140,10 +140,18 @@ void __init falcon_register_i2c(void)
{
platform_device_register_simple("i2c-falcon", 0,
falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
- sys1_hw_activate(ACTS_I2C_ACT);
+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_I2C_ACT);
@@ -121,3 +121,16 @@ falcon_register_gpio_extra(void)
platform_device_register_simple("falcon_gpio", 4,
falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
}
-void __init falcon_register_crypto(void)
+
+/* spi flash */
+static struct platform_device ltq_spi = {
+ .name = "falcon_spi",
@ -46,14 +37,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+void __init
+falcon_register_spi_flash(struct spi_board_info *data)
{
- platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
+{
+ spi_register_board_info(data, 1);
+ platform_device_register(&ltq_spi);
}
+}
diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
index 18be8b6..5e6f720 100644
--- a/arch/mips/lantiq/falcon/devices.h
+++ b/arch/mips/lantiq/falcon/devices.h
@@ -11,11 +11,15 @@
@@ -11,10 +11,14 @@
#ifndef _FALCON_DEVICES_H__
#define _FALCON_DEVICES_H__
@ -65,13 +57,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
extern void falcon_register_nand(void);
extern void falcon_register_gpio(void);
extern void falcon_register_gpio_extra(void);
extern void falcon_register_i2c(void);
+extern void falcon_register_spi_flash(struct spi_board_info *data);
#endif
diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c
index 361b8f0..1a7caad 100644
--- a/arch/mips/lantiq/falcon/mach-easy98000.c
+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
@@ -40,6 +40,21 @@ struct physmap_flash_data easy98000_nor_
@@ -40,6 +40,21 @@ struct physmap_flash_data easy98000_nor_flash_data = {
.parts = easy98000_nor_partitions,
};
@ -119,9 +112,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
"EASY98000NAND",
"EASY98000 Eval Board (NAND Flash)",
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8ba4510..b8424ba 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -189,6 +189,10 @@ config SPI_MPC52xx
@@ -180,6 +180,10 @@ config SPI_MPC52xx
This drivers supports the MPC52xx SPI controller in master SPI
mode.
@ -132,9 +127,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
config SPI_MPC52xx_PSC
tristate "Freescale MPC52xx PSC SPI controller"
depends on PPC_MPC52xx && EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 61c3261..570894c 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmi
@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
@ -142,9 +139,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
new file mode 100644
index 0000000..447bbaa
--- /dev/null
+++ b/drivers/spi/spi-falcon.c
@@ -0,0 +1,477 @@
@@ -0,0 +1,483 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -287,8 +287,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ txp++;
+ bytelen--;
+ if (bytelen) {
+ /* more data:
+ * maybe address and/or dummy */
+ /*
+ * more data:
+ * maybe address and/or dummy
+ */
+ state = state_command_prepare;
+ break;
+ } else {
@ -313,8 +315,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ state = state_end;
+ break;
+ }
+ case state_command_prepare: /* collect tx data for
+ address and dummy phase */
+ /* collect tx data for address and dummy phase */
+ case state_command_prepare:
+ {
+ /* txp is valid, already checked */
+ val = 0;
@ -353,8 +355,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ /* end of sequence? */
+ state = state_disable_cs;
+ } else {
+ /* go to end and expect another
+ * call (read or write) */
+ /*
+ * go to end and expect another
+ * call (read or write)
+ */
+ state = state_end;
+ }
+ break;
@ -452,7 +456,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+falcon_spi_setup(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ const u32 ebuclk = CLOCK_100M;
+ const u32 ebuclk = 100000000;
+ unsigned int i;
+ unsigned long flags;
+
@ -486,8 +490,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ | (i << (SFTIME_SCK_PER_OFFSET + 1)),
+ LTQ_SFTIME);
+
+ /* set some bits of unused_wd, to not trigger HOLD/WP
+ * signals on non QUAD flashes */
+ /*
+ * set some bits of unused_wd, to not trigger HOLD/WP
+ * signals on non QUAD flashes
+ */
+ ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO);
+
+ ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
@ -622,24 +628,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -48,6 +48,10 @@
--
1.7.7.1
#define LTQ_EBU_MODCON 0x000C
+/* I2C */
+#define LTQ_I2C_BASE_ADDR 0x1E200000
+#define LTQ_I2C_SIZE 0x00010000
+
/* GPIO */
#define LTQ_GPIO0_BASE_ADDR 0x1D810000
#define LTQ_GPIO0_SIZE 0x0080
@@ -92,6 +96,7 @@
/* Activation Status Register */
#define ACTS_ASC1_ACT 0x00000800
+#define ACTS_I2C_ACT 0x00004000
#define ACTS_P0 0x00010000
#define ACTS_P1 0x00010000
#define ACTS_P2 0x00020000

489
target/linux/lantiq/patches/0011-MIPS-lantiq-adds-falcon-I2C.patch → target/linux/lantiq/patches-3.2/0040-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
View File

@ -1,78 +1,185 @@
From 6437f41dfdf9475178e22ab0dd886af033f90cc2 Mon Sep 17 00:00:00 2001
From 97050437c6a3ce59ce2c5a8286b9bc1c9f1b3b60 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 29 Sep 2011 21:10:16 +0200
Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
Date: Fri, 4 Nov 2011 16:00:34 +0100
Subject: [PATCH 40/70] I2C: MIPS: lantiq: add FALC-ON i2c bus master
This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-i2c@vger.kernel.org
---
arch/mips/lantiq/falcon/devices.c | 21 +
.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 5 +
arch/mips/lantiq/falcon/clk.c | 44 -
arch/mips/lantiq/falcon/devices.c | 16 +
arch/mips/lantiq/falcon/devices.h | 1 +
drivers/i2c/busses/Kconfig | 4 +
arch/mips/lantiq/falcon/mach-easy98000.c | 1 +
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-falcon.c | 815 +++++++++++++++++++++++++++++++++++++
5 files changed, 842 insertions(+), 0 deletions(-)
drivers/i2c/busses/i2c-falcon.c | 1040 ++++++++++++++++++++
8 files changed, 1074 insertions(+), 44 deletions(-)
delete mode 100644 arch/mips/lantiq/falcon/clk.c
create mode 100644 drivers/i2c/busses/i2c-falcon.c
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index 120c56c..fff5ecd 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -72,6 +72,10 @@
#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600
#define LTQ_PADCTRL4_SIZE 0x0100
+/* I2C */
+#define GPON_I2C_BASE 0x1E200000
+#define GPON_I2C_SIZE 0x00010000
+
/* CHIP ID */
#define LTQ_STATUS_BASE_ADDR 0x1E802000
@@ -106,6 +110,7 @@
#define ACTS_PADCTRL2 0x00200000
#define ACTS_PADCTRL3 0x00200000
#define ACTS_PADCTRL4 0x00400000
+#define ACTS_I2C_ACT 0x00004000
/* global register ranges */
extern __iomem void *ltq_ebu_membase;
diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
deleted file mode 100644
index afe1b52..0000000
--- a/arch/mips/lantiq/falcon/clk.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/ioport.h>
-#include <linux/export.h>
-
-#include <lantiq_soc.h>
-
-#include "devices.h"
-
-/* CPU0 Clock Control Register */
-#define LTQ_SYS1_CPU0CC 0x0040
-/* clock divider bit */
-#define LTQ_CPU0CC_CPUDIV 0x0001
-
-unsigned int
-ltq_get_io_region_clock(void)
-{
- return CLOCK_200M;
-}
-EXPORT_SYMBOL(ltq_get_io_region_clock);
-
-unsigned int
-ltq_get_cpu_hz(void)
-{
- if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
- return CLOCK_200M;
- else
- return CLOCK_400M;
-}
-EXPORT_SYMBOL(ltq_get_cpu_hz);
-
-unsigned int
-ltq_get_fpi_hz(void)
-{
- return CLOCK_100M;
-}
-EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
index 92ec571..e684ed4 100644
--- a/arch/mips/lantiq/falcon/devices.c
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -126,3 +126,24 @@ falcon_register_gpio_extra(void)
ltq_sysctl_activate(SYSCTL_SYS1,
ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
@@ -134,3 +134,19 @@ falcon_register_spi_flash(struct spi_board_info *data)
spi_register_board_info(data, 1);
platform_device_register(&ltq_spi);
}
+
+/* i2c */
+static struct resource falcon_i2c_resources[] = {
+ MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
+ IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
+ IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
+ IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
+ IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P),
+ MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE),
+ IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ),
+ IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ),
+ IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR),
+ IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P),
+};
+
+void __init falcon_register_i2c(void)
+void __init
+falcon_register_i2c(void)
+{
+ platform_device_register_simple("i2c-falcon", 0,
+ falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
+ sys1_hw_activate(ACTS_I2C_ACT);
+}
+
+void __init falcon_register_crypto(void)
+{
+ platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
+}
diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
index 5e6f720..d81edbe 100644
--- a/arch/mips/lantiq/falcon/devices.h
+++ b/arch/mips/lantiq/falcon/devices.h
@@ -16,5 +16,6 @@
extern void falcon_register_nand(void);
@@ -20,5 +20,6 @@ extern void falcon_register_nand(void);
extern void falcon_register_gpio(void);
extern void falcon_register_gpio_extra(void);
extern void falcon_register_spi_flash(struct spi_board_info *data);
+extern void falcon_register_i2c(void);
#endif
diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c
index 1a7caad..fc5720d 100644
--- a/arch/mips/lantiq/falcon/mach-easy98000.c
+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
@@ -98,6 +98,7 @@ easy98000_init_common(void)
{
spi_register_board_info(&easy98000_spi_gpio_devices, 1);
platform_device_register(&easy98000_spi_gpio_device);
+ falcon_register_i2c();
}
static void __init
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a3afac4..41be6cc 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -284,6 +284,10 @@ config I2C_POWERMAC
comment "I2C system bus drivers (mostly embedded / system-on-chip)"
@@ -369,6 +369,16 @@ config I2C_DESIGNWARE_PCI
This driver can also be built as a module. If so, the module
will be called i2c-designware-pci.
+config I2C_FALCON
+ tristate "Falcon I2C interface"
+# depends on SOC_FALCON
+ depends on SOC_FALCON
+ help
+ If you say yes to this option, support will be included for the
+ Lantiq FALC-ON I2C core.
+
config I2C_AT91
tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
+ This driver can also be built as a module. If so, the module
+ will be called i2c-falcon.
+
config I2C_GPIO
tristate "GPIO-based bitbanging I2C"
depends on GENERIC_GPIO
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index fba6da6..36239c8 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
obj-$(CONFIG_I2C_STUB) += i2c-stub.o
obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
@@ -37,6 +37,7 @@ obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o
obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
i2c-designware-pci-objs := i2c-designware-pcidrv.o i2c-designware-core.o
+obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o
ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
diff --git a/drivers/i2c/busses/i2c-falcon.c b/drivers/i2c/busses/i2c-falcon.c
new file mode 100644
index 0000000..fc4f0eb
--- /dev/null
+++ b/drivers/i2c/busses/i2c-falcon.c
@@ -0,0 +1,815 @@
@@ -0,0 +1,1040 @@
+/*
+ * Lantiq FALC(tm) ON - I2C bus adapter
+ *
@ -91,14 +198,21 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
+ */
+
+/* #define DEBUG */
+/*
+ * CURRENT ISSUES:
+ * - no high speed support
+ * - supports only master mode
+ * - ten bit mode is not tested (no slave devices)
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/slab.h> /* for kzalloc, kfree */
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/clk.h>
+#include <linux/errno.h>
@ -107,25 +221,242 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+
+#include <falcon/lantiq_soc.h>
+#include <lantiq_soc.h>
+
+/* CURRENT ISSUES:
+ * - no high speed support
+ * - supports only master mode
+ * - ten bit mode is not tested (no slave devices)
+/* I2C Identification Register */
+/* Module ID */
+#define I2C_ID_ID_MASK 0x0000FF00
+/* field offset */
+#define I2C_ID_ID_OFFSET 8
+/* Revision */
+#define I2C_ID_REV_MASK 0x000000FF
+/* field offset */
+#define I2C_ID_REV_OFFSET 0
+
+/* I2C Error Interrupt Request Source Status Register */
+/* TXF_OFL */
+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
+/* TXF_UFL */
+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
+/* RXF_OFL */
+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
+/* RXF_UFL */
+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
+
+/* I2C Bus Status Register */
+/* Bus Status */
+#define I2C_BUS_STAT_BS_MASK 0x00000003
+/* I2C Bus is free. */
+#define I2C_BUS_STAT_BS_FREE 0x00000000
+/*
+ * The device is working as master and has claimed the control
+ * on the I2C-bus (busy master).
+ */
+#define I2C_BUS_STAT_BS_BM 0x00000002
+
+/* I2C Interrupt Clear Register */
+/* Clear */
+#define I2C_ICR_BREQ_INT_CLR 0x00000008
+/* Clear */
+#define I2C_ICR_LBREQ_INT_CLR 0x00000004
+
+/* I2C RUN Control Register */
+/* Enable */
+#define I2C_RUN_CTRL_RUN_EN 0x00000001
+
+/* I2C Kernel Clock Control Register */
+/* field offset */
+#define I2C_CLC_RMC_OFFSET 8
+/* Enable */
+#define I2C_IMSC_I2C_P_INT_EN 0x00000020
+/* Enable */
+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
+/* Enable */
+#define I2C_IMSC_BREQ_INT_EN 0x00000008
+/* Enable */
+#define I2C_IMSC_LBREQ_INT_EN 0x00000004
+
+/* I2C Fractional Divider Configuration Register */
+/* field offset */
+#define I2C_FDIV_CFG_INC_OFFSET 16
+/* field offset */
+#define I2C_FDIV_CFG_DEC_OFFSET 0
+
+/* I2C Fractional Divider (highspeed mode) Configuration Register */
+/* field offset */
+#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
+/* field offset */
+#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
+
+/* I2C Address Register */
+/* Enable */
+#define I2C_ADDR_CFG_SOPE_EN 0x00200000
+/* Enable */
+#define I2C_ADDR_CFG_SONA_EN 0x00100000
+/* Enable */
+#define I2C_ADDR_CFG_MnS_EN 0x00080000
+
+/* I2C Protocol Interrupt Request Source Status Register */
+/* RX */
+#define I2C_P_IRQSS_RX 0x00000040
+/* TX_END */
+#define I2C_P_IRQSS_TX_END 0x00000020
+/* NACK */
+#define I2C_P_IRQSS_NACK 0x00000010
+/* AL */
+#define I2C_P_IRQSS_AL 0x00000008
+
+/* I2C Raw Interrupt Status Register */
+/* Read: Interrupt occurred. */
+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
+/* Read: Interrupt occurred. */
+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
+
+/* I2C End Data Control Register */
+/*
+ * Set End of Transmission - Note: Do not write '1' to this bit when bus is
+ * free. This will cause an abort after the first byte when a new transfer
+ * is started.
+ */
+#define I2C_ENDD_CTRL_SETEND 0x00000002
+/* TX FIFO Flow Control */
+#define I2C_FIFO_CFG_TXFC 0x00020000
+/* RX FIFO Flow Control */
+#define I2C_FIFO_CFG_RXFC 0x00010000
+/* Word aligned (character alignment of four characters) */
+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
+/* Word aligned (character alignment of four characters) */
+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
+/* 1 word */
+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
+/* 1 word */
+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
+
+
+/* I2C register structure */
+struct gpon_reg_i2c {
+ /* I2C Kernel Clock Control Register */
+ unsigned int clc; /* 0x00000000 */
+ /* Reserved */
+ unsigned int res_0; /* 0x00000004 */
+ /* I2C Identification Register */
+ unsigned int id; /* 0x00000008 */
+ /* Reserved */
+ unsigned int res_1; /* 0x0000000C */
+ /*
+ * I2C RUN Control Register - This register enables and disables the I2C
+ * peripheral. Before enabling, the I2C has to be configured properly.
+ * After enabling no configuration is possible
+ */
+ unsigned int run_ctrl; /* 0x00000010 */
+ /*
+ * I2C End Data Control Register - This register is used to either turn
+ * around the data transmission direction or to address another slave
+ * without sending a stop condition. Also the software can stop the
+ * slave-transmitter by sending a not-accolade when working as
+ * master-receiver or even stop data transmission immediately when
+ * operating as master-transmitter. The writing to the bits of this
+ * control register is only effective when in MASTER RECEIVES BYTES,
+ * MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
+ */
+ unsigned int endd_ctrl; /* 0x00000014 */
+ /*
+ * I2C Fractional Divider Configuration Register - These register is
+ * used to program the fractional divider of the I2C bus. Before the
+ * peripheral is switched on by setting the RUN-bit the two (fixed)
+ * values for the two operating frequencies are programmed into these
+ * (configuration) registers. The Register FDIV_HIGH_CFG has the same
+ * layout as I2C_FDIV_CFG.
+ */
+ unsigned int fdiv_cfg; /* 0x00000018 */
+ /*
+ * I2C Fractional Divider (highspeed mode) Configuration Register
+ * These register is used to program the fractional divider of the I2C
+ * bus. Before the peripheral is switched on by setting the RUN-bit the
+ * two (fixed) values for the two operating frequencies are programmed
+ * into these (configuration) registers. The Register FDIV_CFG has the
+ * same layout as I2C_FDIV_CFG.
+ */
+ unsigned int fdiv_high_cfg; /* 0x0000001C */
+ /* I2C Address Configuration Register */
+ unsigned int addr_cfg; /* 0x00000020 */
+ /*
+ * I2C Bus Status Register - This register gives a status information
+ * of the I2C. This additional information can be used by the software
+ * to start proper actions.
+ */
+ unsigned int bus_stat; /* 0x00000024 */
+ /* I2C FIFO Configuration Register */
+ unsigned int fifo_cfg; /* 0x00000028 */
+ /* I2C Maximum Received Packet Size Register */
+ unsigned int mrps_ctrl; /* 0x0000002C */
+ /* I2C Received Packet Size Status Register */
+ unsigned int rps_stat; /* 0x00000030 */
+ /* I2C Transmit Packet Size Register */
+ unsigned int tps_ctrl; /* 0x00000034 */
+ /* I2C Filled FIFO Stages Status Register */
+ unsigned int ffs_stat; /* 0x00000038 */
+ /* Reserved */
+ unsigned int res_2; /* 0x0000003C */
+ /* I2C Timing Configuration Register */
+ unsigned int tim_cfg; /* 0x00000040 */
+ /* Reserved */
+ unsigned int res_3[7]; /* 0x00000044 */
+ /* I2C Error Interrupt Request Source Mask Register */
+ unsigned int err_irqsm; /* 0x00000060 */
+ /* I2C Error Interrupt Request Source Status Register */
+ unsigned int err_irqss; /* 0x00000064 */
+ /* I2C Error Interrupt Request Source Clear Register */
+ unsigned int err_irqsc; /* 0x00000068 */
+ /* Reserved */
+ unsigned int res_4; /* 0x0000006C */
+ /* I2C Protocol Interrupt Request Source Mask Register */
+ unsigned int p_irqsm; /* 0x00000070 */
+ /* I2C Protocol Interrupt Request Source Status Register */
+ unsigned int p_irqss; /* 0x00000074 */
+ /* I2C Protocol Interrupt Request Source Clear Register */
+ unsigned int p_irqsc; /* 0x00000078 */
+ /* Reserved */
+ unsigned int res_5; /* 0x0000007C */
+ /* I2C Raw Interrupt Status Register */
+ unsigned int ris; /* 0x00000080 */
+ /* I2C Interrupt Mask Control Register */
+ unsigned int imsc; /* 0x00000084 */
+ /* I2C Masked Interrupt Status Register */
+ unsigned int mis; /* 0x00000088 */
+ /* I2C Interrupt Clear Register */
+ unsigned int icr; /* 0x0000008C */
+ /* I2C Interrupt Set Register */
+ unsigned int isr; /* 0x00000090 */
+ /* I2C DMA Enable Register */
+ unsigned int dmae; /* 0x00000094 */
+ /* Reserved */
+ unsigned int res_6[8154]; /* 0x00000098 */
+ /* I2C Transmit Data Register */
+ unsigned int txd; /* 0x00008000 */
+ /* Reserved */
+ unsigned int res_7[4095]; /* 0x00008004 */
+ /* I2C Receive Data Register */
+ unsigned int rxd; /* 0x0000C000 */
+ /* Reserved */
+ unsigned int res_8[4095]; /* 0x0000C004 */
+};
+
+/* mapping for access macros */
+#define i2c ((struct gpon_reg_i2c *)priv->membase)
+#define reg_r32(reg) __raw_readl(reg)
+#define reg_w32(val, reg) __raw_writel(val, reg)
+#define reg_w32_mask(clear, set, reg) \
+ reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
+#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
+#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
+#define i2c (priv->membase)
+#include <falcon/i2c_reg.h>
+
+#define i2c_r32(reg) reg_r32(&i2c->reg)
+#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
+#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
+
+#define DRV_NAME "i2c-falcon"
+#define DRV_VERSION "1.01"
@ -133,12 +464,12 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */
+
+#ifdef DEBUG
+#define FALCON_I2C_XFER_TIMEOUT 25*HZ
+#define FALCON_I2C_XFER_TIMEOUT (25 * HZ)
+#else
+#define FALCON_I2C_XFER_TIMEOUT HZ
+#endif
+#if defined(DEBUG) && 0
+#define PRINTK(arg...) printk(arg)
+#define PRINTK(arg...) pr_info(arg)
+#else
+#define PRINTK(arg...) do {} while (0)
+#endif
@ -209,7 +540,7 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+static void prepare_msg_send_addr(struct falcon_i2c *priv)
+{
+ struct i2c_msg *msg = priv->current_msg;
+ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */
+ int rd = !!(msg->flags & I2C_M_RD);
+ u16 addr = msg->addr;
+
+ /* new i2c_msg */
@ -233,7 +564,7 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ struct i2c_msg *msg = priv->current_msg;
+ int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
+
+ PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD)?'R':'T');
+ PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? ('R') : ('T'));
+
+ priv->status = STATUS_ADDR;
+
@ -297,8 +628,8 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ fifo_cfg);
+
+ /* configure address */
+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in the
+ fifo */
+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data
+ in the fifo */
+ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */
+ I2C_ADDR_CFG_MnS_EN | /* we are master device */
+ 0, /* our slave address (not used!) */
@ -339,10 +670,9 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ } else
+ last = 1;
+
+ if (last) {
+ if (last)
+ disable_burst_irq(priv);
+}
+}
+
+static void falcon_i2c_rx(struct falcon_i2c *priv, int last)
+{
@ -406,10 +736,10 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+{
+#if defined(DEBUG)
+ int i, j;
+ printk("Messages %d %s\n", num, rx ? "out" : "in");
+ pr_info("Messages %d %s\n", num, rx ? "out" : "in");
+ for (i = 0; i < num; i++) {
+ printk("%2d %cX Msg(%d) addr=0x%X: ", i,
+ (msgs[i].flags & I2C_M_RD)?'R':'T',
+ pr_info("%2d %cX Msg(%d) addr=0x%X: ", i,
+ (msgs[i].flags & I2C_M_RD) ? ('R') : ('T'),
+ msgs[i].len, msgs[i].addr);
+ if (!(msgs[i].flags & I2C_M_RD) || rx) {
+ for (j = 0; j < msgs[i].len; j++)
@ -470,10 +800,9 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ ret = -EREMOTEIO;
+ goto done;
+ }
+ if (--priv->msgs_num) {
+ if (--priv->msgs_num)
+ priv->current_msg++;
+ }
+ }
+ /* no error? */
+ ret = num;
+
@ -514,7 +843,7 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ break;
+ default:
+ disable_burst_irq(priv);
+ printk("Status R %d\n", priv->status);
+ PRINTK("Status R %d\n", priv->status);
+ break;
+ }
+ } else {
@ -529,7 +858,7 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ break;
+ default:
+ disable_burst_irq(priv);
+ printk("Status W %d\n", priv->status);
+ PRINTK("Status W %d\n", priv->status);
+ break;
+ }
+ }
@ -662,7 +991,7 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ return -ENODEV;
+ }
+
+ clk = clk_get(&pdev->dev, "fpi");
+ clk = clk_get_fpi();
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed to get fpi clk\n");
+ return -ENOENT;
@ -672,6 +1001,11 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ dev_err(&pdev->dev, "input clock is not 100MHz\n");
+ return -ENOENT;
+ }
+ clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "failed to get i2c clk\n");
+ return -ENOENT;
+ }
+
+ /* allocate private data */
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
@ -694,16 +1028,10 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ init_completion(&priv->cmd_complete);
+ mutex_init(&priv->mutex);
+
+ ret = ltq_gpio_request(107, 0, 0, 0, DRV_NAME":sda");
+ if (ret) {
+ dev_err(&pdev->dev, "I2C gpio 107 (sda) not available\n");
+ ret = -ENXIO;
+ goto err_free_priv;
+ }
+ ret = ltq_gpio_request(108, 0, 0, 0, DRV_NAME":scl");
+ if (ret) {
+ gpio_free(107);
+ dev_err(&pdev->dev, "I2C gpio 108 (scl) not available\n");
+ if (ltq_gpio_request(&pdev->dev, 107, 0, 0, DRV_NAME":sda") ||
+ ltq_gpio_request(&pdev->dev, 108, 0, 0, DRV_NAME":scl"))
+ {
+ dev_err(&pdev->dev, "I2C gpios not available\n");
+ ret = -ENXIO;
+ goto err_free_priv;
+ }
@ -729,7 +1057,8 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED,
+ irqres_lb->name, priv);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start);
+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
+ irqres_lb->start);
+ ret = -ENODEV;
+ goto err_unmap_mem;
+ }
@ -738,7 +1067,8 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED,
+ irqres_b->name, priv);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start);
+ dev_err(&pdev->dev, "can't get burst IRQ %d\n",
+ irqres_b->start);
+ ret = -ENODEV;
+ goto err_free_lb_irq;
+ }
@ -747,7 +1077,8 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
+ irqres_err->name, priv);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start);
+ dev_err(&pdev->dev, "can't get error IRQ %d\n",
+ irqres_err->start);
+ ret = -ENODEV;
+ goto err_free_b_irq;
+ }
@ -756,7 +1087,8 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+ ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
+ irqres_p->name, priv);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start);
+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
+ irqres_p->start);
+ ret = -ENODEV;
+ goto err_free_err_irq;
+ }
@ -888,3 +1220,6 @@ Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+MODULE_ALIAS("platform:" DRV_NAME);
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
--
1.7.7.1

310
target/linux/lantiq/patches-3.2/0041-MIPS-lantiq-add-xway-nand-driver.patch Normal file
View File

@ -0,0 +1,310 @@
From 9c7a6f8804aef7559ee8edcb7466676ee7d00c09 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 27 Aug 2011 20:08:14 +0200
Subject: [PATCH 41/70] MIPS: lantiq: add xway nand driver
This patch adds a nand driver for XWAY SoCs. The patch makes use of the
plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
endianess swap problem on read. To workaround this problem we make the
read_byte() callback available via the plat_nand driver causing the nand
layer to do byte reads.
Signed-off-by: John Crispin <blogic@openwrt.org>
TODO : memory ranges
cs lines
plat dev
ebu2 and not ebu1 ?
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
arch/mips/lantiq/xway/Makefile | 2 +-
arch/mips/lantiq/xway/devices.h | 1 +
arch/mips/lantiq/xway/nand.c | 216 ++++++++++++++++++++
drivers/mtd/nand/plat_nand.c | 1 +
include/linux/mtd/nand.h | 1 +
6 files changed, 222 insertions(+), 1 deletions(-)
create mode 100644 arch/mips/lantiq/xway/nand.c
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 3f22acb..ab2d236 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -145,6 +145,8 @@
/* register access macros for EBU and CGU */
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
+#define ltq_ebu_w32_mask(x, y, z) \
+ ltq_w32_mask(x, y, ltq_ebu_membase + (z))
#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 9d1a0a2..277aa34 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,4 +1,4 @@
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o
+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o
obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h
index e904934..d825cbd 100644
--- a/arch/mips/lantiq/xway/devices.h
+++ b/arch/mips/lantiq/xway/devices.h
@@ -16,5 +16,6 @@ extern void ltq_register_gpio(void);
extern void ltq_register_gpio_stp(void);
extern void ltq_register_ase_asc(void);
extern void ltq_register_etop(struct ltq_eth_data *eth);
+extern void xway_register_nand(struct mtd_partition *parts, int count);
#endif
diff --git a/arch/mips/lantiq/xway/nand.c b/arch/mips/lantiq/xway/nand.c
new file mode 100644
index 0000000..9ab91d8
--- /dev/null
+++ b/arch/mips/lantiq/xway/nand.c
@@ -0,0 +1,216 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <lantiq_soc.h>
+#include <lantiq_irq.h>
+#include <lantiq_platform.h>
+
+#include "devices.h"
+
+/* nand registers */
+#define LTQ_EBU_NAND_WAIT 0xB4
+#define LTQ_EBU_NAND_ECC0 0xB8
+#define LTQ_EBU_NAND_ECC_AC 0xBC
+#define LTQ_EBU_NAND_CON 0xB0
+#define LTQ_EBU_ADDSEL1 0x24
+
+/* gpio definitions */
+#define PIN_ALE 13
+#define PIN_CLE 24
+#define PIN_CS1 23
+#define PIN_RDY 48 /* NFLASH_READY */
+#define PIN_RD 49 /* NFLASH_READ_N */
+
+#define NAND_CMD_ALE (1 << 2)
+#define NAND_CMD_CLE (1 << 3)
+#define NAND_CMD_CS (1 << 4)
+#define NAND_WRITE_CMD_RESET 0xff
+#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
+#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
+#define NAND_WRITE_DATA (NAND_CMD_CS)
+#define NAND_READ_DATA (NAND_CMD_CS)
+#define NAND_WAIT_WR_C (1 << 3)
+#define NAND_WAIT_RD (0x1)
+
+#define ADDSEL1_MASK(x) (x << 4)
+#define ADDSEL1_REGEN 1
+#define BUSCON1_SETUP (1 << 22)
+#define BUSCON1_BCGEN_RES (0x3 << 12)
+#define BUSCON1_WAITWRC2 (2 << 8)
+#define BUSCON1_WAITRDC2 (2 << 6)
+#define BUSCON1_HOLDC1 (1 << 4)
+#define BUSCON1_RECOVC1 (1 << 2)
+#define BUSCON1_CMULT4 1
+#define NAND_CON_NANDM 1
+#define NAND_CON_CSMUX (1 << 1)
+#define NAND_CON_CS_P (1 << 4)
+#define NAND_CON_SE_P (1 << 5)
+#define NAND_CON_WP_P (1 << 6)
+#define NAND_CON_PRE_P (1 << 7)
+#define NAND_CON_IN_CS0 0
+#define NAND_CON_OUT_CS0 0
+#define NAND_CON_IN_CS1 (1 << 8)
+#define NAND_CON_OUT_CS1 (1 << 10)
+#define NAND_CON_CE (1 << 20)
+
+#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000)
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+static void xway_select_chip(struct mtd_info *mtd, int chip)
+{
+ switch (chip) {
+ case -1:
+ ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
+ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
+ break;
+ case 0:
+ ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
+ ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
+ /* reset the nand chip */
+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ ;
+ ltq_w32(NAND_WRITE_CMD_RESET,
+ ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
+ break;
+ default:
+ BUG();
+ }
+}
+
+static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_CLE)
+ this->IO_ADDR_W = (void __iomem *)
+ (NAND_BASE_ADDRESS | NAND_WRITE_CMD);
+ else if (ctrl & NAND_ALE)
+ this->IO_ADDR_W = (void __iomem *)
+ (NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
+ }
+
+ if (data != NAND_CMD_NONE) {
+ *(volatile u8*) ((u32) this->IO_ADDR_W) = data;
+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ ;
+ }
+}
+
+static int xway_dev_ready(struct mtd_info *mtd)
+{
+ return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
+}
+
+void nand_write(unsigned int addr, unsigned int val)
+{
+ ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr)));
+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ ;
+}
+
+unsigned char xway_read_byte(struct mtd_info *mtd)
+{
+ return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
+}
+
+static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ {
+ unsigned char res8 = ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
+ buf[i] = res8;
+ }
+}
+
+static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ {
+ ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA))));
+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
+ }
+}
+
+int xway_probe(struct platform_device *pdev)
+{
+ /* might need this later ?
+ ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1");
+ */
+ ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE");
+ ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE");
+ if (ltq_is_ar9() || ltq_is_vr9()) {
+ ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY");
+ ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD");
+ }
+
+ ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
+ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
+
+ ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
+ | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
+ | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
+
+ ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
+ | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
+ | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
+
+ ltq_w32(NAND_WRITE_CMD_RESET,
+ ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ ;
+
+ return 0;
+}
+
+static struct platform_nand_data falcon_flash_nand_data = {
+ .chip = {
+ .nr_chips = 1,
+ .chip_delay = 30,
+ .part_probe_types = part_probes,
+ },
+ .ctrl = {
+ .probe = xway_probe,
+ .cmd_ctrl = xway_cmd_ctrl,
+ .dev_ready = xway_dev_ready,
+ .select_chip = xway_select_chip,
+ .read_byte = xway_read_byte,
+ .read_buf = xway_read_buf,
+ .write_buf = xway_write_buf,
+ }
+};
+
+static struct resource ltq_nand_res =
+ MEM_RES("nand", 0x14000000, 0x7ffffff);
+
+static struct platform_device ltq_flash_nand = {
+ .name = "gen_nand",
+ .id = -1,
+ .num_resources = 1,
+ .resource = &ltq_nand_res,
+ .dev = {
+ .platform_data = &falcon_flash_nand_data,
+ },
+};
+
+void __init xway_register_nand(struct mtd_partition *parts, int count)
+{
+ falcon_flash_nand_data.chip.partitions = parts;
+ falcon_flash_nand_data.chip.nr_partitions = count;
+ platform_device_register(&ltq_flash_nand);
+}
diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
index ea8e123..9040ba1 100644
--- a/drivers/mtd/nand/plat_nand.c
+++ b/drivers/mtd/nand/plat_nand.c
@@ -75,6 +75,7 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
data->chip.select_chip = pdata->ctrl.select_chip;
data->chip.write_buf = pdata->ctrl.write_buf;
data->chip.read_buf = pdata->ctrl.read_buf;
+ data->chip.read_byte = pdata->ctrl.read_byte;
data->chip.chip_delay = pdata->chip.chip_delay;
data->chip.options |= pdata->chip.options;
data->chip.bbt_options |= pdata->chip.bbt_options;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 904131b..80e11b9 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -650,6 +650,7 @@ struct platform_nand_ctrl {
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
+ unsigned char (*read_byte)(struct mtd_info *mtd);
void *priv;
};
--
1.7.7.1

97
target/linux/lantiq/patches/0014-MIPS-lantiq-adds-xway-spi.patch → target/linux/lantiq/patches-3.2/0042-SPI-MIPS-lantiq-adds-spi-xway.patch
View File

@ -1,18 +1,19 @@
From e29263339db41d49d79482c93463c4c0cbe764d7 Mon Sep 17 00:00:00 2001
From b257baf20b44e97770a2654a07f196fcbcd46e92 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 30 Sep 2011 14:23:42 +0200
Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
Date: Mon, 10 Oct 2011 22:29:13 +0200
Subject: [PATCH 42/70] SPI: MIPS: lantiq: adds spi xway
---
.../mips/include/asm/mach-lantiq/lantiq_platform.h | 9 +
.../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 +
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 +
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 2 +-
drivers/spi/spi-xway.c | 1062 ++++++++++++++++++++
6 files changed, 1083 insertions(+), 1 deletions(-)
drivers/spi/Makefile | 1 +
drivers/spi/spi-xway.c | 1068 ++++++++++++++++++++
5 files changed, 1088 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi-xway.c
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
index a305f1d..38ed938 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -50,4 +50,13 @@ struct ltq_eth_data {
@ -29,6 +30,8 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+};
+
#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index 2a8d5ad..b7f10e6 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -27,6 +27,8 @@
@ -40,19 +43,11 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -81,6 +81,7 @@
#define PMU_DMA 0x0020
#define PMU_USB 0x8041
+#define PMU_SPI 0x0100
#define PMU_LED 0x0800
#define PMU_GPT 0x1000
#define PMU_PPE 0x2000
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b8424ba..ca4189c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -393,6 +393,14 @@ config SPI_NUC900
@@ -384,6 +384,14 @@ config SPI_NUC900
help
SPI driver for Nuvoton NUC900 series ARM SoCs
@ -67,17 +62,22 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
#
# Add new SPI master controllers in alphabetical order above this line
#
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 570894c..a465d9a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,4 +60,5 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x
@@ -59,4 +59,5 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
+obj-$(CONFIG_SPI_XWAY) += spi-xway.o
diff --git a/drivers/spi/spi-xway.c b/drivers/spi/spi-xway.c
new file mode 100644
index 0000000..016a6d0
--- /dev/null
+++ b/drivers/spi/spi-xway.c
@@ -0,0 +1,1062 @@
@@ -0,0 +1,1068 @@
+/*
+ * Lantiq SoC SPI controller
+ *
@ -234,7 +234,8 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk;
+ struct clk *fpiclk;
+ struct clk *spiclk;
+
+ int status;
+ int irq[3];
@ -267,8 +268,7 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+
+struct ltq_spi_cs_gpio_map {
+ unsigned gpio;
+ unsigned altsel0;
+ unsigned altsel1;
+ unsigned mux;
+};
+
+static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
@ -309,7 +309,7 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ u32 clc;
+
+ /* Power-up mdule */
+ ltq_pmu_enable(PMU_SPI);
+ clk_enable(hw->spiclk);
+
+ /*
+ * Set clock divider for run mode to 1 to
@ -325,7 +325,7 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
+
+ /* Power-down mdule */
+ ltq_pmu_disable(PMU_SPI);
+ clk_disable(hw->spiclk);
+}
+
+static void ltq_spi_reset_fifos(struct ltq_spi *hw)
@ -475,7 +475,7 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ * SPI module clock is derived from FPI bus clock dependent on
+ * divider value in CLC.RMS which is always set to 1.
+ */
+ spi_clk = clk_get_rate(hw->clk);
+ spi_clk = clk_get_rate(hw->fpiclk);
+
+ /*
+ * Maximum SPI clock frequency in master mode is half of
@ -628,12 +628,12 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+}
+
+static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = {
+ { 15, 1, 0 },
+ { 22, 1, 0 },
+ { 13, 0, 1 },
+ { 10, 0, 1 },
+ { 9, 0, 1 },
+ { 11, 1, 1 },
+ { 15, 2 },
+ { 22, 2 },
+ { 13, 1 },
+ { 10, 1 },
+ { 9, 1 },
+ { 11, 3 },
+};
+
+static int ltq_spi_setup(struct spi_device *spi)
@ -680,9 +680,8 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ cstate->cs_activate = ltq_spi_gpio_cs_activate;
+ cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate;
+ } else {
+ ret = ltq_gpio_request(ltq_spi_cs[spi->chip_select].gpio,
+ ltq_spi_cs[spi->chip_select].altsel0,
+ ltq_spi_cs[spi->chip_select].altsel1,
+ ret = ltq_gpio_request(&spi->dev, ltq_spi_cs[spi->chip_select].gpio,
+ ltq_spi_cs[spi->chip_select].mux,
+ 1, "spi-cs");
+ if (ret)
+ return -EBUSY;
@ -989,10 +988,17 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ goto err_master;
+ }
+
+ hw->clk = clk_get(&pdev->dev, "fpi");
+ if (IS_ERR(hw->clk)) {
+ hw->fpiclk = clk_get_fpi();
+ if (IS_ERR(hw->fpiclk)) {
+ dev_err(&pdev->dev, "clk_get\n");
+ ret = PTR_ERR(hw->clk);
+ ret = PTR_ERR(hw->fpiclk);
+ goto err_master;
+ }
+
+ hw->spiclk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(hw->spiclk)) {
+ dev_err(&pdev->dev, "clk_get\n");
+ ret = PTR_ERR(hw->spiclk);
+ goto err_master;
+ }
+
@ -1028,9 +1034,9 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ spin_lock_init(&hw->lock);
+
+ /* Set GPIO alternate functions to SPI */
+ ltq_gpio_request(LTQ_SPI_GPIO_DI, 1, 0, 0, "spi-di");
+ ltq_gpio_request(LTQ_SPI_GPIO_DO, 1, 0, 1, "spi-do");
+ ltq_gpio_request(LTQ_SPI_GPIO_CLK, 1, 0, 1, "spi-clk");
+ ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DI, 2, 0, "spi-di");
+ ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DO, 2, 1, "spi-do");
+ ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_CLK, 2, 1, "spi-clk");
+
+ ltq_spi_hw_enable(hw);
+
@ -1076,7 +1082,7 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ ltq_spi_hw_disable(hw);
+
+err_irq:
+ clk_put(hw->clk);
+ clk_put(hw->fpiclk);
+
+ for (; i > 0; i--)
+ free_irq(hw->irq[i], hw);
@ -1110,7 +1116,7 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+ gpio_free(LTQ_SPI_GPIO_DO);
+ gpio_free(LTQ_SPI_GPIO_CLK);
+
+ clk_put(hw->clk);
+ clk_put(hw->fpiclk);
+ spi_master_put(hw->bitbang.master);
+
+ return 0;
@ -1118,7 +1124,7 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+
+static struct platform_driver ltq_spi_driver = {
+ .driver = {
+ .name = "ltq-spi",
+ .name = "ltq_spi",
+ .owner = THIS_MODULE,
+ },
+ .remove = __exit_p(ltq_spi_remove),
@ -1140,3 +1146,6 @@ Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
+MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ltq-spi");
--
1.7.7.1

1470
target/linux/lantiq/patches-3.2/0043-NET-adds-driver-for-lantiq-vr9-ethernet.patch Normal file
View File

File diff suppressed because it is too large Load Diff

445
target/linux/lantiq/patches-3.2/0044-MIPS-NET-several-fixes-to-etop-driver.patch Normal file
View File

@ -0,0 +1,445 @@
From 06663beb0230c02d1962eca8d9f6709c2e852328 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 21 Mar 2012 18:14:06 +0100
Subject: [PATCH 44/70] MIPS: NET: several fixes to etop driver
---
drivers/net/ethernet/lantiq_etop.c | 208 +++++++++++++++++++-----------------
1 files changed, 108 insertions(+), 100 deletions(-)
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index a084d74..1a807d8 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -103,15 +103,6 @@
/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9())
-/* use 2 static channels for TX/RX
- depending on the SoC we need to use different DMA channels for ethernet */
-#define LTQ_ETOP_TX_CHANNEL 1
-#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \
- ((ltq_has_gbit()) ? (0) : (6)))
-
-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
-
#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
#define ltq_etop_w32_mask(x, y, z) \
@@ -128,8 +119,8 @@ static void __iomem *ltq_etop_membase;
static void __iomem *ltq_gbit_membase;
struct ltq_etop_chan {
- int idx;
int tx_free;
+ int irq;
struct net_device *netdev;
struct napi_struct napi;
struct ltq_dma_channel dma;
@@ -144,8 +135,8 @@ struct ltq_etop_priv {
struct mii_bus *mii_bus;
struct phy_device *phydev;
- struct ltq_etop_chan ch[MAX_DMA_CHAN];
- int tx_free[MAX_DMA_CHAN >> 1];
+ struct ltq_etop_chan txch;
+ struct ltq_etop_chan rxch;
spinlock_t lock;
@@ -206,8 +197,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
{
struct ltq_etop_chan *ch = container_of(napi,
struct ltq_etop_chan, napi);
+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
int rx = 0;
int complete = 0;
+ unsigned long flags;
while ((rx < budget) && !complete) {
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
@@ -221,7 +214,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
}
if (complete || !rx) {
napi_complete(&ch->napi);
+ spin_lock_irqsave(&priv->lock, flags);
ltq_dma_ack_irq(&ch->dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
}
return rx;
}
@@ -233,7 +228,7 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
container_of(napi, struct ltq_etop_chan, napi);
struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
struct netdev_queue *txq =
- netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
@@ -251,7 +246,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
if (netif_tx_queue_stopped(txq))
netif_tx_start_queue(txq);
napi_complete(&ch->napi);
+ spin_lock_irqsave(&priv->lock, flags);
ltq_dma_ack_irq(&ch->dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
return 1;
}
@@ -259,9 +256,10 @@ static irqreturn_t
ltq_etop_dma_irq(int irq, void *_priv)
{
struct ltq_etop_priv *priv = _priv;
- int ch = irq - LTQ_DMA_ETOP;
-
- napi_schedule(&priv->ch[ch].napi);
+ if (irq == priv->txch.dma.irq)
+ napi_schedule(&priv->txch.napi);
+ else
+ napi_schedule(&priv->rxch.napi);
return IRQ_HANDLED;
}
@@ -273,7 +271,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
ltq_dma_free(&ch->dma);
if (ch->dma.irq)
free_irq(ch->dma.irq, priv);
- if (IS_RX(ch->idx)) {
+ if (ch == &priv->txch) {
int desc;
for (desc = 0; desc < LTQ_DESC_NUM; desc++)
dev_kfree_skb_any(ch->skb[ch->dma.desc]);
@@ -284,7 +282,6 @@ static void
ltq_etop_hw_exit(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
clk_disable(priv->clk_ppe);
@@ -296,9 +293,8 @@ ltq_etop_hw_exit(struct net_device *dev)
clk_disable(priv->clk_ephycgu);
}
- for (i = 0; i < MAX_DMA_CHAN; i++)
- if (IS_TX(i) || IS_RX(i))
- ltq_etop_free_channel(dev, &priv->ch[i]);
+ ltq_etop_free_channel(dev, &priv->txch);
+ ltq_etop_free_channel(dev, &priv->rxch);
}
static void
@@ -326,8 +322,6 @@ ltq_etop_hw_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned int mii_mode = priv->pldata->mii_mode;
- int err = 0;
- int i;
clk_enable(priv->clk_ppe);
@@ -369,31 +363,50 @@ ltq_etop_hw_init(struct net_device *dev)
/* enable crc generation */
ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
+ return 0;
+}
+
+static int
+ltq_etop_dma_init(struct net_device *dev)
+{
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+ int tx = 1;
+ int rx = ((ltq_is_ase()) ? (5) : \
+ ((ltq_is_ar9()) ? (0) : (6)));
+ int tx_irq = LTQ_DMA_ETOP + tx;
+ int rx_irq = LTQ_DMA_ETOP + rx;
+ int err;
+
ltq_dma_init_port(DMA_PORT_ETOP);
- for (i = 0; i < MAX_DMA_CHAN && !err; i++) {
- int irq = LTQ_DMA_ETOP + i;
- struct ltq_etop_chan *ch = &priv->ch[i];
-
- ch->idx = ch->dma.nr = i;
-
- if (IS_TX(i)) {
- ltq_dma_alloc_tx(&ch->dma);
- err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
- "etop_tx", priv);
- } else if (IS_RX(i)) {
- ltq_dma_alloc_rx(&ch->dma);
- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
- ch->dma.desc++)
- if (ltq_etop_alloc_skb(ch))
- err = -ENOMEM;
- ch->dma.desc = 0;
- err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
- "etop_rx", priv);
+ priv->txch.dma.nr = tx;
+ ltq_dma_alloc_tx(&priv->txch.dma);
+ err = request_irq(tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
+ "eth_tx", priv);
+ if (err) {
+ netdev_err(dev, "failed to allocate tx irq\n");
+ goto err_out;
+ }
+ priv->txch.dma.irq = tx_irq;
+
+ priv->rxch.dma.nr = rx;
+ ltq_dma_alloc_rx(&priv->rxch.dma);
+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
+ priv->rxch.dma.desc++) {
+ if (ltq_etop_alloc_skb(&priv->rxch)) {
+ netdev_err(dev, "failed to allocate skbs\n");
+ err = -ENOMEM;
+ goto err_out;
}
- if (!err)
- ch->dma.irq = irq;
}
+ priv->rxch.dma.desc = 0;
+ err = request_irq(rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
+ "eth_rx", priv);
+ if (err)
+ netdev_err(dev, "failed to allocate rx irq\n");
+ else
+ priv->rxch.dma.irq = rx_irq;
+err_out:
return err;
}
@@ -410,7 +423,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- return phy_ethtool_gset(priv->phydev, cmd);
+ if (priv->phydev)
+ return phy_ethtool_gset(priv->phydev, cmd);
+ else
+ return 0;
}
static int
@@ -418,7 +434,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- return phy_ethtool_sset(priv->phydev, cmd);
+ if (priv->phydev)
+ return phy_ethtool_sset(priv->phydev, cmd);
+ else
+ return 0;
}
static int
@@ -426,7 +445,10 @@ ltq_etop_nway_reset(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- return phy_start_aneg(priv->phydev);
+ if (priv->phydev)
+ return phy_start_aneg(priv->phydev);
+ else
+ return 0;
}
static const struct ethtool_ops ltq_etop_ethtool_ops = {
@@ -618,18 +640,19 @@ static int
ltq_etop_open(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
+ unsigned long flags;
- for (i = 0; i < MAX_DMA_CHAN; i++) {
- struct ltq_etop_chan *ch = &priv->ch[i];
+ napi_enable(&priv->txch.napi);
+ napi_enable(&priv->rxch.napi);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ ltq_dma_open(&priv->txch.dma);
+ ltq_dma_open(&priv->rxch.dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
- if (!IS_TX(i) && (!IS_RX(i)))
- continue;
- ltq_dma_open(&ch->dma);
- napi_enable(&ch->napi);
- }
if (priv->phydev)
phy_start(priv->phydev);
+
netif_tx_start_all_queues(dev);
return 0;
}
@@ -638,19 +661,19 @@ static int
ltq_etop_stop(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
+ unsigned long flags;
netif_tx_stop_all_queues(dev);
if (priv->phydev)
phy_stop(priv->phydev);
- for (i = 0; i < MAX_DMA_CHAN; i++) {
- struct ltq_etop_chan *ch = &priv->ch[i];
+ napi_disable(&priv->txch.napi);
+ napi_disable(&priv->rxch.napi);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ ltq_dma_close(&priv->txch.dma);
+ ltq_dma_close(&priv->rxch.dma);
+ spin_unlock_irqrestore(&priv->lock, flags);
- if (!IS_RX(i) && !IS_TX(i))
- continue;
- napi_disable(&ch->napi);
- ltq_dma_close(&ch->dma);
- }
return 0;
}
@@ -660,16 +683,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
int queue = skb_get_queue_mapping(skb);
struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
struct ltq_etop_priv *priv = netdev_priv(dev);
- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+ struct ltq_dma_desc *desc =
+ &priv->txch.dma.desc_base[priv->txch.dma.desc];
unsigned long flags;
u32 byte_offset;
int len;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
- dev_kfree_skb_any(skb);
+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
+ priv->txch.skb[priv->txch.dma.desc]) {
netdev_err(dev, "tx ring full\n");
netif_tx_stop_queue(txq);
return NETDEV_TX_BUSY;
@@ -677,7 +700,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
/* dma needs to start on a 16 byte aligned address */
byte_offset = CPHYSADDR(skb->data) % 16;
- ch->skb[ch->dma.desc] = skb;
+ priv->txch.skb[priv->txch.dma.desc] = skb;
dev->trans_start = jiffies;
@@ -687,11 +710,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
wmb();
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
- ch->dma.desc++;
- ch->dma.desc %= LTQ_DESC_NUM;
+ priv->txch.dma.desc++;
+ priv->txch.dma.desc %= LTQ_DESC_NUM;
spin_unlock_irqrestore(&priv->lock, flags);
- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
netif_tx_stop_queue(txq);
return NETDEV_TX_OK;
@@ -776,6 +799,10 @@ ltq_etop_init(struct net_device *dev)
err = ltq_etop_hw_init(dev);
if (err)
goto err_hw;
+ err = ltq_etop_dma_init(dev);
+ if (err)
+ goto err_hw;
+
ltq_etop_change_mtu(dev, 1500);
memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
@@ -811,6 +838,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
err = ltq_etop_hw_init(dev);
if (err)
goto err_hw;
+ err = ltq_etop_dma_init(dev);
+ if (err)
+ goto err_hw;
dev->trans_start = jiffies;
netif_wake_queue(dev);
return;
@@ -834,14 +864,13 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
.ndo_tx_timeout = ltq_etop_tx_timeout,
};
-static int __init
+static int __devinit
ltq_etop_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct ltq_etop_priv *priv;
struct resource *res, *gbit_res;
int err;
- int i;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -917,15 +946,10 @@ ltq_etop_probe(struct platform_device *pdev)
spin_lock_init(&priv->lock);
- for (i = 0; i < MAX_DMA_CHAN; i++) {
- if (IS_TX(i))
- netif_napi_add(dev, &priv->ch[i].napi,
- ltq_etop_poll_tx, 8);
- else if (IS_RX(i))
- netif_napi_add(dev, &priv->ch[i].napi,
- ltq_etop_poll_rx, 32);
- priv->ch[i].netdev = dev;
- }
+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
+ priv->txch.netdev = dev;
+ priv->rxch.netdev = dev;
err = register_netdev(dev);
if (err)
@@ -955,6 +979,7 @@ ltq_etop_remove(struct platform_device *pdev)
}
static struct platform_driver ltq_mii_driver = {
+ .probe = ltq_etop_probe,
.remove = __devexit_p(ltq_etop_remove),
.driver = {
.name = "ltq_etop",
@@ -962,24 +987,7 @@ static struct platform_driver ltq_mii_driver = {
},
};
-int __init
-init_ltq_etop(void)
-{
- int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
-
- if (ret)
- pr_err("ltq_etop: Error registering platfom driver!");
- return ret;
-}
-
-static void __exit
-exit_ltq_etop(void)
-{
- platform_driver_unregister(&ltq_mii_driver);
-}
-
-module_init(init_ltq_etop);
-module_exit(exit_ltq_etop);
+module_platform_driver(ltq_mii_driver);
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("Lantiq SoC ETOP");
--
1.7.7.1

64
target/linux/lantiq/patches-3.2/0045-MTD-MIPS-lantiq-use-module_platform_driver-inside-la.patch Normal file
View File

@ -0,0 +1,64 @@
From f94454615da63008ac865e6a7b03bbe79041e8c2 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 20 Feb 2012 12:15:25 +0100
Subject: [PATCH 45/70] MTD: MIPS: lantiq: use module_platform_driver inside
lantiq map driver
Reduce boilerplate code by converting driver to module_platform_driver.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mtd@lists.infradead.org
---
drivers/mtd/maps/lantiq-flash.c | 22 +++-------------------
1 files changed, 3 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 764d468..b55212c 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -108,7 +108,7 @@ ltq_copy_to(struct map_info *map, unsigned long to,
spin_unlock_irqrestore(&ebu_lock, flags);
}
-static int __init
+static int __devinit
ltq_mtd_probe(struct platform_device *pdev)
{
struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev);
@@ -208,6 +208,7 @@ ltq_mtd_remove(struct platform_device *pdev)
}
static struct platform_driver ltq_mtd_driver = {
+ .probe = ltq_mtd_probe,
.remove = __devexit_p(ltq_mtd_remove),
.driver = {
.name = "ltq_nor",
@@ -215,24 +216,7 @@ static struct platform_driver ltq_mtd_driver = {
},
};
-static int __init
-init_ltq_mtd(void)
-{
- int ret = platform_driver_probe(&ltq_mtd_driver, ltq_mtd_probe);
-
- if (ret)
- pr_err("ltq_nor: error registering platform driver");
- return ret;
-}
-
-static void __exit
-exit_ltq_mtd(void)
-{
- platform_driver_unregister(&ltq_mtd_driver);
-}
-
-module_init(init_ltq_mtd);
-module_exit(exit_ltq_mtd);
+module_platform_driver(ltq_mtd_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
--
1.7.7.1

61
target/linux/lantiq/patches-3.2/0046-WDT-MIPS-lantiq-use-module_platform_driver-inside-la.patch Normal file
View File

@ -0,0 +1,61 @@
From 7d332825d131e70daff66b934797c89f50c11ace Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 20 Feb 2012 12:16:31 +0100
Subject: [PATCH 46/70] WDT: MIPS: lantiq: use module_platform_driver inside
lantiq watchdog driver
Reduce boilerplate code by converting driver to module_platform_driver.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-watchdog@vger.kernel.org
---
drivers/watchdog/lantiq_wdt.c | 19 +++----------------
1 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index da2b09f..40c9eb7 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -182,7 +182,7 @@ static struct miscdevice ltq_wdt_miscdev = {
.fops = &ltq_wdt_fops,
};
-static int __init
+static int __devinit
ltq_wdt_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -230,6 +230,7 @@ ltq_wdt_remove(struct platform_device *pdev)
static struct platform_driver ltq_wdt_driver = {
+ .probe = ltq_wdt_probe,
.remove = __devexit_p(ltq_wdt_remove),
.driver = {
.name = "ltq_wdt",
@@ -237,21 +238,7 @@ static struct platform_driver ltq_wdt_driver = {
},
};
-static int __init
-init_ltq_wdt(void)
-{
- return platform_driver_probe(&ltq_wdt_driver, ltq_wdt_probe);
-}
-
-static void __exit
-exit_ltq_wdt(void)
-{
- return platform_driver_unregister(&ltq_wdt_driver);
-}
-
-module_init(init_ltq_wdt);
-module_exit(exit_ltq_wdt);
-
+module_platform_driver(ltq_wdt_driver);
module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
--
1.7.7.1

64
target/linux/lantiq/patches/0017-MIPS-lantiq-adds-GPTU-driver.patch → target/linux/lantiq/patches-3.2/0047-MIPS-lantiq-adds-GPTU-driver.patch
View File

@ -1,16 +1,20 @@
From 45dbb232686978816e8148753e12f27caa2b2eb3 Mon Sep 17 00:00:00 2001
From b672c54f9ae4504687a80bb51cdfe102bdae96e1 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 29 Sep 2011 17:16:38 +0200
Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
Subject: [PATCH 47/70] MIPS: lantiq: adds GPTU driver
---
arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++
arch/mips/lantiq/xway/Makefile | 2 +-
arch/mips/lantiq/xway/timer.c | 830 ++++++++++++++++++++++
3 files changed, 986 insertions(+), 1 deletions(-)
arch/mips/lantiq/xway/sysctrl.c | 1 +
arch/mips/lantiq/xway/timer.c | 846 ++++++++++++++++++++++
4 files changed, 1003 insertions(+), 1 deletions(-)
create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
create mode 100644 arch/mips/lantiq/xway/timer.c
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
new file mode 100644
index 0000000..ef564ab
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
@@ -0,0 +1,155 @@
@ -169,17 +173,34 @@ Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+ u32 reload, unsigned long arg1, unsigned long arg2);
+
+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 277aa34..4c3106f 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,4 +1,4 @@
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o
+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o timer.o
-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o
+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o
obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 38f02f9..1a2e2d4 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -147,6 +147,7 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
+ clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
if (!ltq_is_vr9())
clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
if (ltq_is_ase()) {
diff --git a/arch/mips/lantiq/xway/timer.c b/arch/mips/lantiq/xway/timer.c
new file mode 100644
index 0000000..9794c87
--- /dev/null
+++ b/arch/mips/lantiq/xway/timer.c
@@ -0,0 +1,830 @@
@@ -0,0 +1,846 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/version.h>
@ -195,6 +216,7 @@ Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+
+#include <asm/irq.h>
+#include <asm/div64.h>
+#include "../clk.h"
+
+#include <lantiq_soc.h>
+#include <lantiq_irq.h>
@ -332,7 +354,18 @@ Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
+};
+
+unsigned int ltq_get_fpi_bus_clock(int fpi);
+unsigned long ltq_danube_fpi_bus_clock(int fpi);
+unsigned long ltq_vr9_fpi_bus_clock(int fpi);
+
+unsigned int ltq_get_fpi_bus_clock(int fpi) {
+ if (ltq_is_ase())
+ return CLOCK_133M;
+ else if (ltq_is_vr9())
+ return ltq_vr9_fpi_bus_clock(fpi);
+
+ return ltq_danube_fpi_bus_clock(fpi);
+}
+
+
+static long gptu_ioctl(struct file *, unsigned int, unsigned long);
+static int gptu_open(struct inode *, struct file *);
@ -387,7 +420,10 @@ Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+
+static inline void lq_enable_gptu(void)
+{
+ ltq_pmu_enable(PMU_GPT);
+ struct clk *clk = clk_get_sys("ltq_gptu", NULL);
+ clk_enable(clk);
+
+ //ltq_pmu_enable(PMU_GPT);
+
+ /* Set divider as 1, disable write protection for SPEN, enable module. */
+ *LQ_GPTU_CLC =
@ -402,6 +438,7 @@ Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+
+static inline void lq_disable_gptu(void)
+{
+ struct clk *clk = clk_get_sys("ltq_gptu", NULL);
+ ltq_w32(0x00, LQ_GPTU_IRNEN);
+ ltq_w32(0xfff, LQ_GPTU_IRNCR);
+
@ -415,7 +452,7 @@ Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+ GPTU_CLC_SPEN_SET(0) |
+ GPTU_CLC_DISR_SET(1);
+
+ ltq_pmu_disable(PMU_GPT);
+ clk_enable(clk);
+}
+
+int lq_request_timer(unsigned int timer, unsigned int flag,
@ -1010,3 +1047,6 @@ Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+
+module_init(lq_gptu_init);
+module_exit(lq_gptu_exit);
--
1.7.7.1

73
target/linux/lantiq/patches/0018-MIPS-lantiq-adds-dwc_otg.patch → target/linux/lantiq/patches-3.2/0048-MIPS-lantiq-adds-dwc_otg.patch
View File

@ -1,7 +1,7 @@
From ffd7924fcc69ff146d62f131d72ef18575bf0227 Mon Sep 17 00:00:00 2001
From 668e5f88aa80ef8c4c8cb935c7c222146de79825 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 30 Sep 2011 14:37:36 +0200
Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
Subject: [PATCH 48/70] MIPS: lantiq: adds dwc_otg
---
drivers/usb/Kconfig | 2 +
@ -45,9 +45,11 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
create mode 100644 drivers/usb/dwc_otg/dwc_otg_plat.h
create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 791f11b..1eafa7a 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -116,6 +116,8 @@ source "drivers/usb/wusbcore/Kconfig"
@@ -129,6 +129,8 @@ source "drivers/usb/wusbcore/Kconfig"
source "drivers/usb/host/Kconfig"
@ -56,9 +58,11 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
source "drivers/usb/musb/Kconfig"
source "drivers/usb/renesas_usbhs/Kconfig"
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 75eca76..7fe8e83 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -28,6 +28,8 @@ obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
@@ -30,6 +30,8 @@ obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
obj-$(CONFIG_USB_WUSB) += wusbcore/
@ -67,9 +71,11 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
obj-$(CONFIG_USB_ACM) += class/
obj-$(CONFIG_USB_PRINTER) += class/
obj-$(CONFIG_USB_WDM) += class/
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 7978146..6a7df52 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -2891,11 +2891,11 @@ hub_port_init (struct usb_hub *hub, stru
@@ -2935,11 +2935,11 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
udev->ttport = hdev->ttport;
} else if (udev->speed != USB_SPEED_HIGH
&& hdev->speed == USB_SPEED_HIGH) {
@ -83,6 +89,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
udev->tt = &hub->tt;
udev->ttport = port1;
}
diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig
new file mode 100644
index 0000000..e018490
--- /dev/null
+++ b/drivers/usb/dwc_otg/Kconfig
@@ -0,0 +1,37 @@
@ -123,6 +132,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+config DWC_OTG_DEBUG
+ bool "Enable debug mode"
+ depends on DWC_OTG
diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile
new file mode 100644
index 0000000..d4d2355
--- /dev/null
+++ b/drivers/usb/dwc_otg/Makefile
@@ -0,0 +1,39 @@
@ -165,6 +177,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+
+#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o
+#dwc_otg_ifx-objs := dwc_otg_ifx.o
diff --git a/drivers/usb/dwc_otg/dwc_otg_attr.c b/drivers/usb/dwc_otg/dwc_otg_attr.c
new file mode 100644
index 0000000..4675a5c
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_attr.c
@@ -0,0 +1,802 @@
@ -970,6 +985,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+ device_remove_file(_dev, &dev_attr_rd_reg_test);
+ device_remove_file(_dev, &dev_attr_wr_reg_test);
+}
diff --git a/drivers/usb/dwc_otg/dwc_otg_attr.h b/drivers/usb/dwc_otg/dwc_otg_attr.h
new file mode 100644
index 0000000..4bbf7df
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_attr.h
@@ -0,0 +1,67 @@
@ -1040,6 +1058,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+void dwc_otg_attr_remove (struct device *_dev);
+
+#endif
diff --git a/drivers/usb/dwc_otg/dwc_otg_cil.c b/drivers/usb/dwc_otg/dwc_otg_cil.c
new file mode 100644
index 0000000..42c69eb
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
@@ -0,0 +1,3025 @@
@ -4068,6 +4089,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+ _cb->p = _p;
+}
+
diff --git a/drivers/usb/dwc_otg/dwc_otg_cil.h b/drivers/usb/dwc_otg/dwc_otg_cil.h
new file mode 100644
index 0000000..bbb9516
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_cil.h
@@ -0,0 +1,911 @@
@ -4982,6 +5006,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+
+
+#endif
diff --git a/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
new file mode 100644
index 0000000..b0298ec
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
@@ -0,0 +1,58 @@
@ -5043,6 +5070,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+
+#endif // __DWC_OTG_CIL_IFX_H__
+
diff --git a/drivers/usb/dwc_otg/dwc_otg_cil_intr.c b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
new file mode 100644
index 0000000..d469ab4
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
@@ -0,0 +1,708 @@
@ -5754,6 +5784,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+ }
+ return retval;
+}
diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.c b/drivers/usb/dwc_otg/dwc_otg_driver.c
new file mode 100644
index 0000000..1b0daab
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
@@ -0,0 +1,1274 @@
@ -7031,6 +7064,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+ </td></tr>
+
+*/
diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.h b/drivers/usb/dwc_otg/dwc_otg_driver.h
new file mode 100644
index 0000000..7e6940d
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_driver.h
@@ -0,0 +1,84 @@
@ -7118,6 +7154,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg)
+
+#endif
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd.c b/drivers/usb/dwc_otg/dwc_otg_hcd.c
new file mode 100644
index 0000000..ad6bc72
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c
@@ -0,0 +1,2870 @@
@ -9991,6 +10030,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+#endif
+}
+#endif /* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd.h b/drivers/usb/dwc_otg/dwc_otg_hcd.h
new file mode 100644
index 0000000..8a20dff
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h
@@ -0,0 +1,676 @@
@ -10670,6 +10712,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+#endif // DEBUG
+#endif // __DWC_HCD_H__
+#endif /* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 0000000..834b5e0
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,1841 @@
@ -12514,6 +12559,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+}
+
+#endif /* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 0000000..fcb5ce6
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,794 @@
@ -13311,6 +13359,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+}
+
+#endif /* DWC_DEVICE_ONLY */
diff --git a/drivers/usb/dwc_otg/dwc_otg_ifx.c b/drivers/usb/dwc_otg/dwc_otg_ifx.c
new file mode 100644
index 0000000..0a4c209
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
@@ -0,0 +1,100 @@
@ -13414,6 +13465,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+void ifx_usb_hc_remove(void)
+{
+}
diff --git a/drivers/usb/dwc_otg/dwc_otg_ifx.h b/drivers/usb/dwc_otg/dwc_otg_ifx.h
new file mode 100644
index 0000000..402d7a6
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.h
@@ -0,0 +1,85 @@
@ -13502,6 +13556,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+ ltq_mask_and_ack_irq(&d);
+}
+#endif //__DWC_OTG_IFX_H__
diff --git a/drivers/usb/dwc_otg/dwc_otg_plat.h b/drivers/usb/dwc_otg/dwc_otg_plat.h
new file mode 100644
index 0000000..727d0c4
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_plat.h
@@ -0,0 +1,269 @@
@ -13774,6 +13831,9 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+
+#endif
+
diff --git a/drivers/usb/dwc_otg/dwc_otg_regs.h b/drivers/usb/dwc_otg/dwc_otg_regs.h
new file mode 100644
index 0000000..397a954
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_regs.h
@@ -0,0 +1,1797 @@
@ -15574,3 +15634,6 @@ Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+} dwc_otg_host_if_t;
+
+#endif
--
1.7.7.1

26
target/linux/lantiq/patches-3.2/0049-dwc_otg-remove-bogus-halt_channel.patch Normal file
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@ -0,0 +1,26 @@
From 7f73b86b26fc58e0513a792533b7e11450aa0737 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 23 Mar 2012 16:14:33 +0100
Subject: [PATCH 49/70] dwc_otg: remove bogus halt_channel
https://lists.openwrt.org/pipermail/openwrt-devel/2012-March/014524.html
---
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
index 834b5e0..f6f3f3d 100644
--- a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -1278,8 +1278,6 @@ static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *_hcd,
* automatically executes the PING, then the transfer.
*/
halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free);
- } else {
- halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
}
}
--
1.7.7.1

16672
target/linux/lantiq/patches-3.2/0050-MIPS-adds-ifxhcd.patch Normal file
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File diff suppressed because it is too large Load Diff

195
target/linux/lantiq/patches-3.2/0051-MIPS-adds-gptu-driver.patch Normal file
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@ -0,0 +1,195 @@
From a7c55f5e927b69bb30912fe1c3e5bcd8751e8381 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 14 Mar 2012 15:37:19 +0100
Subject: [PATCH 51/70] MIPS: adds gptu driver
---
arch/mips/lantiq/xway/gptu.c | 176 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 176 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/lantiq/xway/gptu.c
diff --git a/arch/mips/lantiq/xway/gptu.c b/arch/mips/lantiq/xway/gptu.c
new file mode 100644
index 0000000..ac82c37
--- /dev/null
+++ b/arch/mips/lantiq/xway/gptu.c
@@ -0,0 +1,176 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/pm.h>
+#include <linux/export.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <asm/reboot.h>
+
+#include <lantiq_soc.h>
+#include "../clk.h"
+
+#include "../devices.h"
+
+#define ltq_gptu_w32(x, y) ltq_w32((x), ltq_gptu_membase + (y))
+#define ltq_gptu_r32(x) ltq_r32(ltq_gptu_membase + (x))
+
+
+/* the magic ID byte of the core */
+#define GPTU_MAGIC 0x59
+/* clock control register */
+#define GPTU_CLC 0x00
+/* id register */
+#define GPTU_ID 0x08
+/* interrupt node enable */
+#define GPTU_IRNEN 0xf4
+/* interrupt control register */
+#define GPTU_IRCR 0xf8
+/* interrupt capture register */
+#define GPTU_IRNCR 0xfc
+/* there are 3 identical blocks of 2 timers. calculate register offsets */
+#define GPTU_SHIFT(x) (x % 2 ? 4 : 0)
+#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10)
+/* timer control register */
+#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
+/* timer auto reload register */
+#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
+/* timer manual reload register */
+#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
+/* timer count register */
+#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
+
+/* GPTU_CON(x) */
+#define CON_CNT BIT(2)
+#define CON_EDGE_FALL BIT(7)
+#define CON_SYNC BIT(8)
+#define CON_CLK_INT BIT(10)
+
+/* GPTU_RUN(x) */
+#define RUN_SEN BIT(0)
+#define RUN_RL BIT(2)
+
+/* set clock to runmode */
+#define CLC_RMC BIT(8)
+/* bring core out of suspend */
+#define CLC_SUSPEND BIT(4)
+/* the disable bit */
+#define CLC_DISABLE BIT(0)
+
+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
+
+enum gptu_timer {
+ TIMER1A = 0,
+ TIMER1B,
+ TIMER2A,
+ TIMER2B,
+ TIMER3A,
+ TIMER3B
+};
+
+static struct resource ltq_gptu_resource =
+ MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE);
+
+static void __iomem *ltq_gptu_membase;
+
+static irqreturn_t timer_irq_handler(int irq, void *priv)
+{
+ int timer = irq - TIMER_INTERRUPT;
+ ltq_gptu_w32(1 << timer, GPTU_IRNCR);
+ return IRQ_HANDLED;
+}
+
+static void gptu_hwinit(void)
+{
+ struct clk *clk = clk_get_sys("ltq_gptu", NULL);
+ clk_enable(clk);
+ ltq_gptu_w32(0x00, GPTU_IRNEN);
+ ltq_gptu_w32(0xff, GPTU_IRNCR);
+ ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
+}
+
+static void gptu_hwexit(void)
+{
+ ltq_gptu_w32(0x00, GPTU_IRNEN);
+ ltq_gptu_w32(0xff, GPTU_IRNCR);
+ ltq_gptu_w32(CLC_DISABLE, GPTU_CLC);
+}
+
+static int ltq_gptu_enable(struct clk *clk)
+{
+ int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler,
+ IRQF_TIMER, "timer", NULL);
+ if (ret) {
+ pr_err("gptu: failed to request irq\n");
+ return ret;
+ }
+
+ ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT,
+ GPTU_CON(clk->bits));
+ ltq_gptu_w32(1, GPTU_RLD(clk->bits));
+ ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN);
+ ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
+ return 0;
+}
+
+static void ltq_gptu_disable(struct clk *clk)
+{
+ ltq_gptu_w32(0, GPTU_RUN(clk->bits));
+ ltq_gptu_w32(0, GPTU_CON(clk->bits));
+ ltq_gptu_w32(0, GPTU_RLD(clk->bits));
+ ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN);
+ free_irq(TIMER_INTERRUPT + clk->bits, NULL);
+}
+
+static inline void clkdev_add_gptu(const char *con, unsigned int timer)
+{
+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+ clk->cl.dev_id = "ltq_gptu";
+ clk->cl.con_id = con;
+ clk->cl.clk = clk;
+ clk->enable = ltq_gptu_enable;
+ clk->disable = ltq_gptu_disable;
+ clk->bits = timer;
+ clkdev_add(&clk->cl);
+}
+
+static int __init gptu_setup(void)
+{
+ /* remap gptu register range */
+ ltq_gptu_membase = ltq_remap_resource(&ltq_gptu_resource);
+ if (!ltq_gptu_membase)
+ panic("Failed to remap gptu memory");
+
+ /* power up the core */
+ gptu_hwinit();
+
+ /* the gptu has a ID register */
+ if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
+ pr_err("gptu: failed to find magic\n");
+ gptu_hwexit();
+ return -ENAVAIL;
+ }
+
+ /* register the clocks */
+ clkdev_add_gptu("timer1a", TIMER1A);
+ clkdev_add_gptu("timer1b", TIMER1B);
+ clkdev_add_gptu("timer2a", TIMER2A);
+ clkdev_add_gptu("timer2b", TIMER2B);
+ clkdev_add_gptu("timer3a", TIMER3A);
+ clkdev_add_gptu("timer3b", TIMER3B);
+
+ pr_info("gptu: 6 timers loaded\n");
+
+ return 0;
+}
+
+arch_initcall(gptu_setup);
--
1.7.7.1

79
target/linux/lantiq/patches-3.2/0052-MIPS-lantiq-pci-rename-variable-inside.patch Normal file
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@ -0,0 +1,79 @@
From 3571f6a294783e617c2f8f52021f9c33bc9e5a36 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 12:00:17 +0100
Subject: [PATCH 52/70] MIPS: lantiq: pci: rename variable inside
* rename a global var inside the pci code
---
arch/mips/pci/ops-lantiq.c | 6 +++---
arch/mips/pci/pci-lantiq.c | 6 +++---
arch/mips/pci/pci-lantiq.h | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
index 1f2afb5..5cbb0cf 100644
--- a/arch/mips/pci/ops-lantiq.c
+++ b/arch/mips/pci/ops-lantiq.c
@@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
spin_lock_irqsave(&ebu_lock, flags);
- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
+ cfg_base = (unsigned long) ltq_pci_cfgbase;
cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
@@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
wmb();
/* clean possible Master abort */
- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
+ cfg_base = (unsigned long) ltq_pci_cfgbase;
cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
temp = ltq_r32(((u32 *)(cfg_base)));
temp = swab32(temp);
- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
+ cfg_base = (unsigned long) ltq_pci_cfgbase;
cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
ltq_w32(temp, ((u32 *)cfg_base));
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 47b551c..efcdd45 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -65,8 +65,8 @@
#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
-#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
-#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
+#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_cfgbase + (y))
+#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_cfgbase + (x))
struct ltq_pci_gpio_map {
int pin;
@@ -273,7 +273,7 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
pci_probe_only = 0;
ltq_pci_irq_map = ltq_pci_data->irq;
ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
- ltq_pci_mapped_cfg =
+ ltq_pci_cfgbase =
ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
ltq_pci_controller.io_map_base =
(unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h
index 66bf6cd..c4721b4 100644
--- a/arch/mips/pci/pci-lantiq.h
+++ b/arch/mips/pci/pci-lantiq.h
@@ -9,7 +9,7 @@
#ifndef _LTQ_PCI_H__
#define _LTQ_PCI_H__
-extern __iomem void *ltq_pci_mapped_cfg;
+extern __iomem void *ltq_pci_cfgbase;
extern int ltq_pci_read_config_dword(struct pci_bus *bus,
unsigned int devfn, int where, int size, u32 *val);
extern int ltq_pci_write_config_dword(struct pci_bus *bus,
--
1.7.7.1

45
target/linux/lantiq/patches-3.2/0053-MIPS-lantiq-pci-give-xway-pci-support-its-own-kbuild.patch Normal file
View File

@ -0,0 +1,45 @@
From 00dda451e12b6fc519cd4f575a696c4216f45992 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 13:13:31 +0100
Subject: [PATCH 53/70] MIPS: lantiq: pci: give xway pci support its own
kbuild symbol
---
arch/mips/lantiq/Kconfig | 5 +++++
arch/mips/pci/Makefile | 2 +-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index cb6b39f..dde9fc6 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -19,8 +19,13 @@ config SOC_XWAY
config SOC_FALCON
bool "FALCON"
+
endchoice
+config PCI_LANTIQ
+ bool "PCI Support"
+ depends on SOC_XWAY && PCI
+
source "arch/mips/lantiq/xway/Kconfig"
source "arch/mips/lantiq/falcon/Kconfig"
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bb82cbd..afad91d 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -40,7 +40,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
-obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o
+obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
--
1.7.7.1

131
target/linux/lantiq/patches-3.2/0054-MIPS-lantiq-pci-move-pcibios-code-into-fixup-lantiq..patch Normal file
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@ -0,0 +1,131 @@
From 49b5d2242091e216736216d98d7f940870d4f1ec Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 8 Mar 2012 15:53:10 +0100
Subject: [PATCH 54/70] MIPS: lantiq: pci: move pcibios code into
fixup-lantiq.c
---
arch/mips/pci/Makefile | 1 +
arch/mips/pci/fixup-lantiq.c | 42 ++++++++++++++++++++++++++++++++++++++++++
arch/mips/pci/pci-lantiq.c | 24 ++----------------------
3 files changed, 45 insertions(+), 22 deletions(-)
create mode 100644 arch/mips/pci/fixup-lantiq.c
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index afad91d..3ca5f75 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
+obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
diff --git a/arch/mips/pci/fixup-lantiq.c b/arch/mips/pci/fixup-lantiq.c
new file mode 100644
index 0000000..daf5ae9
--- /dev/null
+++ b/arch/mips/pci/fixup-lantiq.c
@@ -0,0 +1,42 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+
+int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin) = NULL;
+int (*ltqpci_plat_arch_init)(struct pci_dev *dev) = NULL;
+int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
+int *ltq_pci_irq_map;
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ if (ltqpci_plat_arch_init)
+ return ltqpci_plat_arch_init(dev);
+
+ if (ltqpci_plat_dev_init)
+ return ltqpci_plat_dev_init(dev);
+
+ return 0;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ if (ltqpci_map_irq)
+ return ltqpci_map_irq(dev, slot, pin);
+ if (ltq_pci_irq_map[slot]) {
+ dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, ltq_pci_irq_map[slot]);
+ return ltq_pci_irq_map[slot];
+ }
+ printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
+ slot);
+
+ return 0;
+}
+
+
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index efcdd45..7a29738 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -93,16 +93,14 @@ static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
{ 37, 2, 0, "pci-req4" },
};
-__iomem void *ltq_pci_mapped_cfg;
+__iomem void *ltq_pci_cfgbase;
static __iomem void *ltq_pci_membase;
-int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
-
/* Since the PCI REQ pins can be reused for other functionality, make it
possible to exclude those from interpretation by the PCI controller */
static int ltq_pci_req_mask = 0xf;
-static int *ltq_pci_irq_map;
+extern int *ltq_pci_irq_map;
struct pci_ops ltq_pci_ops = {
.read = ltq_pci_read_config_dword,
@@ -131,14 +129,6 @@ static struct pci_controller ltq_pci_controller = {
.io_offset = 0x00000000UL,
};
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- if (ltqpci_plat_dev_init)
- return ltqpci_plat_dev_init(dev);
-
- return 0;
-}
-
static u32 ltq_calc_bar11mask(void)
{
u32 mem, bar11mask;
@@ -256,16 +246,6 @@ static int __devinit ltq_pci_startup(struct device *dev)
return 0;
}
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- if (ltq_pci_irq_map[slot])
- return ltq_pci_irq_map[slot];
- printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
- slot);
-
- return 0;
-}
-
static int __devinit ltq_pci_probe(struct platform_device *pdev)
{
struct ltq_pci_data *ltq_pci_data =
--
1.7.7.1

3503
target/linux/lantiq/patches-3.2/0055-MIPS-lantiq-pcie-add-pcie-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

95
target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch → target/linux/lantiq/patches-3.2/0056-MIPS-lantiq-make-GPIO3-work-on-AR9.patch
View File

@ -1,7 +1,7 @@
From 92b24777385cd8388e0fa8b9f1d24e5bc4466641 Mon Sep 17 00:00:00 2001
From b11a96f2bdf1730fe3fd3be1d0667e20a4eb5bff Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 13 Aug 2011 13:59:50 +0200
Subject: [PATCH 12/22] MIPS: lantiq: make GPIO3 work on AR9
Subject: [PATCH 56/70] MIPS: lantiq: make GPIO3 work on AR9
There are 3 16bit and 1 8bit gpio ports on AR9. The gpio driver needs a hack
at 2 places to make the different register layout of the GPIO3 work properly
@ -13,14 +13,16 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
arch/mips/lantiq/xway/devices.c | 3 +
arch/mips/lantiq/xway/gpio.c | 62 ++++++++++++++++----
arch/mips/lantiq/xway/gpio.c | 84 ++++++++++++++++----
arch/mips/lantiq/xway/gpio_ebu.c | 3 +-
arch/mips/lantiq/xway/gpio_stp.c | 3 +-
5 files changed, 57 insertions(+), 16 deletions(-)
5 files changed, 75 insertions(+), 20 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index d1b8cc8..bfdeb16 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -121,7 +121,9 @@
@@ -126,7 +126,9 @@
#define LTQ_GPIO0_BASE_ADDR 0x1E100B10
#define LTQ_GPIO1_BASE_ADDR 0x1E100B40
#define LTQ_GPIO2_BASE_ADDR 0x1E100B70
@ -30,9 +32,11 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
/* SSC */
#define LTQ_SSC_BASE_ADDR 0x1e100800
diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
index 5efa4f3..e6d45bc 100644
--- a/arch/mips/lantiq/xway/devices.c
+++ b/arch/mips/lantiq/xway/devices.c
@@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource
@@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource[] = {
MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
@ -49,14 +53,18 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
}
}
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index 54ec6c9..375329b 100644
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -23,9 +23,15 @@
@@ -23,9 +23,17 @@
#define LTQ_GPIO_OD 0x14
#define LTQ_GPIO_PUDSEL 0x1C
#define LTQ_GPIO_PUDEN 0x20
+#define LTQ_GPIO3_OD 0x24
+#define LTQ_GPIO3_ALTSEL1 0x24
+#define LTQ_GPIO3_PUDSEL 0x28
+#define LTQ_GPIO3_PUDEN 0x2C
+/* PORT3 only has 8 pins and its register layout
+ is slightly different */
@ -68,34 +76,34 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r)
@@ -55,7 +61,7 @@ int ltq_gpio_request(unsigned int pin, u
@@ -55,7 +63,7 @@ int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux,
{
int id = 0;
- if (pin >= (MAX_PORTS * PINS_PER_PORT))
+ if (pin >= MAX_PIN)
return -EINVAL;
if (gpio_request(pin, name)) {
if (devm_gpio_request(dev, pin, name)) {
pr_err("failed to setup lantiq gpio: %s\n", name);
@@ -75,12 +81,21 @@ int ltq_gpio_request(unsigned int pin, u
@@ -75,12 +83,21 @@ int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux,
else
ltq_gpio_clearbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL0, pin);
- if (alt1)
- if (mux & 0x1)
- ltq_gpio_setbit(ltq_gpio_port[id].membase,
- LTQ_GPIO_ALTSEL1, pin);
- else
- ltq_gpio_clearbit(ltq_gpio_port[id].membase,
- LTQ_GPIO_ALTSEL1, pin);
+ if (id == 3) {
+ if (alt1)
+ if (mux & 0x1)
+ ltq_gpio_setbit(ltq_gpio_port[1].membase,
+ LTQ_GPIO3_ALTSEL1, pin);
+ else
+ ltq_gpio_clearbit(ltq_gpio_port[1].membase,
+ LTQ_GPIO3_ALTSEL1, pin);
+ } else {
+ if (alt1)
+ if (mux & 0x1)
+ ltq_gpio_setbit(ltq_gpio_port[id].membase,
+ LTQ_GPIO_ALTSEL1, pin);
+ else
@ -105,32 +113,53 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
return 0;
}
EXPORT_SYMBOL(ltq_gpio_request);
@@ -106,7 +121,11 @@ static int ltq_gpio_direction_input(stru
@@ -106,10 +123,19 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ if (chip->ngpio == PINS_PORT3)
+ if (chip->ngpio == PINS_PORT3) {
+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
+ LTQ_GPIO3_OD, offset);
+ else
+ ltq_gpio_setbit(ltq_gpio_port[0].membase,
+ LTQ_GPIO3_PUDSEL, offset);
+ ltq_gpio_setbit(ltq_gpio_port[0].membase,
+ LTQ_GPIO3_PUDEN, offset);
+ } else {
+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
+ }
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
@@ -119,7 +138,10 @@ static int ltq_gpio_direction_output(str
- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
return 0;
}
@@ -119,10 +145,19 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip,
{
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ if (chip->ngpio == PINS_PORT3)
+ ltq_gpio_setbit(ltq_gpio_port[0].membase, LTQ_GPIO3_OD, offset);
+ else
+ if (chip->ngpio == PINS_PORT3) {
+ ltq_gpio_setbit(ltq_gpio_port[0].membase,
+ LTQ_GPIO3_OD, offset);
+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
+ LTQ_GPIO3_PUDSEL, offset);
+ ltq_gpio_clearbit(ltq_gpio_port[0].membase,
+ LTQ_GPIO3_PUDEN, offset);
+ } else {
+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
+ }
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
@@ -133,7 +155,11 @@ static int ltq_gpio_req(struct gpio_chip
- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
ltq_gpio_set(chip, offset, value);
return 0;
@@ -133,7 +168,11 @@ static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
@ -143,14 +172,15 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
return 0;
}
@@ -146,6 +172,15 @@ static int ltq_gpio_probe(struct platfor
@@ -146,6 +185,16 @@ static int ltq_gpio_probe(struct platform_device *pdev)
pdev->id);
return -EINVAL;
}
+
+ /* dirty hack - The registers of port3 are not mapped linearly.
+ Port 3 may only load if Port 1/2 are mapped */
+ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase || !ltq_gpio_port[2].membase)) {
+ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase
+ || !ltq_gpio_port[2].membase)) {
+ dev_err(&pdev->dev,
+ "ports 1/2 need to be loaded before port 3 works\n");
+ return -ENOMEM;
@ -159,7 +189,7 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
@@ -175,7 +210,10 @@ static int ltq_gpio_probe(struct platfor
@@ -175,7 +224,10 @@ static int ltq_gpio_probe(struct platform_device *pdev)
ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
@ -171,6 +201,8 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
}
diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c
index b91c7f1..bc5696b 100644
--- a/arch/mips/lantiq/xway/gpio_ebu.c
+++ b/arch/mips/lantiq/xway/gpio_ebu.c
@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = {
@ -184,9 +216,11 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
.owner = THIS_MODULE,
};
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index da91c5e..9610c10 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -72,9 +72,8 @@ static struct gpio_chip ltq_stp_chip = {
@@ -74,9 +74,8 @@ static struct gpio_chip ltq_stp_chip = {
.label = "ltq_stp",
.direction_output = ltq_stp_direction_output,
.set = ltq_stp_set,
@ -197,3 +231,6 @@ Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
.owner = THIS_MODULE,
};
--
1.7.7.1

67
target/linux/lantiq/patches/0019-MIPS-lantiq-adds-VPE-extensions.patch → target/linux/lantiq/patches-3.2/0057-MIPS-lantiq-VPE-extensions.patch
View File

@ -1,7 +1,7 @@
From c6c810d83f0d95f54c3a6b338d219cec7ccef4c9 Mon Sep 17 00:00:00 2001
From 587ca6b21ab64ab014625b1cacb36ef711c74962 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 29 Sep 2011 20:30:40 +0200
Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
Subject: [PATCH 57/70] MIPS: lantiq: VPE extensions
---
arch/mips/Kconfig | 22 +++
@ -17,9 +17,11 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
create mode 100644 arch/mips/kernel/mtsched_proc.c
create mode 100644 arch/mips/kernel/perf_proc.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bbaff9b..902aedb 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1915,6 +1915,28 @@ config MIPS_VPE_LOADER
@@ -1897,6 +1897,28 @@ config MIPS_VPE_LOADER
Includes a loader for loading an elf relocatable object
onto another VPE and running it.
@ -48,6 +50,8 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
config MIPS_MT_SMTC_IM_BACKSTOP
bool "Use per-TC register bits as backstop for inhibited IM bits"
depends on MIPS_MT_SMTC
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index c9420aa..04bfb4b 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -28,14 +28,34 @@
@ -157,9 +161,11 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
/* GPR */
#define read_tc_gpr_sp() mftgpr(29)
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 1a96618..bc5989e 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -86,7 +86,8 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo3
@@ -88,7 +88,8 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o
obj-$(CONFIG_KGDB) += kgdb.o
obj-$(CONFIG_PROC_FS) += proc.o
@ -169,6 +175,8 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
obj-$(CONFIG_64BIT) += cpu-bugs64.o
obj-$(CONFIG_I8253) += i8253.o
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index c23d11f..11d6489 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -21,26 +21,96 @@
@ -273,7 +281,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
/*
* Dump new MIPS MT state for the core. Does not leave TCs halted.
@@ -78,18 +148,18 @@ void mips_mt_regdump(unsigned long mvpct
@@ -78,18 +148,18 @@ void mips_mt_regdump(unsigned long mvpctl)
if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
printk(" VPE %d\n", i);
printk(" VPEControl : %08lx\n",
@ -309,6 +317,9 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
}
/*
diff --git a/arch/mips/kernel/mtsched_proc.c b/arch/mips/kernel/mtsched_proc.c
new file mode 100644
index 0000000..4dafded
--- /dev/null
+++ b/arch/mips/kernel/mtsched_proc.c
@@ -0,0 +1,279 @@
@ -591,6 +602,9 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
+
+/* Automagically create the entry */
+module_init(init_mtsched_proc);
diff --git a/arch/mips/kernel/perf_proc.c b/arch/mips/kernel/perf_proc.c
new file mode 100644
index 0000000..7eec015
--- /dev/null
+++ b/arch/mips/kernel/perf_proc.c
@@ -0,0 +1,191 @@
@ -785,6 +799,8 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
+
+/* Automagically create the entry */
+module_init(init_perf_proc);
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index e309665..2de204f 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -7,6 +7,7 @@
@ -795,7 +811,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
@@ -110,3 +111,19 @@ const struct seq_operations cpuinfo_op =
@@ -110,3 +111,19 @@ const struct seq_operations cpuinfo_op = {
.stop = c_stop,
.show = show_cpuinfo,
};
@ -815,9 +831,11 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
+ mips_proc = proc_mkdir("mips", NULL);
+ return(mips_proc);
+}
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f0895e7..199e853 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1334,6 +1334,13 @@ void smtc_get_new_mmu_context(struct mm_
@@ -1334,6 +1334,13 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
asid = asid_cache(cpu);
do {
@ -831,9 +849,11 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
if (!((asid += ASID_INC) & ASID_MASK) ) {
if (cpu_has_vtag_icache)
flush_icache_all();
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index bfa12a4..e338ba5 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -76,6 +76,58 @@ static struct kspd_notifications kspd_ev
@@ -75,6 +75,58 @@ static struct kspd_notifications kspd_events;
static int kspd_events_reqd;
#endif
@ -892,7 +912,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
/* grab the likely amount of memory we will need. */
#ifdef CONFIG_MIPS_VPE_LOADER_TOM
#define P_SIZE (2 * 1024 * 1024)
@@ -268,6 +320,13 @@ static void *alloc_progmem(unsigned long
@@ -267,6 +319,13 @@ static void *alloc_progmem(unsigned long len)
void *addr;
#ifdef CONFIG_MIPS_VPE_LOADER_TOM
@ -906,7 +926,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
/*
* This means you must tell Linux to use less memory than you
* physically have, for example by passing a mem= boot argument.
@@ -746,6 +805,12 @@ static int vpe_run(struct vpe * v)
@@ -745,6 +804,12 @@ static int vpe_run(struct vpe * v)
}
/* Write the address we want it to start running from in the TCPC register. */
@ -919,7 +939,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
write_tc_c0_tcrestart((unsigned long)v->__start);
write_tc_c0_tccontext((unsigned long)0);
@@ -759,6 +824,20 @@ static int vpe_run(struct vpe * v)
@@ -758,6 +823,20 @@ static int vpe_run(struct vpe * v)
write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
@ -940,7 +960,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
/*
* The sde-kit passes 'memsize' to __start in $a3, so set something
* here... Or set $a3 to zero and define DFLT_STACK_SIZE and
@@ -833,6 +912,9 @@ static int find_vpe_symbols(struct vpe *
@@ -832,6 +911,9 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
if ( (v->__start == 0) || (v->shared_ptr == NULL))
return -1;
@ -950,7 +970,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
return 0;
}
@@ -994,6 +1076,15 @@ static int vpe_elfload(struct vpe * v)
@@ -993,6 +1075,15 @@ static int vpe_elfload(struct vpe * v)
(unsigned long)v->load_addr + v->len);
if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
@ -966,7 +986,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
if (v->__start == 0) {
printk(KERN_WARNING "VPE loader: program does not contain "
"a __start symbol\n");
@@ -1064,6 +1155,9 @@ static int vpe_open(struct inode *inode,
@@ -1063,6 +1154,9 @@ static int vpe_open(struct inode *inode, struct file *filp)
struct vpe_notifications *not;
struct vpe *v;
int ret;
@ -976,7 +996,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
if (minor != iminor(inode)) {
/* assume only 1 device at the moment. */
@@ -1089,7 +1183,12 @@ static int vpe_open(struct inode *inode,
@@ -1088,7 +1182,12 @@ static int vpe_open(struct inode *inode, struct file *filp)
release_progmem(v->load_addr);
cleanup_tc(get_tc(tclimit));
}
@ -990,7 +1010,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
/* this of-course trashes what was there before... */
v->pbuffer = vmalloc(P_SIZE);
if (!v->pbuffer) {
@@ -1097,11 +1196,14 @@ static int vpe_open(struct inode *inode,
@@ -1096,11 +1195,14 @@ static int vpe_open(struct inode *inode, struct file *filp)
return -ENOMEM;
}
v->plen = P_SIZE;
@ -1005,7 +1025,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
#ifdef CONFIG_MIPS_APSP_KSPD
/* get kspd to tell us when a syscall_exit happens */
@@ -1349,6 +1451,133 @@ static void kspd_sp_exit( int sp_id)
@@ -1348,6 +1450,133 @@ static void kspd_sp_exit( int sp_id)
cleanup_tc(get_tc(sp_id));
}
#endif
@ -1139,7 +1159,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
const char *buf, size_t len)
@@ -1430,6 +1659,18 @@ static int __init vpe_module_init(void)
@@ -1429,6 +1658,18 @@ static int __init vpe_module_init(void)
printk("VPE loader: not a MIPS MT capable processor\n");
return -ENODEV;
}
@ -1158,7 +1178,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
if (vpelimit == 0) {
printk(KERN_WARNING "No VPEs reserved for AP/SP, not "
@@ -1474,10 +1715,12 @@ static int __init vpe_module_init(void)
@@ -1473,10 +1714,12 @@ static int __init vpe_module_init(void)
mtflags = dmt();
vpflags = dvpe();
@ -1172,7 +1192,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
val = read_c0_mvpconf0();
hw_tcs = (val & MVPCONF0_PTC) + 1;
@@ -1489,6 +1732,7 @@ static int __init vpe_module_init(void)
@@ -1488,6 +1731,7 @@ static int __init vpe_module_init(void)
* reschedule send IPIs or similar we might hang.
*/
clear_c0_mvpcontrol(MVPCONTROL_VPC);
@ -1180,7 +1200,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
evpe(vpflags);
emt(mtflags);
local_irq_restore(flags);
@@ -1514,6 +1758,7 @@ static int __init vpe_module_init(void)
@@ -1513,6 +1757,7 @@ static int __init vpe_module_init(void)
}
v->ntcs = hw_tcs - tclimit;
@ -1188,7 +1208,7 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
/* add the tc to the list of this vpe's tc's. */
list_add(&t->tc, &v->tc);
@@ -1582,6 +1827,7 @@ static int __init vpe_module_init(void)
@@ -1581,6 +1826,7 @@ static int __init vpe_module_init(void)
out_reenable:
/* release config state */
clear_c0_mvpcontrol(MVPCONTROL_VPC);
@ -1196,3 +1216,6 @@ Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
evpe(vpflags);
emt(mtflags);
--
1.7.7.1

19
target/linux/lantiq/patches/0020-MIPS-lantiq-adds-falcon-VPE-softdog.patch → target/linux/lantiq/patches-3.2/0058-MIPS-lantiq-falcon-VPE-softdog.patch
View File

@ -1,7 +1,7 @@
From e3c377986855f820513edf2924a022a39c363908 Mon Sep 17 00:00:00 2001
From 6a76c0c9a33c32464319c24ff5647f7676642c51 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 29 Sep 2011 21:29:14 +0200
Subject: [PATCH 20/24] MIPS: lantiq: adds falcon VPE softdog
Subject: [PATCH 58/70] MIPS: lantiq: falcon VPE softdog
---
arch/mips/include/asm/mach-lantiq/falcon/vpe.h | 44 ++++++++++
@ -10,6 +10,9 @@ Subject: [PATCH 20/24] MIPS: lantiq: adds falcon VPE softdog
create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/vpe.h
create mode 100644 arch/mips/lantiq/falcon/softdog_vpe.c
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/vpe.h b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h
new file mode 100644
index 0000000..22a701b
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h
@@ -0,0 +1,44 @@
@ -57,6 +60,9 @@ Subject: [PATCH 20/24] MIPS: lantiq: adds falcon VPE softdog
+int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn);
+
+#endif
diff --git a/arch/mips/lantiq/falcon/softdog_vpe.c b/arch/mips/lantiq/falcon/softdog_vpe.c
new file mode 100644
index 0000000..85d22a2
--- /dev/null
+++ b/arch/mips/lantiq/falcon/softdog_vpe.c
@@ -0,0 +1,109 @@
@ -169,9 +175,6 @@ Subject: [PATCH 20/24] MIPS: lantiq: adds falcon VPE softdog
+MODULE_AUTHOR("LXDB");
+MODULE_DESCRIPTION("Software Watchdog For VPE1");
+MODULE_LICENSE("GPL");
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1,2 +1,2 @@
-obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
+obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o softdog_vpe.o
obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
--
1.7.7.1

31
target/linux/lantiq/patches/0022-MIPS-lantiq-adds-udp-in-kernel-redirect.patch → target/linux/lantiq/patches-3.2/0059-MIPS-lantiq-udp-in-kernel-redirect.patch
View File

@ -1,7 +1,7 @@
From 14ff975c660696fa636e8d6b58d0abed0ddc72ce Mon Sep 17 00:00:00 2001
From 268b631d81d5428cdf1a82b9655e9f44f64a8238 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 29 Sep 2011 20:29:54 +0200
Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
Subject: [PATCH 59/70] MIPS: lantiq: udp in-kernel redirect
---
include/linux/udp_redirect.h | 57 +++++++++++++
@ -13,6 +13,9 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
create mode 100644 include/linux/udp_redirect.h
create mode 100644 net/ipv4/udp_redirect_symb.c
diff --git a/include/linux/udp_redirect.h b/include/linux/udp_redirect.h
new file mode 100644
index 0000000..de1e64f
--- /dev/null
+++ b/include/linux/udp_redirect.h
@@ -0,0 +1,57 @@
@ -73,6 +76,8 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
+extern int udpredirect_getfrag(void *p, char * to, int offset,
+ int fraglen, int odd, struct sk_buff *skb);
+#endif
diff --git a/net/Kconfig b/net/Kconfig
index a073148..d13e3fa 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -72,6 +72,12 @@ config INET
@ -88,9 +93,11 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
if INET
source "net/ipv4/Kconfig"
source "net/ipv6/Kconfig"
diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile
index f2dc69c..6badd72 100644
--- a/net/ipv4/Makefile
+++ b/net/ipv4/Makefile
@@ -14,6 +14,9 @@ obj-y := route.o inetpeer.o protocol
@@ -14,6 +14,9 @@ obj-y := route.o inetpeer.o protocol.o \
inet_fragment.o ping.o
obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o
@ -100,6 +107,8 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o
obj-$(CONFIG_IP_MROUTE) += ipmr.o
diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c
index 5a65eea..cdfa0d4 100644
--- a/net/ipv4/udp.c
+++ b/net/ipv4/udp.c
@@ -108,6 +108,10 @@
@ -113,7 +122,7 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
struct udp_table udp_table __read_mostly;
EXPORT_SYMBOL(udp_table);
@@ -803,7 +807,7 @@ int udp_sendmsg(struct kiocb *iocb, stru
@@ -803,7 +807,7 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
u8 tos;
int err, is_udplite = IS_UDPLITE(sk);
int corkreq = up->corkflag || msg->msg_flags&MSG_MORE;
@ -122,7 +131,7 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
struct sk_buff *skb;
struct ip_options_data opt_copy;
@@ -820,7 +824,13 @@ int udp_sendmsg(struct kiocb *iocb, stru
@@ -820,7 +824,13 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
ipc.opt = NULL;
ipc.tx_flags = 0;
@ -137,7 +146,7 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
fl4 = &inet->cork.fl.u.ip4;
if (up->pending) {
@@ -1621,6 +1631,7 @@ int __udp4_lib_rcv(struct sk_buff *skb,
@@ -1623,6 +1633,7 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable,
struct rtable *rt = skb_rtable(skb);
__be32 saddr, daddr;
struct net *net = dev_net(skb->dev);
@ -145,7 +154,7 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
/*
* Validate the packet.
@@ -1653,7 +1664,16 @@ int __udp4_lib_rcv(struct sk_buff *skb,
@@ -1655,7 +1666,16 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable,
sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable);
if (sk != NULL) {
@ -163,7 +172,7 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
sock_put(sk);
/* a return value > 0 means to resubmit the input, but
@@ -1950,7 +1970,7 @@ struct proto udp_prot = {
@@ -1952,7 +1972,7 @@ struct proto udp_prot = {
.clear_sk = sk_prot_clear_portaddr_nulls,
};
EXPORT_SYMBOL(udp_prot);
@ -172,6 +181,9 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
/* ------------------------------------------------------------------------ */
#ifdef CONFIG_PROC_FS
diff --git a/net/ipv4/udp_redirect_symb.c b/net/ipv4/udp_redirect_symb.c
new file mode 100644
index 0000000..5617e86
--- /dev/null
+++ b/net/ipv4/udp_redirect_symb.c
@@ -0,0 +1,186 @@
@ -361,3 +373,6 @@ Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
+EXPORT_SYMBOL(udp_do_redirect_fn);
+EXPORT_SYMBOL(udpredirect_getfrag_fn);
+#endif /* CONFIG_IFX_UDP_REDIRECT* */
--
1.7.7.1

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