mirror of https://github.com/hak5/openwrt.git
113 lines
3.8 KiB
Diff
113 lines
3.8 KiB
Diff
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From 01aa1e11984ac4cd798308cd7a40c92fc4be214e Mon Sep 17 00:00:00 2001
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From: Daniel Matuschek <info@crazy-audio.com>
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Date: Wed, 15 Jan 2014 21:41:23 +0100
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Subject: [PATCH 156/174] ASoC: wm8804: Implement MCLK configuration options,
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add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs
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for most sample rates. At 192kHz only 128xfs is supported. The existing
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driver selects 128xfs automatically for some lower samples rates. By using an
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additional mclk_div divider, it is now possible to control the behaviour.
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This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It
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should allow lower jitter and better signal quality. The behavior has to be
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controlled by the sound card driver, because some sample frequency share the
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same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only
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difference is the MCLK divider.
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This also added support for 32bit data.
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Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
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---
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sound/soc/codecs/wm8804.c | 19 +++++++++++++++----
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sound/soc/codecs/wm8804.h | 4 ++++
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2 files changed, 19 insertions(+), 4 deletions(-)
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--- a/sound/soc/codecs/wm8804.c
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+++ b/sound/soc/codecs/wm8804.c
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@@ -63,6 +63,7 @@ struct wm8804_priv {
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struct regmap *regmap;
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struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
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struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
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+ int mclk_div;
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};
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static int txsrc_get(struct snd_kcontrol *kcontrol,
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@@ -277,6 +278,7 @@ static int wm8804_hw_params(struct snd_p
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blen = 0x1;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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+ case SNDRV_PCM_FORMAT_S32_LE:
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blen = 0x2;
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break;
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default:
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@@ -318,7 +320,7 @@ static struct {
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#define FIXED_PLL_SIZE ((1ULL << 22) * 10)
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static int pll_factors(struct pll_div *pll_div, unsigned int target,
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- unsigned int source)
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+ unsigned int source, unsigned int mclk_div)
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{
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u64 Kpart;
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unsigned long int K, Ndiv, Nmod, tmp;
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@@ -330,7 +332,8 @@ static int pll_factors(struct pll_div *p
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*/
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for (i = 0; i < ARRAY_SIZE(post_table); i++) {
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tmp = target * post_table[i].div;
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- if (tmp >= 90000000 && tmp <= 100000000) {
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+ if ((tmp >= 90000000 && tmp <= 100000000) &&
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+ (mclk_div == post_table[i].mclkdiv)) {
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pll_div->freqmode = post_table[i].freqmode;
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pll_div->mclkdiv = post_table[i].mclkdiv;
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target *= post_table[i].div;
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@@ -387,8 +390,11 @@ static int wm8804_set_pll(struct snd_soc
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} else {
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int ret;
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struct pll_div pll_div;
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+ struct wm8804_priv *wm8804;
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- ret = pll_factors(&pll_div, freq_out, freq_in);
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+ wm8804 = snd_soc_codec_get_drvdata(codec);
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+
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+ ret = pll_factors(&pll_div, freq_out, freq_in, wm8804->mclk_div);
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if (ret)
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return ret;
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@@ -452,6 +458,7 @@ static int wm8804_set_clkdiv(struct snd_
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int div_id, int div)
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{
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struct snd_soc_codec *codec;
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+ struct wm8804_priv *wm8804;
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codec = dai->codec;
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switch (div_id) {
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@@ -459,6 +466,10 @@ static int wm8804_set_clkdiv(struct snd_
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snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
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(div & 0x3) << 4);
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break;
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+ case WM8804_MCLK_DIV:
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+ wm8804 = snd_soc_codec_get_drvdata(codec);
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+ wm8804->mclk_div = div;
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+ break;
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default:
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dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
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return -EINVAL;
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@@ -641,7 +652,7 @@ static const struct snd_soc_dai_ops wm88
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};
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#define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
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- SNDRV_PCM_FMTBIT_S24_LE)
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+ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
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#define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
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--- a/sound/soc/codecs/wm8804.h
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+++ b/sound/soc/codecs/wm8804.h
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@@ -57,5 +57,9 @@
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#define WM8804_CLKOUT_SRC_OSCCLK 4
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#define WM8804_CLKOUT_DIV 1
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+#define WM8804_MCLK_DIV 2
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+
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+#define WM8804_MCLKDIV_256FS 0
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+#define WM8804_MCLKDIV_128FS 1
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#endif /* _WM8804_H */
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