2020-03-11 15:02:58 +00:00
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From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001
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From: Robert Jones <rjones@gateworks.com>
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Date: Wed, 8 Jan 2020 07:44:24 -0800
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Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support
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The Gateworks GW5912 is an IMX6 SoC based single board computer with:
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- IMX6Q or IMX6DL
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- 32bit DDR3 DRAM
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- GbE RJ45 front-panel
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- 4x miniPCIe socket with PCI Gen2, USB2
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- 1x miniPCIe socket with PCI Gen2, USB2, mSATA
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- 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
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- 10V to 60V DC input barrel jack
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- 3axis accelerometer (lis2de12)
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- GPS (ublox ZOE-M8Q)
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- bi-color front-panel LED
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- 256MB NAND boot device
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- nanoSIM/microSD socket (with UHS-I support)
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- user pushbutton
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- Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
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- CAN Bus transceiver (mcp2562)
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- RS232 transceiver (1x UART with flow-control or 2x UART (build option)
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- off-board SPI connector (1x chip-select)
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Signed-off-by: Robert Jones <rjones@gateworks.com>
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Reviewed-by: Tim Harvey <tharvey@gateworks.com>
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Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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---
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arch/arm/boot/dts/Makefile | 2 +
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arch/arm/boot/dts/imx6dl-gw5912.dts | 13 +
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arch/arm/boot/dts/imx6q-gw5912.dts | 13 +
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arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++
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4 files changed, 489 insertions(+)
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create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts
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create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts
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create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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2020-04-15 13:11:54 +00:00
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@@ -406,6 +406,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
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2020-03-11 15:02:58 +00:00
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imx6dl-gw5904.dtb \
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imx6dl-gw5907.dtb \
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imx6dl-gw5910.dtb \
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+ imx6dl-gw5912.dtb \
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imx6dl-gw5913.dtb \
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imx6dl-hummingboard.dtb \
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imx6dl-hummingboard-emmc-som-v15.dtb \
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2020-04-15 13:11:54 +00:00
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@@ -476,6 +477,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
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2020-03-11 15:02:58 +00:00
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imx6q-gw5904.dtb \
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imx6q-gw5907.dtb \
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imx6q-gw5910.dtb \
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+ imx6q-gw5912.dtb \
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imx6q-gw5913.dtb \
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imx6q-h100.dtb \
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imx6q-hummingboard.dtb \
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--- /dev/null
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+++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
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@@ -0,0 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright 2019 Gateworks Corporation
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+ */
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+
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+/dts-v1/;
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+#include "imx6dl.dtsi"
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+#include "imx6qdl-gw5912.dtsi"
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+
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+/ {
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+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
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+ compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/imx6q-gw5912.dts
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@@ -0,0 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright 2019 Gateworks Corporation
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+ */
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+
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+/dts-v1/;
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+#include "imx6q.dtsi"
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+#include "imx6qdl-gw5912.dtsi"
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+
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+/ {
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+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
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+ compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
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@@ -0,0 +1,461 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright 2019 Gateworks Corporation
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+ */
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ /* these are used by bootloader for disabling nodes */
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+ aliases {
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+ led0 = &led0;
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+ led1 = &led1;
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+ led2 = &led2;
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+ nand = &gpmi;
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+ usb0 = &usbh1;
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+ usb1 = &usbotg;
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+ };
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+
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+ chosen {
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+ stdout-path = &uart2;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_gpio_leds>;
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+
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+ led0: user1 {
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+ label = "user1";
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+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
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+ default-state = "on";
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+ linux,default-trigger = "heartbeat";
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+ };
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+
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+ led1: user2 {
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+ label = "user2";
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+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
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+ default-state = "off";
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+ };
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+
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+ led2: user3 {
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+ label = "user3";
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+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
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+ default-state = "off";
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+ };
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+ };
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+
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+ memory@10000000 {
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+ device_type = "memory";
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+ reg = <0x10000000 0x40000000>;
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+ };
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+
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+ pps {
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+ compatible = "pps-gpio";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pps>;
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+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "3P3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_usb_vbus: regulator-5p0v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-always-on;
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+ };
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+};
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+
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+&can1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_flexcan1>;
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+ status = "okay";
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+};
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+
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+&ecspi2 {
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+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_ecspi2>;
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+ status = "okay";
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+};
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+
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+&fec {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_enet>;
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+ phy-mode = "rgmii-id";
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+ status = "okay";
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+};
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+
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+&gpmi {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_gpmi_nand>;
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+ status = "okay";
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+};
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+
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+&i2c1 {
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+ clock-frequency = <100000>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c1>;
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+ status = "okay";
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+
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+ gpio@23 {
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+ compatible = "nxp,pca9555";
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+ reg = <0x23>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+
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+ eeprom@50 {
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+ compatible = "atmel,24c02";
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+ reg = <0x50>;
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+ pagesize = <16>;
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+ };
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+
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+ eeprom@51 {
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+ compatible = "atmel,24c02";
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+ reg = <0x51>;
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+ pagesize = <16>;
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+ };
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+
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+ eeprom@52 {
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+ compatible = "atmel,24c02";
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+ reg = <0x52>;
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+ pagesize = <16>;
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+ };
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+
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+ eeprom@53 {
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+ compatible = "atmel,24c02";
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+ reg = <0x53>;
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+ pagesize = <16>;
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+ };
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+
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+ rtc@68 {
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+ compatible = "dallas,ds1672";
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+ reg = <0x68>;
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+ };
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+};
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+
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+&i2c2 {
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+ clock-frequency = <100000>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c2>;
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+ status = "okay";
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+};
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+
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+&i2c3 {
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+ clock-frequency = <100000>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c3>;
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+ status = "okay";
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+
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+ accel@19 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_accel>;
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+ compatible = "st,lis2de12";
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+ reg = <0x19>;
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+ st,drdy-int-pin = <1>;
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+ interrupt-parent = <&gpio7>;
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+ interrupts = <13 0>;
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+ interrupt-names = "INT1";
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+ };
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+};
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+
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+&pcie {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pcie>;
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+ reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+};
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+
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+&pwm1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
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+ status = "disabled";
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+};
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+
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+&pwm2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
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+ status = "disabled";
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+};
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+
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+&pwm3 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
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+ status = "disabled";
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+};
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+
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+&pwm4 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
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+ status = "disabled";
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+};
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+
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+&uart1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_uart1>;
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+ rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_uart2>;
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+ status = "okay";
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+};
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+
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+&uart5 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_uart5>;
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+ status = "okay";
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+};
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+
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+&usbotg {
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+ vbus-supply = <®_usb_vbus>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_usbotg>;
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+ disable-over-current;
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+ dr_mode = "host";
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+ status = "okay";
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+};
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+
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+&usbh1 {
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+ vbus-supply = <®_usb_vbus>;
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+ status = "okay";
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+};
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+
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+&usdhc3 {
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+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
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+ pinctrl-0 = <&pinctrl_usdhc3>;
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+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
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+ vmmc-supply = <®_3p3v>;
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+ no-1-8-v; /* firmware will remove if board revision supports */
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+ status = "okay";
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+};
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+
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+&wdog1 {
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+ status = "disabled";
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+};
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+
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+&wdog2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_wdog>;
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+ fsl,ext-reset-output;
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+ status = "okay";
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+};
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+
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+&iomuxc {
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+ pinctrl_accel: accelmuxgrp {
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+ fsl,pins = <
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+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
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+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_enet: enetgrp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
|
|
|
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
|
|
|
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
|
|
|
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
|
|
|
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_ecspi2: escpi2grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
|
|
|
|
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
|
|
|
|
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
|
|
|
|
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_flexcan1: flexcan1grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
|
|
|
|
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
|
|
|
|
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_gpio_leds: gpioledsgrp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
|
|
|
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
|
|
|
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_gpmi_nand: gpminandgrp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
|
|
|
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
|
|
|
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
|
|
|
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
|
|
|
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_i2c1: i2c1grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
|
|
|
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
|
|
|
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_i2c2: i2c2grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
|
|
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_i2c3: i2c3grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
|
|
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_pcie: pciegrp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
|
|
|
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_pps: ppsgrp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_pwm1: pwm1grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_pwm2: pwm2grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_pwm3: pwm3grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_pwm4: pwm4grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_uart1: uart1grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
|
|
|
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
|
|
|
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_uart2: uart2grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
|
|
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
|
|
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_uart5: uart5grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
|
|
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_usbotg: usbotggrp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_usdhc3: usdhc3grp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
|
|
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
|
|
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
|
|
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
|
|
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
|
|
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
|
|
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
|
|
|
|
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
|
|
|
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
|
|
|
|
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
|
|
|
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
|
|
|
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
|
|
|
|
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ pinctrl_wdog: wdoggrp {
|
|
|
|
+ fsl,pins = <
|
|
|
|
+ MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
|
|
|
|
+ >;
|
|
|
|
+ };
|
|
|
|
+};
|