mirror of https://github.com/hak5/openwrt.git
59 lines
1.9 KiB
Diff
59 lines
1.9 KiB
Diff
|
From c1d35c42d697e9c28c817921a79c5f814529a4c6 Mon Sep 17 00:00:00 2001
|
||
|
|
From: John Crispin <blogic@openwrt.org>
|
||
|
|
Date: Sun, 14 Apr 2013 09:55:29 +0200
|
||
|
|
Subject: [PATCH 126/137] MIPS: ralink: add memory definition for MT7620
|
||
|
|
|
||
|
|
Populate struct soc_info with the data that describes our RAM window.
|
||
|
|
|
||
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||
|
|
Patchwork: http://patchwork.linux-mips.org/patch/5183/
|
||
|
|
---
|
||
|
|
arch/mips/include/asm/mach-ralink/mt7620.h | 8 ++++++++
|
||
|
|
arch/mips/ralink/mt7620.c | 20 ++++++++++++++++++++
|
||
|
|
2 files changed, 28 insertions(+)
|
||
|
|
|
||
|
|
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
|
||
|
|
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
|
||
|
|
@@ -50,6 +50,14 @@
|
||
|
|
#define SYSCFG0_DRAM_TYPE_DDR1 1
|
||
|
|
#define SYSCFG0_DRAM_TYPE_DDR2 2
|
||
|
|
|
||
|
|
+#define MT7620_DRAM_BASE 0x0
|
||
|
|
+#define MT7620_SDRAM_SIZE_MIN 2
|
||
|
|
+#define MT7620_SDRAM_SIZE_MAX 64
|
||
|
|
+#define MT7620_DDR1_SIZE_MIN 32
|
||
|
|
+#define MT7620_DDR1_SIZE_MAX 128
|
||
|
|
+#define MT7620_DDR2_SIZE_MIN 32
|
||
|
|
+#define MT7620_DDR2_SIZE_MAX 256
|
||
|
|
+
|
||
|
|
#define MT7620_GPIO_MODE_I2C BIT(0)
|
||
|
|
#define MT7620_GPIO_MODE_UART0_SHIFT 2
|
||
|
|
#define MT7620_GPIO_MODE_UART0_MASK 0x7
|
||
|
|
--- a/arch/mips/ralink/mt7620.c
|
||
|
|
+++ b/arch/mips/ralink/mt7620.c
|
||
|
|
@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_inf
|
||
|
|
|
||
|
|
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
|
||
|
|
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
|
||
|
|
+
|
||
|
|
+ switch (dram_type) {
|
||
|
|
+ case SYSCFG0_DRAM_TYPE_SDRAM:
|
||
|
|
+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
|
||
|
|
+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
|
||
|
|
+ break;
|
||
|
|
+
|
||
|
|
+ case SYSCFG0_DRAM_TYPE_DDR1:
|
||
|
|
+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
|
||
|
|
+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
|
||
|
|
+ break;
|
||
|
|
+
|
||
|
|
+ case SYSCFG0_DRAM_TYPE_DDR2:
|
||
|
|
+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
|
||
|
|
+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
|
||
|
|
+ break;
|
||
|
|
+ default:
|
||
|
|
+ BUG();
|
||
|
|
+ }
|
||
|
|
+ soc_info->mem_base = MT7620_DRAM_BASE;
|
||
|
|
}
|