mirror of https://github.com/hak5/openwrt.git
48 lines
1.4 KiB
Diff
48 lines
1.4 KiB
Diff
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From 845f786c561c0991d9b4088a2d77b8fd4831d487 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 22 Mar 2013 19:25:59 +0100
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Subject: [PATCH 103/137] MIPS: ralink: fix RT305x clock setup
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Add a few missing clocks.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5167/
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---
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arch/mips/ralink/rt305x.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
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void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
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+ unsigned long wmac_rate = 40000000;
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+
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u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
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if (soc_is_rt305x() || soc_is_rt3350()) {
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@@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
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BUG();
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}
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+ if (soc_is_rt3352() || soc_is_rt5350()) {
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+ u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
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+
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+ if (!(val & RT3352_CLKCFG0_XTAL_SEL))
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+ wmac_rate = 20000000;
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+ }
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+
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000100.timer", wdt_rate);
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+ ralink_clk_add("10000120.watchdog", wdt_rate);
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ralink_clk_add("10000500.uart", uart_rate);
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ralink_clk_add("10000c00.uartlite", uart_rate);
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+ ralink_clk_add("10100000.ethernet", sys_rate);
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+ ralink_clk_add("10180000.wmac", wmac_rate);
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}
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void __init ralink_of_remap(void)
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