mirror of https://github.com/hak5/openwrt.git
63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
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From cb86630379c8f3432c916d62045b5176f17f4123 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 16 Jul 2017 12:57:21 +0200
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Subject: [PATCH V2 6/8] MIPS: BCM63XX: move the HSSPI PLL HZ into its own
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clock
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Split up the HSSPL clock into rate and a gate clock, to more closely
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match the actual hardware.
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/bcm63xx/clk.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -248,6 +248,10 @@ static struct clk clk_hsspi = {
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.set = hsspi_set,
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};
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+/*
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+ * HSSPI PLL
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+ */
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+static struct clk clk_hsspi_pll;
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/*
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* XTM clock
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@@ -380,6 +384,7 @@ static struct clk_lookup bcm6328_clks[]
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CLKDEV_INIT(NULL, "periph", &clk_periph),
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CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
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CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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+ CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
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/* gated clocks */
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CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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@@ -447,6 +452,7 @@ static struct clk_lookup bcm6362_clks[]
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CLKDEV_INIT(NULL, "periph", &clk_periph),
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CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
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CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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+ CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
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/* gated clocks */
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CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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@@ -481,7 +487,7 @@ static int __init bcm63xx_clk_init(void)
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clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
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break;
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case BCM6328_CPU_ID:
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- clk_hsspi.rate = HSSPI_PLL_HZ_6328;
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+ clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
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clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
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break;
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case BCM6338_CPU_ID:
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@@ -497,7 +503,7 @@ static int __init bcm63xx_clk_init(void)
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clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
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break;
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case BCM6362_CPU_ID:
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- clk_hsspi.rate = HSSPI_PLL_HZ_6362;
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+ clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
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clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
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break;
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case BCM6368_CPU_ID:
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