mirror of https://github.com/hak5/openwrt.git
79 lines
2.9 KiB
Diff
79 lines
2.9 KiB
Diff
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--- a/drivers/net/ethernet/broadcom/bgmac.c
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+++ b/drivers/net/ethernet/broadcom/bgmac.c
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@@ -725,11 +725,9 @@ static void bgmac_phy_reset(struct bgmac
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if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
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return;
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- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
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- BGMAC_PHY_CTL_RESET);
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+ bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
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udelay(100);
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- if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
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- BGMAC_PHY_CTL_RESET)
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+ if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
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bgmac_err(bgmac, "PHY reset failed\n");
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bgmac_phy_init(bgmac);
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}
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@@ -1200,27 +1198,11 @@ static int bgmac_set_mac_address(struct
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static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
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{
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struct bgmac *bgmac = netdev_priv(net_dev);
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- struct mii_ioctl_data *data = if_mii(ifr);
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- switch (cmd) {
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- case SIOCGMIIPHY:
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- data->phy_id = bgmac->phyaddr;
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- /* fallthru */
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- case SIOCGMIIREG:
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- if (!netif_running(net_dev))
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- return -EAGAIN;
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- data->val_out = bgmac_phy_read(bgmac, data->phy_id,
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- data->reg_num & 0x1f);
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- return 0;
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- case SIOCSMIIREG:
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- if (!netif_running(net_dev))
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- return -EAGAIN;
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- bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
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- data->val_in);
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- return 0;
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- default:
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- return -EOPNOTSUPP;
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- }
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+ if (!netif_running(net_dev))
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+ return -EINVAL;
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+
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+ return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
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}
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static const struct net_device_ops bgmac_netdev_ops = {
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--- a/drivers/net/ethernet/broadcom/bgmac.h
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+++ b/drivers/net/ethernet/broadcom/bgmac.h
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@@ -220,27 +220,6 @@
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#define BGMAC_RX_STATUS 0xb38
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#define BGMAC_TX_STATUS 0xb3c
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-#define BGMAC_PHY_CTL 0x00
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-#define BGMAC_PHY_CTL_SPEED_MSB 0x0040
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-#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */
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-#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */
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-#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */
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-#define BGMAC_PHY_CTL_SPEED 0x2000
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-#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */
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-#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */
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-/* Helpers */
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-#define BGMAC_PHY_CTL_SPEED_10 0
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-#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED
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-#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB
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-#define BGMAC_PHY_ADV 0x04
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-#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */
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-#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */
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-#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */
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-#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */
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-#define BGMAC_PHY_ADV2 0x09
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-#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */
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-#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */
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-
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/* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
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#define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
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#define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
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