mirror of https://github.com/hak5/openwrt.git
1274 lines
39 KiB
Diff
1274 lines
39 KiB
Diff
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From 645c7805f2602569263d7ac78050b2c9e91e3377 Mon Sep 17 00:00:00 2001
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From: Ram Chandra Jangir <rjangir@codeaurora.org>
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Date: Thu, 20 Apr 2017 10:23:00 +0530
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Subject: [PATCH] qcom: mtd: nand: Added bam transaction and support
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additional CSRs
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This patch adds the following for NAND BAM DMA support
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- Bam transaction which will be used for any NAND request.
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It contains the array of command elements, command and
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data sgl. This transaction will be resetted before every
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request.
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- Allocation function for NAND BAM transaction which will be
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called only once at probe time.
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- Reset function for NAND BAM transaction which will be called
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before any new NAND request.
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- Add support for additional CSRs.
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NAND_READ_LOCATION - page offset for reading in BAM DMA mode
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NAND_ERASED_CW_DETECT_CFG - status for erased code words
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NAND_BUFFER_STATUS - status for ECC
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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---
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drivers/mtd/nand/qcom_nandc.c | 631 +++++++++++++++++++++++++++++++++++----
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include/linux/dma/qcom_bam_dma.h | 149 +++++++++
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2 files changed, 721 insertions(+), 59 deletions(-)
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create mode 100644 include/linux/dma/qcom_bam_dma.h
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diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
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index 76a0ffc..9d941e3 100644
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--- a/drivers/mtd/nand/qcom_nandc.c
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+++ b/drivers/mtd/nand/qcom_nandc.c
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@@ -22,6 +22,7 @@
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/delay.h>
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+#include <linux/dma/qcom_bam_dma.h>
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/* NANDc reg offsets */
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#define NAND_FLASH_CMD 0x00
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@@ -53,6 +54,8 @@
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#define NAND_VERSION 0xf08
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#define NAND_READ_LOCATION_0 0xf20
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#define NAND_READ_LOCATION_1 0xf24
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+#define NAND_READ_LOCATION_2 0xf28
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+#define NAND_READ_LOCATION_3 0xf2c
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/* dummy register offsets, used by write_reg_dma */
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#define NAND_DEV_CMD1_RESTORE 0xdead
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@@ -131,6 +134,11 @@
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#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
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#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
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+/* NAND_READ_LOCATION_n bits */
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+#define READ_LOCATION_OFFSET 0
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+#define READ_LOCATION_SIZE 16
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+#define READ_LOCATION_LAST 31
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+
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/* Version Mask */
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#define NAND_VERSION_MAJOR_MASK 0xf0000000
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#define NAND_VERSION_MAJOR_SHIFT 28
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@@ -148,6 +156,9 @@
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#define FETCH_ID 0xb
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#define RESET_DEVICE 0xd
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+/* NAND_CTRL bits */
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+#define BAM_MODE_EN BIT(0)
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+
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/*
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* the NAND controller performs reads/writes with ECC in 516 byte chunks.
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* the driver calls the chunks 'step' or 'codeword' interchangeably
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@@ -169,12 +180,77 @@
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#define ECC_BCH_4BIT BIT(2)
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#define ECC_BCH_8BIT BIT(3)
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+/* Flags used for BAM DMA desc preparation*/
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+/* Don't set the EOT in current tx sgl */
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+#define DMA_DESC_FLAG_NO_EOT (0x0001)
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+/* Set the NWD flag in current sgl */
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+#define DMA_DESC_FLAG_BAM_NWD (0x0002)
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+/* Close current sgl and start writing in another sgl */
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+#define DMA_DESC_FLAG_BAM_NEXT_SGL (0x0004)
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+/*
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+ * Erased codeword status is being used two times in single transfer so this
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+ * flag will determine the current value of erased codeword status register
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+ */
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+#define DMA_DESC_ERASED_CW_SET (0x0008)
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+
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+/* Returns the dma address for reg read buffer */
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+#define REG_BUF_DMA_ADDR(chip, vaddr) \
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+ ((chip)->reg_read_buf_phys + \
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+ ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
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+
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+/* Returns the nand register physical address */
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+#define NAND_REG_PHYS_ADDRESS(chip, addr) \
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+ ((chip)->base_dma + (addr))
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+
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+/* command element array size in bam transaction */
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+#define BAM_CMD_ELEMENT_SIZE (256)
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+/* command sgl size in bam transaction */
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+#define BAM_CMD_SGL_SIZE (256)
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+/* data sgl size in bam transaction */
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+#define BAM_DATA_SGL_SIZE (128)
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+
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+/*
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+ * This data type corresponds to the BAM transaction which will be used for any
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+ * nand request.
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+ * @bam_ce - the array of bam command elements
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+ * @cmd_sgl - sgl for nand bam command pipe
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+ * @tx_sgl - sgl for nand bam consumer pipe
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+ * @rx_sgl - sgl for nand bam producer pipe
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+ * @bam_ce_index - the index in bam_ce which is available for next sgl request
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+ * @pre_bam_ce_index - the index in bam_ce which marks the start position ce
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+ * for current sgl. It will be used for size calculation
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+ * for current sgl
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+ * @cmd_sgl_cnt - no of entries in command sgl.
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+ * @tx_sgl_cnt - no of entries in tx sgl.
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+ * @rx_sgl_cnt - no of entries in rx sgl.
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+ */
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+struct bam_transaction {
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+ struct bam_cmd_element bam_ce[BAM_CMD_ELEMENT_SIZE];
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+ struct qcom_bam_sgl cmd_sgl[BAM_CMD_SGL_SIZE];
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+ struct qcom_bam_sgl tx_sgl[BAM_DATA_SGL_SIZE];
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+ struct qcom_bam_sgl rx_sgl[BAM_DATA_SGL_SIZE];
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+ uint32_t bam_ce_index;
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+ uint32_t pre_bam_ce_index;
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+ uint32_t cmd_sgl_cnt;
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+ uint32_t tx_sgl_cnt;
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+ uint32_t rx_sgl_cnt;
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+};
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+
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+/**
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+ * This data type corresponds to the nand dma descriptor
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+ * @list - list for desc_info
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+ * @dir - DMA transfer direction
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+ * @sgl - sgl which will be used for single sgl dma descriptor
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+ * @dma_desc - low level dma engine descriptor
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+ * @bam_desc_data - used for bam desc mappings
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+ */
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struct desc_info {
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struct list_head node;
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enum dma_data_direction dir;
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struct scatterlist sgl;
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struct dma_async_tx_descriptor *dma_desc;
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+ struct qcom_bam_custom_data bam_desc_data;
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};
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/*
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@@ -202,6 +278,13 @@ struct nandc_regs {
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__le32 orig_vld;
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__le32 ecc_buf_cfg;
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+ __le32 read_location0;
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+ __le32 read_location1;
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+ __le32 read_location2;
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+ __le32 read_location3;
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+
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+ __le32 erased_cw_detect_cfg_clr;
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+ __le32 erased_cw_detect_cfg_set;
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};
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/*
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@@ -217,6 +300,7 @@ struct nandc_regs {
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* @aon_clk: another controller clock
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*
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* @chan: dma channel
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+ * @bam_txn: contains the bam transaction address
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* @cmd_crci: ADM DMA CRCI for command flow control
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* @data_crci: ADM DMA CRCI for data flow control
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* @desc_list: DMA descriptor list (list of desc_infos)
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@@ -242,6 +326,7 @@ struct nandc_regs {
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struct qcom_nand_controller {
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struct nand_hw_control controller;
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struct list_head host_list;
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+ struct bam_transaction *bam_txn;
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struct device *dev;
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@@ -342,6 +427,45 @@ struct qcom_nand_driver_data {
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bool dma_bam_enabled;
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};
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+/* Allocates and Initializes the BAM transaction */
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+struct bam_transaction *alloc_bam_transaction(
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+ struct qcom_nand_controller *nandc)
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+{
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+ struct bam_transaction *bam_txn;
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+
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+ bam_txn = kzalloc(sizeof(*bam_txn), GFP_KERNEL);
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+
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+ if (!bam_txn)
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+ return NULL;
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+
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+ bam_txn->bam_ce_index = 0;
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+ bam_txn->pre_bam_ce_index = 0;
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+ bam_txn->cmd_sgl_cnt = 0;
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+ bam_txn->tx_sgl_cnt = 0;
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+ bam_txn->rx_sgl_cnt = 0;
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+
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+ qcom_bam_sg_init_table(bam_txn->cmd_sgl, BAM_CMD_SGL_SIZE);
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+ qcom_bam_sg_init_table(bam_txn->tx_sgl, BAM_DATA_SGL_SIZE);
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+ qcom_bam_sg_init_table(bam_txn->rx_sgl, BAM_DATA_SGL_SIZE);
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+
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+ return bam_txn;
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+}
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+
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+/* Clears the BAM transaction index */
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+void clear_bam_transaction(struct qcom_nand_controller *nandc)
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+{
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+ struct bam_transaction *bam_txn = nandc->bam_txn;
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+
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+ if (!nandc->dma_bam_enabled)
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+ return;
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+
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+ bam_txn->bam_ce_index = 0;
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+ bam_txn->pre_bam_ce_index = 0;
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+ bam_txn->cmd_sgl_cnt = 0;
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+ bam_txn->tx_sgl_cnt = 0;
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+ bam_txn->rx_sgl_cnt = 0;
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+}
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+
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static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
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{
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return container_of(chip, struct qcom_nand_host, chip);
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@@ -398,6 +522,16 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
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return ®s->orig_vld;
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case NAND_EBI2_ECC_BUF_CFG:
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return ®s->ecc_buf_cfg;
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+ case NAND_BUFFER_STATUS:
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+ return ®s->clrreadstatus;
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+ case NAND_READ_LOCATION_0:
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+ return ®s->read_location0;
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+ case NAND_READ_LOCATION_1:
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+ return ®s->read_location1;
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+ case NAND_READ_LOCATION_2:
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+ return ®s->read_location2;
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+ case NAND_READ_LOCATION_3:
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+ return ®s->read_location3;
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default:
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return NULL;
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}
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@@ -439,7 +573,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
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{
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struct nand_chip *chip = &host->chip;
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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- u32 cmd, cfg0, cfg1, ecc_bch_cfg;
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+ u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
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if (read) {
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if (host->use_ecc)
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@@ -456,12 +590,20 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
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cfg1 = host->cfg1;
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ecc_bch_cfg = host->ecc_bch_cfg;
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+ if (read)
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+ read_location0 = (0 << READ_LOCATION_OFFSET) |
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+ (host->cw_data << READ_LOCATION_SIZE) |
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+ (1 << READ_LOCATION_LAST);
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} else {
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cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
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(num_cw - 1) << CW_PER_PAGE;
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cfg1 = host->cfg1_raw;
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ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
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+ if (read)
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+ read_location0 = (0 << READ_LOCATION_OFFSET) |
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+ (host->cw_size << READ_LOCATION_SIZE) |
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+ (1 << READ_LOCATION_LAST);
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}
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nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
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@@ -472,8 +614,104 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
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nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
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nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
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nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
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+
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+ if (read)
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+ nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
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}
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+/*
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+ * Prepares the command descriptor for BAM DMA which will be used for NAND
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+ * register read and write. The command descriptor requires the command
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+ * to be formed in command element type so this function uses the command
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+ * element from bam transaction ce array and fills the same with required
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+ * data. A single SGL can contain multiple command elements so
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+ * DMA_DESC_FLAG_BAM_NEXT_SGL will be used for starting the separate SGL
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+ * after the current command element.
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+ */
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+static int prep_dma_desc_command(struct qcom_nand_controller *nandc, bool read,
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+ int reg_off, const void *vaddr,
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+ int size, unsigned int flags)
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+{
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+ int bam_ce_size;
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+ int i;
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+ struct bam_cmd_element *bam_ce_buffer;
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+ struct bam_transaction *bam_txn = nandc->bam_txn;
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+
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+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_index];
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+
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+ /* fill the command desc */
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+ for (i = 0; i < size; i++) {
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+ if (read) {
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+ qcom_prep_bam_ce(&bam_ce_buffer[i],
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+ NAND_REG_PHYS_ADDRESS(nandc, reg_off + 4 * i),
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+ BAM_READ_COMMAND,
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+ REG_BUF_DMA_ADDR(nandc,
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+ (unsigned int *)vaddr + i));
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+ } else {
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+ qcom_prep_bam_ce(&bam_ce_buffer[i],
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+ NAND_REG_PHYS_ADDRESS(nandc, reg_off + 4 * i),
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+ BAM_WRITE_COMMAND,
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+ *((unsigned int *)vaddr + i));
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+ }
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+ }
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+
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+ /* use the separate sgl after this command */
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+ if (flags & DMA_DESC_FLAG_BAM_NEXT_SGL) {
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+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->pre_bam_ce_index];
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+ bam_txn->bam_ce_index += size;
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+ bam_ce_size = (bam_txn->bam_ce_index -
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+ bam_txn->pre_bam_ce_index) *
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+ sizeof(struct bam_cmd_element);
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+ sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_cnt].sgl,
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+ bam_ce_buffer,
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+ bam_ce_size);
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+ if (flags & DMA_DESC_FLAG_BAM_NWD)
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+ bam_txn->cmd_sgl[bam_txn->cmd_sgl_cnt].dma_flags =
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+ DESC_FLAG_NWD | DESC_FLAG_CMD;
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+ else
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+ bam_txn->cmd_sgl[bam_txn->cmd_sgl_cnt].dma_flags =
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+ DESC_FLAG_CMD;
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+
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+ bam_txn->cmd_sgl_cnt++;
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+ bam_txn->pre_bam_ce_index = bam_txn->bam_ce_index;
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+ } else {
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+ bam_txn->bam_ce_index += size;
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+ }
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+
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+ return 0;
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+}
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+
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+/*
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+ * Prepares the data descriptor for BAM DMA which will be used for NAND
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+ * data read and write.
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+ */
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+static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, bool read,
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+ int reg_off, const void *vaddr,
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+ int size, unsigned int flags)
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+{
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+ struct bam_transaction *bam_txn = nandc->bam_txn;
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+
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+ if (read) {
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+ sg_set_buf(&bam_txn->rx_sgl[bam_txn->rx_sgl_cnt].sgl,
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+ vaddr, size);
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||
|
+ bam_txn->rx_sgl[bam_txn->rx_sgl_cnt].dma_flags = 0;
|
||
|
+ bam_txn->rx_sgl_cnt++;
|
||
|
+ } else {
|
||
|
+ sg_set_buf(&bam_txn->tx_sgl[bam_txn->tx_sgl_cnt].sgl,
|
||
|
+ vaddr, size);
|
||
|
+ if (flags & DMA_DESC_FLAG_NO_EOT)
|
||
|
+ bam_txn->tx_sgl[bam_txn->tx_sgl_cnt].dma_flags = 0;
|
||
|
+ else
|
||
|
+ bam_txn->tx_sgl[bam_txn->tx_sgl_cnt].dma_flags =
|
||
|
+ DESC_FLAG_EOT;
|
||
|
+
|
||
|
+ bam_txn->tx_sgl_cnt++;
|
||
|
+ }
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+/* Prepares the dma desciptor for adm dma engine */
|
||
|
static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
|
||
|
int reg_off, const void *vaddr, int size,
|
||
|
bool flow_control)
|
||
|
@@ -552,7 +790,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
|
||
|
* @num_regs: number of registers to read
|
||
|
*/
|
||
|
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
|
||
|
- int num_regs)
|
||
|
+ int num_regs, unsigned int flags)
|
||
|
{
|
||
|
bool flow_control = false;
|
||
|
void *vaddr;
|
||
|
@@ -561,10 +799,18 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
|
||
|
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
|
||
|
flow_control = true;
|
||
|
|
||
|
- size = num_regs * sizeof(u32);
|
||
|
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
|
||
|
nandc->reg_read_pos += num_regs;
|
||
|
|
||
|
+ if (nandc->dma_bam_enabled) {
|
||
|
+ size = num_regs;
|
||
|
+
|
||
|
+ return prep_dma_desc_command(nandc, true, first, vaddr, size,
|
||
|
+ flags);
|
||
|
+ }
|
||
|
+
|
||
|
+ size = num_regs * sizeof(u32);
|
||
|
+
|
||
|
return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
|
||
|
}
|
||
|
|
||
|
@@ -576,7 +822,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
|
||
|
* @num_regs: number of registers to write
|
||
|
*/
|
||
|
static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
|
||
|
- int num_regs)
|
||
|
+ int num_regs, unsigned int flags)
|
||
|
{
|
||
|
bool flow_control = false;
|
||
|
struct nandc_regs *regs = nandc->regs;
|
||
|
@@ -588,12 +834,29 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
|
||
|
if (first == NAND_FLASH_CMD)
|
||
|
flow_control = true;
|
||
|
|
||
|
+ if (first == NAND_ERASED_CW_DETECT_CFG) {
|
||
|
+ if (flags & DMA_DESC_ERASED_CW_SET)
|
||
|
+ vaddr = ®s->erased_cw_detect_cfg_set;
|
||
|
+ else
|
||
|
+ vaddr = ®s->erased_cw_detect_cfg_clr;
|
||
|
+ }
|
||
|
+
|
||
|
+ if (first == NAND_EXEC_CMD)
|
||
|
+ flags |= DMA_DESC_FLAG_BAM_NWD;
|
||
|
+
|
||
|
if (first == NAND_DEV_CMD1_RESTORE)
|
||
|
first = NAND_DEV_CMD1;
|
||
|
|
||
|
if (first == NAND_DEV_CMD_VLD_RESTORE)
|
||
|
first = NAND_DEV_CMD_VLD;
|
||
|
|
||
|
+ if (nandc->dma_bam_enabled) {
|
||
|
+ size = num_regs;
|
||
|
+
|
||
|
+ return prep_dma_desc_command(nandc, false, first, vaddr, size,
|
||
|
+ flags);
|
||
|
+ }
|
||
|
+
|
||
|
size = num_regs * sizeof(u32);
|
||
|
|
||
|
return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
|
||
|
@@ -608,8 +871,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
|
||
|
* @size: DMA transaction size in bytes
|
||
|
*/
|
||
|
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||
|
- const u8 *vaddr, int size)
|
||
|
+ const u8 *vaddr, int size, unsigned int flags)
|
||
|
{
|
||
|
+ if (nandc->dma_bam_enabled)
|
||
|
+ return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
|
||
|
+ flags);
|
||
|
+
|
||
|
return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
|
||
|
}
|
||
|
|
||
|
@@ -622,8 +889,12 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||
|
* @size: DMA transaction size in bytes
|
||
|
*/
|
||
|
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||
|
- const u8 *vaddr, int size)
|
||
|
+ const u8 *vaddr, int size, unsigned int flags)
|
||
|
{
|
||
|
+ if (nandc->dma_bam_enabled)
|
||
|
+ return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
|
||
|
+ size, flags);
|
||
|
+
|
||
|
return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
|
||
|
}
|
||
|
|
||
|
@@ -633,14 +904,57 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
|
||
|
*/
|
||
|
static void config_cw_read(struct qcom_nand_controller *nandc)
|
||
|
{
|
||
|
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
|
||
|
- write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
|
||
|
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
|
||
|
|
||
|
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
|
||
|
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
|
||
|
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
|
||
|
+
|
||
|
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
|
||
|
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
|
||
|
+ DMA_DESC_ERASED_CW_SET);
|
||
|
+ if (nandc->dma_bam_enabled)
|
||
|
+ write_reg_dma(nandc, NAND_READ_LOCATION_0, 1,
|
||
|
+ DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+
|
||
|
|
||
|
- read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
|
||
|
- read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
|
||
|
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NWD |
|
||
|
+ DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+
|
||
|
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
|
||
|
+ read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
|
||
|
+ DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+}
|
||
|
+
|
||
|
+/*
|
||
|
+ * Helpers to prepare DMA descriptors for configuring registers
|
||
|
+ * before reading a NAND page with BAM.
|
||
|
+ */
|
||
|
+static void config_bam_page_read(struct qcom_nand_controller *nandc)
|
||
|
+{
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
|
||
|
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
|
||
|
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
|
||
|
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
|
||
|
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
|
||
|
+ DMA_DESC_ERASED_CW_SET |
|
||
|
+ DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+}
|
||
|
+
|
||
|
+/*
|
||
|
+ * Helpers to prepare DMA descriptors for configuring registers
|
||
|
+ * before reading each codeword in NAND page with BAM.
|
||
|
+ */
|
||
|
+static void config_bam_cw_read(struct qcom_nand_controller *nandc)
|
||
|
+{
|
||
|
+ if (nandc->dma_bam_enabled)
|
||
|
+ write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, 0);
|
||
|
+
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+
|
||
|
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
|
||
|
+ read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
|
||
|
+ DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
@@ -649,19 +963,20 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
|
||
|
*/
|
||
|
static void config_cw_write_pre(struct qcom_nand_controller *nandc)
|
||
|
{
|
||
|
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
|
||
|
- write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
|
||
|
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
|
||
|
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
|
||
|
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
|
||
|
+ DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
}
|
||
|
|
||
|
static void config_cw_write_post(struct qcom_nand_controller *nandc)
|
||
|
{
|
||
|
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
|
||
|
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
|
||
|
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
- write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
|
||
|
- write_reg_dma(nandc, NAND_READ_STATUS, 1);
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
|
||
|
+ write_reg_dma(nandc, NAND_READ_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
@@ -675,6 +990,8 @@ static int nandc_param(struct qcom_nand_host *host)
|
||
|
struct nand_chip *chip = &host->chip;
|
||
|
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||
|
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
+
|
||
|
/*
|
||
|
* NAND_CMD_PARAM is called before we know much about the FLASH chip
|
||
|
* in use. we configure the controller to perform a raw read of 512
|
||
|
@@ -708,9 +1025,13 @@ static int nandc_param(struct qcom_nand_host *host)
|
||
|
|
||
|
nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
|
||
|
nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0,
|
||
|
+ (0 << READ_LOCATION_OFFSET) |
|
||
|
+ (512 << READ_LOCATION_SIZE) |
|
||
|
+ (1 << READ_LOCATION_LAST));
|
||
|
|
||
|
- write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
|
||
|
- write_reg_dma(nandc, NAND_DEV_CMD1, 1);
|
||
|
+ write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
|
||
|
+ write_reg_dma(nandc, NAND_DEV_CMD1, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
nandc->buf_count = 512;
|
||
|
memset(nandc->data_buffer, 0xff, nandc->buf_count);
|
||
|
@@ -718,11 +1039,12 @@ static int nandc_param(struct qcom_nand_host *host)
|
||
|
config_cw_read(nandc);
|
||
|
|
||
|
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
|
||
|
- nandc->buf_count);
|
||
|
+ nandc->buf_count, 0);
|
||
|
|
||
|
/* restore CMD1 and VLD regs */
|
||
|
- write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
|
||
|
- write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
|
||
|
+ write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
|
||
|
+ write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1,
|
||
|
+ DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -733,6 +1055,8 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
|
||
|
struct nand_chip *chip = &host->chip;
|
||
|
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||
|
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
+
|
||
|
nandc_set_reg(nandc, NAND_FLASH_CMD,
|
||
|
BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
|
||
|
nandc_set_reg(nandc, NAND_ADDR0, page_addr);
|
||
|
@@ -744,14 +1068,15 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
|
||
|
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
|
||
|
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
|
||
|
|
||
|
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
|
||
|
- write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
|
||
|
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
|
||
|
|
||
|
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_CMD, 3, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 2, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
- write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
|
||
|
- write_reg_dma(nandc, NAND_READ_STATUS, 1);
|
||
|
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
|
||
|
+ write_reg_dma(nandc, NAND_READ_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -765,16 +1090,19 @@ static int read_id(struct qcom_nand_host *host, int column)
|
||
|
if (column == -1)
|
||
|
return 0;
|
||
|
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
+
|
||
|
nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
|
||
|
nandc_set_reg(nandc, NAND_ADDR0, column);
|
||
|
nandc_set_reg(nandc, NAND_ADDR1, 0);
|
||
|
- nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
|
||
|
+ nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
|
||
|
+ nandc->dma_bam_enabled ? 0 : DM_EN);
|
||
|
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
|
||
|
|
||
|
- write_reg_dma(nandc, NAND_FLASH_CMD, 4);
|
||
|
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_CMD, 4, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
- read_reg_dma(nandc, NAND_READ_ID, 1);
|
||
|
+ read_reg_dma(nandc, NAND_READ_ID, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -785,15 +1113,61 @@ static int reset(struct qcom_nand_host *host)
|
||
|
struct nand_chip *chip = &host->chip;
|
||
|
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||
|
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
+
|
||
|
nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
|
||
|
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
|
||
|
|
||
|
- write_reg_dma(nandc, NAND_FLASH_CMD, 1);
|
||
|
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
|
||
|
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+
|
||
|
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
|
||
|
+ struct dma_chan *chan,
|
||
|
+ struct qcom_bam_sgl *bam_sgl,
|
||
|
+ int sgl_cnt,
|
||
|
+ enum dma_transfer_direction direction)
|
||
|
+{
|
||
|
+ struct desc_info *desc;
|
||
|
+ struct dma_async_tx_descriptor *dma_desc;
|
||
|
+
|
||
|
+ if (!qcom_bam_map_sg(nandc->dev, bam_sgl, sgl_cnt, direction)) {
|
||
|
+ dev_err(nandc->dev, "failure in mapping sgl\n");
|
||
|
+ return -ENOMEM;
|
||
|
+ }
|
||
|
+
|
||
|
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
|
||
|
+ if (!desc) {
|
||
|
+ qcom_bam_unmap_sg(nandc->dev, bam_sgl, sgl_cnt, direction);
|
||
|
+ return -ENOMEM;
|
||
|
+ }
|
||
|
+
|
||
|
+
|
||
|
+ desc->bam_desc_data.dir = direction;
|
||
|
+ desc->bam_desc_data.sgl_cnt = sgl_cnt;
|
||
|
+ desc->bam_desc_data.bam_sgl = bam_sgl;
|
||
|
+
|
||
|
+ dma_desc = dmaengine_prep_dma_custom_mapping(chan,
|
||
|
+ &desc->bam_desc_data,
|
||
|
+ 0);
|
||
|
+
|
||
|
+ if (!dma_desc) {
|
||
|
+ dev_err(nandc->dev, "failure in cmd prep desc\n");
|
||
|
+ qcom_bam_unmap_sg(nandc->dev, bam_sgl, sgl_cnt, direction);
|
||
|
+ kfree(desc);
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+
|
||
|
+ desc->dma_desc = dma_desc;
|
||
|
|
||
|
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
|
||
|
+ list_add_tail(&desc->node, &nandc->desc_list);
|
||
|
|
||
|
return 0;
|
||
|
+
|
||
|
}
|
||
|
|
||
|
/* helpers to submit/free our list of dma descriptors */
|
||
|
@@ -801,12 +1175,46 @@ static int submit_descs(struct qcom_nand_controller *nandc)
|
||
|
{
|
||
|
struct desc_info *desc;
|
||
|
dma_cookie_t cookie = 0;
|
||
|
+ struct bam_transaction *bam_txn = nandc->bam_txn;
|
||
|
+ int r;
|
||
|
+
|
||
|
+ if (nandc->dma_bam_enabled) {
|
||
|
+ if (bam_txn->rx_sgl_cnt) {
|
||
|
+ r = prepare_bam_async_desc(nandc, nandc->rx_chan,
|
||
|
+ bam_txn->rx_sgl, bam_txn->rx_sgl_cnt,
|
||
|
+ DMA_DEV_TO_MEM);
|
||
|
+ if (r)
|
||
|
+ return r;
|
||
|
+ }
|
||
|
+
|
||
|
+ if (bam_txn->tx_sgl_cnt) {
|
||
|
+ r = prepare_bam_async_desc(nandc, nandc->tx_chan,
|
||
|
+ bam_txn->tx_sgl, bam_txn->tx_sgl_cnt,
|
||
|
+ DMA_MEM_TO_DEV);
|
||
|
+ if (r)
|
||
|
+ return r;
|
||
|
+ }
|
||
|
+
|
||
|
+ r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
|
||
|
+ bam_txn->cmd_sgl, bam_txn->cmd_sgl_cnt,
|
||
|
+ DMA_MEM_TO_DEV);
|
||
|
+ if (r)
|
||
|
+ return r;
|
||
|
+ }
|
||
|
|
||
|
list_for_each_entry(desc, &nandc->desc_list, node)
|
||
|
cookie = dmaengine_submit(desc->dma_desc);
|
||
|
|
||
|
- if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
|
||
|
- return -ETIMEDOUT;
|
||
|
+ if (nandc->dma_bam_enabled) {
|
||
|
+ dma_async_issue_pending(nandc->tx_chan);
|
||
|
+ dma_async_issue_pending(nandc->rx_chan);
|
||
|
+
|
||
|
+ if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
|
||
|
+ return -ETIMEDOUT;
|
||
|
+ } else {
|
||
|
+ if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
|
||
|
+ return -ETIMEDOUT;
|
||
|
+ }
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -817,7 +1225,16 @@ static void free_descs(struct qcom_nand_controller *nandc)
|
||
|
|
||
|
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
|
||
|
list_del(&desc->node);
|
||
|
- dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
|
||
|
+
|
||
|
+ if (nandc->dma_bam_enabled)
|
||
|
+ qcom_bam_unmap_sg(nandc->dev,
|
||
|
+ desc->bam_desc_data.bam_sgl,
|
||
|
+ desc->bam_desc_data.sgl_cnt,
|
||
|
+ desc->bam_desc_data.dir);
|
||
|
+ else
|
||
|
+ dma_unmap_sg(nandc->dev, &desc->sgl, 1,
|
||
|
+ desc->dir);
|
||
|
+
|
||
|
kfree(desc);
|
||
|
}
|
||
|
}
|
||
|
@@ -1128,6 +1545,9 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
|
||
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||
|
int i, ret;
|
||
|
|
||
|
+ if (nandc->dma_bam_enabled)
|
||
|
+ config_bam_page_read(nandc);
|
||
|
+
|
||
|
/* queue cmd descs for each codeword */
|
||
|
for (i = 0; i < ecc->steps; i++) {
|
||
|
int data_size, oob_size;
|
||
|
@@ -1141,11 +1561,36 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
|
||
|
oob_size = host->ecc_bytes_hw + host->spare_bytes;
|
||
|
}
|
||
|
|
||
|
- config_cw_read(nandc);
|
||
|
+ if (nandc->dma_bam_enabled) {
|
||
|
+ if (data_buf && oob_buf) {
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0,
|
||
|
+ (0 << READ_LOCATION_OFFSET) |
|
||
|
+ (data_size << READ_LOCATION_SIZE) |
|
||
|
+ (0 << READ_LOCATION_LAST));
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_1,
|
||
|
+ (data_size << READ_LOCATION_OFFSET) |
|
||
|
+ (oob_size << READ_LOCATION_SIZE) |
|
||
|
+ (1 << READ_LOCATION_LAST));
|
||
|
+ } else if (data_buf) {
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0,
|
||
|
+ (0 << READ_LOCATION_OFFSET) |
|
||
|
+ (data_size << READ_LOCATION_SIZE) |
|
||
|
+ (1 << READ_LOCATION_LAST));
|
||
|
+ } else {
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0,
|
||
|
+ (data_size << READ_LOCATION_OFFSET) |
|
||
|
+ (oob_size << READ_LOCATION_SIZE) |
|
||
|
+ (1 << READ_LOCATION_LAST));
|
||
|
+ }
|
||
|
+
|
||
|
+ config_bam_cw_read(nandc);
|
||
|
+ } else {
|
||
|
+ config_cw_read(nandc);
|
||
|
+ }
|
||
|
|
||
|
if (data_buf)
|
||
|
read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
|
||
|
- data_size);
|
||
|
+ data_size, 0);
|
||
|
|
||
|
/*
|
||
|
* when ecc is enabled, the controller doesn't read the real
|
||
|
@@ -1161,7 +1606,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
|
||
|
*oob_buf++ = 0xff;
|
||
|
|
||
|
read_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||
|
- oob_buf, oob_size);
|
||
|
+ oob_buf, oob_size, 0);
|
||
|
}
|
||
|
|
||
|
if (data_buf)
|
||
|
@@ -1200,10 +1645,14 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
|
||
|
|
||
|
set_address(host, host->cw_size * (ecc->steps - 1), page);
|
||
|
update_rw_regs(host, 1, true);
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0,
|
||
|
+ (0 << READ_LOCATION_OFFSET) |
|
||
|
+ (size << READ_LOCATION_SIZE) |
|
||
|
+ (1 << READ_LOCATION_LAST));
|
||
|
|
||
|
config_cw_read(nandc);
|
||
|
|
||
|
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
|
||
|
+ read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
|
||
|
|
||
|
ret = submit_descs(nandc);
|
||
|
if (ret)
|
||
|
@@ -1226,6 +1675,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||
|
data_buf = buf;
|
||
|
oob_buf = oob_required ? chip->oob_poi : NULL;
|
||
|
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
ret = read_page_ecc(host, data_buf, oob_buf);
|
||
|
if (ret) {
|
||
|
dev_err(nandc->dev, "failure to read page\n");
|
||
|
@@ -1245,13 +1695,19 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
|
||
|
u8 *data_buf, *oob_buf;
|
||
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||
|
int i, ret;
|
||
|
+ int read_location;
|
||
|
|
||
|
data_buf = buf;
|
||
|
oob_buf = chip->oob_poi;
|
||
|
|
||
|
host->use_ecc = false;
|
||
|
+
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
update_rw_regs(host, ecc->steps, true);
|
||
|
|
||
|
+ if (nandc->dma_bam_enabled)
|
||
|
+ config_bam_page_read(nandc);
|
||
|
+
|
||
|
for (i = 0; i < ecc->steps; i++) {
|
||
|
int data_size1, data_size2, oob_size1, oob_size2;
|
||
|
int reg_off = FLASH_BUF_ACC;
|
||
|
@@ -1269,21 +1725,49 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
|
||
|
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
|
||
|
}
|
||
|
|
||
|
- config_cw_read(nandc);
|
||
|
+ if (nandc->dma_bam_enabled) {
|
||
|
+ read_location = 0;
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0,
|
||
|
+ (read_location << READ_LOCATION_OFFSET) |
|
||
|
+ (data_size1 << READ_LOCATION_SIZE) |
|
||
|
+ (0 << READ_LOCATION_LAST));
|
||
|
+ read_location += data_size1;
|
||
|
+
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_1,
|
||
|
+ (read_location << READ_LOCATION_OFFSET) |
|
||
|
+ (oob_size1 << READ_LOCATION_SIZE) |
|
||
|
+ (0 << READ_LOCATION_LAST));
|
||
|
+ read_location += oob_size1;
|
||
|
+
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_2,
|
||
|
+ (read_location << READ_LOCATION_OFFSET) |
|
||
|
+ (data_size2 << READ_LOCATION_SIZE) |
|
||
|
+ (0 << READ_LOCATION_LAST));
|
||
|
+ read_location += data_size2;
|
||
|
+
|
||
|
+ nandc_set_reg(nandc, NAND_READ_LOCATION_3,
|
||
|
+ (read_location << READ_LOCATION_OFFSET) |
|
||
|
+ (oob_size2 << READ_LOCATION_SIZE) |
|
||
|
+ (1 << READ_LOCATION_LAST));
|
||
|
+
|
||
|
+ config_bam_cw_read(nandc);
|
||
|
+ } else {
|
||
|
+ config_cw_read(nandc);
|
||
|
+ }
|
||
|
|
||
|
- read_data_dma(nandc, reg_off, data_buf, data_size1);
|
||
|
+ read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
|
||
|
reg_off += data_size1;
|
||
|
data_buf += data_size1;
|
||
|
|
||
|
- read_data_dma(nandc, reg_off, oob_buf, oob_size1);
|
||
|
+ read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
|
||
|
reg_off += oob_size1;
|
||
|
oob_buf += oob_size1;
|
||
|
|
||
|
- read_data_dma(nandc, reg_off, data_buf, data_size2);
|
||
|
+ read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
|
||
|
reg_off += data_size2;
|
||
|
data_buf += data_size2;
|
||
|
|
||
|
- read_data_dma(nandc, reg_off, oob_buf, oob_size2);
|
||
|
+ read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
|
||
|
oob_buf += oob_size2;
|
||
|
}
|
||
|
|
||
|
@@ -1306,6 +1790,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
|
||
|
int ret;
|
||
|
|
||
|
clear_read_regs(nandc);
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
|
||
|
host->use_ecc = true;
|
||
|
set_address(host, 0, page);
|
||
|
@@ -1329,6 +1814,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||
|
int i, ret;
|
||
|
|
||
|
clear_read_regs(nandc);
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
|
||
|
data_buf = (u8 *)buf;
|
||
|
oob_buf = chip->oob_poi;
|
||
|
@@ -1350,7 +1836,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||
|
|
||
|
config_cw_write_pre(nandc);
|
||
|
|
||
|
- write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
|
||
|
+ write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
|
||
|
+ i == (ecc->steps - 1) ? DMA_DESC_FLAG_NO_EOT : 0);
|
||
|
|
||
|
/*
|
||
|
* when ECC is enabled, we don't really need to write anything
|
||
|
@@ -1363,7 +1850,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||
|
oob_buf += host->bbm_size;
|
||
|
|
||
|
write_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||
|
- oob_buf, oob_size);
|
||
|
+ oob_buf, oob_size, 0);
|
||
|
}
|
||
|
|
||
|
config_cw_write_post(nandc);
|
||
|
@@ -1393,6 +1880,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
|
||
|
int i, ret;
|
||
|
|
||
|
clear_read_regs(nandc);
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
|
||
|
data_buf = (u8 *)buf;
|
||
|
oob_buf = chip->oob_poi;
|
||
|
@@ -1419,19 +1907,22 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
|
||
|
|
||
|
config_cw_write_pre(nandc);
|
||
|
|
||
|
- write_data_dma(nandc, reg_off, data_buf, data_size1);
|
||
|
+ write_data_dma(nandc, reg_off, data_buf, data_size1,
|
||
|
+ DMA_DESC_FLAG_NO_EOT);
|
||
|
reg_off += data_size1;
|
||
|
data_buf += data_size1;
|
||
|
|
||
|
- write_data_dma(nandc, reg_off, oob_buf, oob_size1);
|
||
|
+ write_data_dma(nandc, reg_off, oob_buf, oob_size1,
|
||
|
+ DMA_DESC_FLAG_NO_EOT);
|
||
|
reg_off += oob_size1;
|
||
|
oob_buf += oob_size1;
|
||
|
|
||
|
- write_data_dma(nandc, reg_off, data_buf, data_size2);
|
||
|
+ write_data_dma(nandc, reg_off, data_buf, data_size2,
|
||
|
+ DMA_DESC_FLAG_NO_EOT);
|
||
|
reg_off += data_size2;
|
||
|
data_buf += data_size2;
|
||
|
|
||
|
- write_data_dma(nandc, reg_off, oob_buf, oob_size2);
|
||
|
+ write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
|
||
|
oob_buf += oob_size2;
|
||
|
|
||
|
config_cw_write_post(nandc);
|
||
|
@@ -1467,6 +1958,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
|
||
|
|
||
|
host->use_ecc = true;
|
||
|
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
ret = copy_last_cw(host, page);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
@@ -1486,7 +1978,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
|
||
|
|
||
|
config_cw_write_pre(nandc);
|
||
|
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
|
||
|
- data_size + oob_size);
|
||
|
+ data_size + oob_size, 0);
|
||
|
config_cw_write_post(nandc);
|
||
|
|
||
|
ret = submit_descs(nandc);
|
||
|
@@ -1524,6 +2016,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
|
||
|
*/
|
||
|
host->use_ecc = false;
|
||
|
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
ret = copy_last_cw(host, page);
|
||
|
if (ret)
|
||
|
goto err;
|
||
|
@@ -1554,6 +2047,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
|
||
|
int page, ret, status = 0;
|
||
|
|
||
|
clear_read_regs(nandc);
|
||
|
+ clear_bam_transaction(nandc);
|
||
|
|
||
|
/*
|
||
|
* to mark the BBM as bad, we flash the entire last codeword with 0s.
|
||
|
@@ -1570,7 +2064,8 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
|
||
|
update_rw_regs(host, 1, false);
|
||
|
|
||
|
config_cw_write_pre(nandc);
|
||
|
- write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
|
||
|
+ write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
|
||
|
+ host->cw_size, 0);
|
||
|
config_cw_write_post(nandc);
|
||
|
|
||
|
ret = submit_descs(nandc);
|
||
|
@@ -1930,6 +2425,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
|
||
|
|
||
|
host->clrflashstatus = FS_READY_BSY_N;
|
||
|
host->clrreadstatus = 0xc0;
|
||
|
+ nandc->regs->erased_cw_detect_cfg_clr = CLR_ERASED_PAGE_DET;
|
||
|
+ nandc->regs->erased_cw_detect_cfg_set = SET_ERASED_PAGE_DET;
|
||
|
|
||
|
dev_dbg(nandc->dev,
|
||
|
"cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
|
||
|
@@ -2008,6 +2505,12 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
|
||
|
dev_err(nandc->dev, "failed to request cmd channel\n");
|
||
|
return -ENODEV;
|
||
|
}
|
||
|
+
|
||
|
+ nandc->bam_txn = alloc_bam_transaction(nandc);
|
||
|
+ if (!nandc->bam_txn) {
|
||
|
+ dev_err(nandc->dev, "failed to allocate bam transaction\n");
|
||
|
+ return -ENOMEM;
|
||
|
+ }
|
||
|
}
|
||
|
|
||
|
INIT_LIST_HEAD(&nandc->desc_list);
|
||
|
@@ -2043,6 +2546,9 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
|
||
|
devm_kfree(nandc->dev, nandc->reg_read_buf);
|
||
|
}
|
||
|
|
||
|
+ if (nandc->bam_txn)
|
||
|
+ devm_kfree(nandc->dev, nandc->bam_txn);
|
||
|
+
|
||
|
if (nandc->regs)
|
||
|
devm_kfree(nandc->dev, nandc->regs);
|
||
|
|
||
|
@@ -2053,11 +2559,18 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
|
||
|
/* one time setup of a few nand controller registers */
|
||
|
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
|
||
|
{
|
||
|
+ u32 nand_ctrl;
|
||
|
+
|
||
|
/* kill onenand */
|
||
|
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
|
||
|
|
||
|
- /* enable ADM DMA */
|
||
|
- nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
|
||
|
+ /* enable ADM or BAM DMA */
|
||
|
+ if (!nandc->dma_bam_enabled) {
|
||
|
+ nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
|
||
|
+ } else {
|
||
|
+ nand_ctrl = nandc_read(nandc, NAND_CTRL);
|
||
|
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
|
||
|
+ }
|
||
|
|
||
|
/* save the original values of these registers */
|
||
|
nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
|
||
|
diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_dma.h
|
||
|
new file mode 100644
|
||
|
index 0000000..7e87a85
|
||
|
--- /dev/null
|
||
|
+++ b/include/linux/dma/qcom_bam_dma.h
|
||
|
@@ -0,0 +1,149 @@
|
||
|
+/*
|
||
|
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
||
|
+ *
|
||
|
+ * Permission to use, copy, modify, and/or distribute this software for any
|
||
|
+ * purpose with or without fee is hereby granted, provided that the above
|
||
|
+ * copyright notice and this permission notice appear in all copies.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||
|
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||
|
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||
|
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||
|
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||
|
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||
|
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||
|
+ */
|
||
|
+
|
||
|
+#ifndef _QCOM_BAM_DMA_H
|
||
|
+#define _QCOM_BAM_DMA_H
|
||
|
+
|
||
|
+#include <linux/dma-mapping.h>
|
||
|
+
|
||
|
+#define DESC_FLAG_INT BIT(15)
|
||
|
+#define DESC_FLAG_EOT BIT(14)
|
||
|
+#define DESC_FLAG_EOB BIT(13)
|
||
|
+#define DESC_FLAG_NWD BIT(12)
|
||
|
+#define DESC_FLAG_CMD BIT(11)
|
||
|
+
|
||
|
+/*
|
||
|
+ * QCOM BAM DMA SGL struct
|
||
|
+ *
|
||
|
+ * @sgl: DMA SGL
|
||
|
+ * @dma_flags: BAM DMA flags
|
||
|
+ */
|
||
|
+struct qcom_bam_sgl {
|
||
|
+ struct scatterlist sgl;
|
||
|
+ unsigned int dma_flags;
|
||
|
+};
|
||
|
+
|
||
|
+/*
|
||
|
+ * This data type corresponds to the native Command Element
|
||
|
+ * supported by BAM DMA Engine.
|
||
|
+ *
|
||
|
+ * @addr - register address.
|
||
|
+ * @command - command type.
|
||
|
+ * @data - for write command: content to be written into peripheral register.
|
||
|
+ * for read command: dest addr to write peripheral register value to.
|
||
|
+ * @mask - register mask.
|
||
|
+ * @reserved - for future usage.
|
||
|
+ *
|
||
|
+ */
|
||
|
+struct bam_cmd_element {
|
||
|
+ __le32 addr:24;
|
||
|
+ __le32 command:8;
|
||
|
+ __le32 data;
|
||
|
+ __le32 mask;
|
||
|
+ __le32 reserved;
|
||
|
+};
|
||
|
+
|
||
|
+/*
|
||
|
+ * This enum indicates the command type in a command element
|
||
|
+ */
|
||
|
+enum bam_command_type {
|
||
|
+ BAM_WRITE_COMMAND = 0,
|
||
|
+ BAM_READ_COMMAND,
|
||
|
+};
|
||
|
+
|
||
|
+/*
|
||
|
+ * qcom_bam_sg_init_table - Init QCOM BAM SGL
|
||
|
+ * @bam_sgl: bam sgl
|
||
|
+ * @nents: number of entries in bam sgl
|
||
|
+ *
|
||
|
+ * This function performs the initialization for each SGL in BAM SGL
|
||
|
+ * with generic SGL API.
|
||
|
+ */
|
||
|
+static inline void qcom_bam_sg_init_table(struct qcom_bam_sgl *bam_sgl,
|
||
|
+ unsigned int nents)
|
||
|
+{
|
||
|
+ int i;
|
||
|
+
|
||
|
+ for (i = 0; i < nents; i++)
|
||
|
+ sg_init_table(&bam_sgl[i].sgl, 1);
|
||
|
+}
|
||
|
+
|
||
|
+/*
|
||
|
+ * qcom_bam_unmap_sg - Unmap QCOM BAM SGL
|
||
|
+ * @dev: device for which unmapping needs to be done
|
||
|
+ * @bam_sgl: bam sgl
|
||
|
+ * @nents: number of entries in bam sgl
|
||
|
+ * @dir: dma transfer direction
|
||
|
+ *
|
||
|
+ * This function performs the DMA unmapping for each SGL in BAM SGL
|
||
|
+ * with generic SGL API.
|
||
|
+ */
|
||
|
+static inline void qcom_bam_unmap_sg(struct device *dev,
|
||
|
+ struct qcom_bam_sgl *bam_sgl, int nents, enum dma_data_direction dir)
|
||
|
+{
|
||
|
+ int i;
|
||
|
+
|
||
|
+ for (i = 0; i < nents; i++)
|
||
|
+ dma_unmap_sg(dev, &bam_sgl[i].sgl, 1, dir);
|
||
|
+}
|
||
|
+
|
||
|
+/*
|
||
|
+ * qcom_bam_map_sg - Map QCOM BAM SGL
|
||
|
+ * @dev: device for which mapping needs to be done
|
||
|
+ * @bam_sgl: bam sgl
|
||
|
+ * @nents: number of entries in bam sgl
|
||
|
+ * @dir: dma transfer direction
|
||
|
+ *
|
||
|
+ * This function performs the DMA mapping for each SGL in BAM SGL
|
||
|
+ * with generic SGL API.
|
||
|
+ *
|
||
|
+ * returns 0 on error and > 0 on success
|
||
|
+ */
|
||
|
+static inline int qcom_bam_map_sg(struct device *dev,
|
||
|
+ struct qcom_bam_sgl *bam_sgl, int nents, enum dma_data_direction dir)
|
||
|
+{
|
||
|
+ int i, ret = 0;
|
||
|
+
|
||
|
+ for (i = 0; i < nents; i++) {
|
||
|
+ ret = dma_map_sg(dev, &bam_sgl[i].sgl, 1, dir);
|
||
|
+ if (!ret)
|
||
|
+ break;
|
||
|
+ }
|
||
|
+
|
||
|
+ /* unmap the mapped sgl from previous loop in case of error */
|
||
|
+ if (!ret)
|
||
|
+ qcom_bam_unmap_sg(dev, bam_sgl, i, dir);
|
||
|
+
|
||
|
+ return ret;
|
||
|
+}
|
||
|
+
|
||
|
+/*
|
||
|
+ * qcom_prep_bam_ce - Wrapper function to prepare a single BAM command element
|
||
|
+ * with the data that is passed to this function.
|
||
|
+ * @bam_ce: bam command element
|
||
|
+ * @addr: target address
|
||
|
+ * @command: command in bam_command_type
|
||
|
+ * @data: actual data for write and dest addr for read
|
||
|
+ */
|
||
|
+static inline void qcom_prep_bam_ce(struct bam_cmd_element *bam_ce,
|
||
|
+ uint32_t addr, uint32_t command, uint32_t data)
|
||
|
+{
|
||
|
+ bam_ce->addr = cpu_to_le32(addr);
|
||
|
+ bam_ce->command = cpu_to_le32(command);
|
||
|
+ bam_ce->data = cpu_to_le32(data);
|
||
|
+ bam_ce->mask = 0xFFFFFFFF;
|
||
|
+}
|
||
|
+#endif
|
||
|
--
|
||
|
2.7.2
|