2016-05-15 11:14:00 +00:00
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From: Felix Fietkau <nbd@nbd.name>
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Date: Sun, 15 May 2016 13:09:20 +0200
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Subject: [PATCH] MIPS: ath79: fix regression in PCI window initialization
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ath79_ddr_pci_win_base has the type void __iomem *, so register offsets
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need to be a multiple of 4.
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Cc: Alban Bedel <albeu@free.fr>
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Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -76,14 +76,14 @@ void ath79_ddr_set_pci_windows(void)
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{
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BUG_ON(!ath79_ddr_pci_win_base);
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- __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0);
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- __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1);
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- __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2);
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- __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3);
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- __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4);
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- __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5);
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- __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6);
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- __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7);
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+ __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
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+ __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
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+ __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
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+ __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
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+ __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
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+ __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
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+ __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
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2016-05-16 17:52:31 +00:00
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+ __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
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2016-05-15 11:14:00 +00:00
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}
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EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
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