layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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From a4be9046c3a3fc39a06089553df8cc19a2abd814 Mon Sep 17 00:00:00 2001
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From: Priyanka Jain <Priyanka.Jain@freescale.com>
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Date: Tue, 3 Nov 2015 11:25:24 +0530
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Subject: [PATCH 233/238] i2c: pca954x: Add option to skip disabling PCA954x
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Mux device
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On some Layerscape boards like LS2085ARDB/LS2080ARDB,
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input pull-up resistors on PCA954x Mux device are
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missing on board. So, if mux are disabled after powered-on,
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input lines will float leading to incorrect functionality.
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Hence, PCA954x Mux device should never be turned-off after
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power-on.
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Add option to skip disabling PCA954x Mux device
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if device tree contians "i2c-mux-never-disable" property
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for pca954x device node.
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Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
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---
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drivers/i2c/muxes/i2c-mux-pca954x.c | 38 +++++++++++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
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+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
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@@ -63,6 +63,7 @@ struct pca954x {
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struct i2c_adapter *virt_adaps[PCA954X_MAX_NCHANS];
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u8 last_chan; /* last register value */
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+ u8 disable_mux; /* do not disable mux if val not 0 */
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};
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struct chip_desc {
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2017-01-06 12:53:27 +00:00
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@@ -174,6 +175,13 @@ static int pca954x_deselect_mux(struct i
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layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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{
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struct pca954x *data = i2c_get_clientdata(client);
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+#ifdef CONFIG_ARCH_LAYERSCAPE
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+ if (data->disable_mux != 0)
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+ data->last_chan = chips[data->type].nchans;
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+ else
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+ data->last_chan = 0;
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+ return pca954x_reg_write(adap, client, data->disable_mux);
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+#endif
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/* Deselect active channel */
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data->last_chan = 0;
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return pca954x_reg_write(adap, client, data->last_chan);
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2017-01-06 12:53:27 +00:00
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@@ -201,6 +209,23 @@ static int pca954x_probe(struct i2c_clie
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layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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if (!data)
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return -ENOMEM;
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+#ifdef CONFIG_ARCH_LAYERSCAPE
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+ /* The point here is that you must not disable a mux if there
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+ * are no pullups on the input or you mess up the I2C. This
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+ * needs to be put into the DTS really as the kernel cannot
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+ * know this otherwise.
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+ */
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+ data->type = id->driver_data;
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+ data->disable_mux = of_node &&
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+ of_property_read_bool(of_node, "i2c-mux-never-disable") &&
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+ chips[data->type].muxtype == pca954x_ismux ?
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+ chips[data->type].enable : 0;
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+ /* force the first selection */
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+ if (data->disable_mux != 0)
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+ data->last_chan = chips[data->type].nchans;
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+ else
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+ data->last_chan = 0;
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+#endif
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i2c_set_clientdata(client, data);
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/* Get the mux out of reset if a reset GPIO is specified. */
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2017-01-06 12:53:27 +00:00
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@@ -212,13 +237,19 @@ static int pca954x_probe(struct i2c_clie
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layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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* that the mux is in fact present. This also
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* initializes the mux to disconnected state.
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*/
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+#ifdef CONFIG_ARCH_LAYERSCAPE
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+ if (i2c_smbus_write_byte(client, data->disable_mux) < 0) {
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+#else
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if (i2c_smbus_write_byte(client, 0) < 0) {
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+#endif
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dev_warn(&client->dev, "probe failed\n");
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return -ENODEV;
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}
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+#ifndef CONFIG_ARCH_LAYERSCAPE
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data->type = id->driver_data;
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data->last_chan = 0; /* force the first selection */
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+#endif
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idle_disconnect_dt = of_node &&
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of_property_read_bool(of_node, "i2c-mux-idle-disconnect");
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2017-01-06 12:53:27 +00:00
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@@ -289,6 +320,13 @@ static int pca954x_resume(struct device
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layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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struct i2c_client *client = to_i2c_client(dev);
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struct pca954x *data = i2c_get_clientdata(client);
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+#ifdef CONFIG_ARCH_LAYERSCAPE
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+ if (data->disable_mux != 0)
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+ data->last_chan = chips[data->type].nchans;
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+ else
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+ data->last_chan = 0;
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+ return i2c_smbus_write_byte(client, data->disable_mux);
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+#endif
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data->last_chan = 0;
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return i2c_smbus_write_byte(client, 0);
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}
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