mirror of https://github.com/hak5/openwrt.git
754 lines
19 KiB
Diff
754 lines
19 KiB
Diff
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,4/5] PCI: qcom: Add Qualcomm PCIe controller driver
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From: Stanimir Varbanov <svarbanov@mm-sol.com>
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X-Patchwork-Id: 6326161
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Message-Id: <1430743338-10441-5-git-send-email-svarbanov@mm-sol.com>
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To: Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>,
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Mark Rutland <mark.rutland@arm.com>,
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Grant Likely <grant.likely@linaro.org>,
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Bjorn Helgaas <bhelgaas@google.com>,
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Kishon Vijay Abraham I <kishon@ti.com>,
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Russell King <linux@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>
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Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
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linux-pci@vger.kernel.org, Mathieu Olivari <mathieu@codeaurora.org>,
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Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
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Stanimir Varbanov <svarbanov@mm-sol.com>
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Date: Mon, 4 May 2015 15:42:17 +0300
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The PCIe driver reuse the Designware common code for host
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and MSI initialization, and also program the Qualcomm
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application specific registers.
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Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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---
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MAINTAINERS | 7 +
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drivers/pci/host/Kconfig | 9 +
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drivers/pci/host/Makefile | 1 +
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drivers/pci/host/pcie-qcom.c | 677 ++++++++++++++++++++++++++++++++++++++++++
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4 files changed, 694 insertions(+), 0 deletions(-)
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create mode 100644 drivers/pci/host/pcie-qcom.c
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -7599,6 +7599,13 @@ L: linux-pci@vger.kernel.org
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S: Maintained
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F: drivers/pci/host/*spear*
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+PCIE DRIVER FOR QUALCOMM MSM
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+M: Stanimir Varbanov <svarbanov@mm-sol.com>
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+L: linux-pci@vger.kernel.org
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+L: linux-arm-msm@vger.kernel.org
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+S: Maintained
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+F: drivers/pci/host/*qcom*
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+
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PCMCIA SUBSYSTEM
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P: Linux PCMCIA Team
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L: linux-pcmcia@lists.infradead.org
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--- a/drivers/pci/host/Kconfig
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+++ b/drivers/pci/host/Kconfig
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@@ -125,4 +125,13 @@ config PCIE_IPROC_PLATFORM
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Say Y here if you want to use the Broadcom iProc PCIe controller
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through the generic platform bus interface
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+config PCIE_QCOM
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+ bool "Qualcomm PCIe controller"
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+ depends on ARCH_QCOM && OF || (ARM && COMPILE_TEST)
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+ select PCIE_DW
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+ select PCIEPORTBUS
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+ help
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+ Say Y here to enable PCIe controller support on Qualcomm SoCs. The
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+ PCIe controller use Designware core plus Qualcomm specific hardware
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+ wrappers.
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endmenu
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--- /dev/null
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+++ b/drivers/pci/host/pcie-qcom.c
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@@ -0,0 +1,677 @@
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+/*
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+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/gpio.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of_gpio.h>
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+#include <linux/pci.h>
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+#include <linux/platform_device.h>
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+#include <linux/phy/phy.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/reset.h>
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+#include <linux/slab.h>
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+#include <linux/types.h>
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+
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+#include "pcie-designware.h"
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+
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+#define PCIE20_PARF_PHY_CTRL 0x40
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+#define PCIE20_PARF_PHY_REFCLK 0x4C
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+#define PCIE20_PARF_DBI_BASE_ADDR 0x168
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+#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
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+#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
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+
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+#define PCIE20_ELBI_SYS_CTRL 0x04
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+#define PCIE20_ELBI_SYS_STTS 0x08
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+#define XMLH_LINK_UP BIT(10)
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+
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+#define PCIE20_CAP 0x70
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+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
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+
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+#define PERST_DELAY_MIN_US 1000
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+#define PERST_DELAY_MAX_US 1005
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+
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+#define LINKUP_DELAY_MIN_US 5000
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+#define LINKUP_DELAY_MAX_US 5100
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+#define LINKUP_RETRIES_COUNT 20
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+
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+#define PCIE_V0 0 /* apq8064 */
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+#define PCIE_V1 1 /* apq8084 */
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+
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+struct qcom_pcie_resources_v0 {
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+ struct clk *iface_clk;
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+ struct clk *core_clk;
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+ struct clk *phy_clk;
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+ struct reset_control *pci_reset;
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+ struct reset_control *axi_reset;
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+ struct reset_control *ahb_reset;
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+ struct reset_control *por_reset;
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+ struct reset_control *phy_reset;
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+ struct regulator *vdda;
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+ struct regulator *vdda_phy;
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+ struct regulator *vdda_refclk;
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+};
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+
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+struct qcom_pcie_resources_v1 {
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+ struct clk *iface;
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+ struct clk *aux;
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+ struct clk *master_bus;
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+ struct clk *slave_bus;
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+ struct reset_control *core;
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+ struct regulator *vdda;
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+};
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+
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+union pcie_resources {
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+ struct qcom_pcie_resources_v0 v0;
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+ struct qcom_pcie_resources_v1 v1;
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+};
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+
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+struct qcom_pcie {
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+ struct pcie_port pp;
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+ struct device *dev;
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+ union pcie_resources res;
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+ void __iomem *parf;
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+ void __iomem *dbi;
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+ void __iomem *elbi;
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+ struct phy *phy;
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+ struct gpio_desc *reset;
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+ unsigned int version;
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+};
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+
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+#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
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+
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+static inline void
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+writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
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+{
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+ u32 val = readl(addr);
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+
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+ val &= ~clear_mask;
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+ val |= set_mask;
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+ writel(val, addr);
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+}
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+
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+static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
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+{
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+ int val, active_low;
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+
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+ if (IS_ERR_OR_NULL(pcie->reset))
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+ return;
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+
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+ active_low = gpiod_is_active_low(pcie->reset);
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+
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+ if (assert)
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+ val = !!active_low;
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+ else
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+ val = !active_low;
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+
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+ gpiod_set_value(pcie->reset, val);
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+
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+ usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
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+}
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+
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+static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
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+{
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+ qcom_ep_reset_assert_deassert(pcie, 1);
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+}
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+
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+static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
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+{
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+ qcom_ep_reset_assert_deassert(pcie, 0);
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+}
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+
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+static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
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+{
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+ struct pcie_port *pp = arg;
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+
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+ return dw_handle_msi_irq(pp);
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+}
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+
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+static int qcom_pcie_link_up(struct pcie_port *pp)
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+{
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+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
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+ u32 val = readl(pcie->dbi + PCIE20_CAP_LINKCTRLSTATUS);
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+
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+ return val & BIT(29) ? 1 : 0;
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+}
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+
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+static void qcom_pcie_disable_resources_v0(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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+
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+ reset_control_assert(res->pci_reset);
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+ reset_control_assert(res->axi_reset);
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+ reset_control_assert(res->ahb_reset);
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+ reset_control_assert(res->por_reset);
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+ reset_control_assert(res->pci_reset);
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+ clk_disable_unprepare(res->iface_clk);
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+ clk_disable_unprepare(res->core_clk);
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+ clk_disable_unprepare(res->phy_clk);
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+ regulator_disable(res->vdda);
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+ regulator_disable(res->vdda_phy);
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+ regulator_disable(res->vdda_refclk);
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+}
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+
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+static void qcom_pcie_disable_resources_v1(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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+
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+ reset_control_assert(res->core);
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+ clk_disable_unprepare(res->slave_bus);
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+ clk_disable_unprepare(res->master_bus);
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+ clk_disable_unprepare(res->iface);
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+ clk_disable_unprepare(res->aux);
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+ regulator_disable(res->vdda);
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+}
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+
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+static int qcom_pcie_enable_resources_v0(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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+ struct device *dev = pcie->dev;
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+ int ret;
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+
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+ ret = regulator_enable(res->vdda);
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+ if (ret) {
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+ dev_err(dev, "cannot enable vdda regulator\n");
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+ return ret;
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+ }
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+
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+ ret = regulator_enable(res->vdda_refclk);
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+ if (ret) {
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+ dev_err(dev, "cannot enable vdda_refclk regulator\n");
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+ goto err_refclk;
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+ }
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+
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+ ret = regulator_enable(res->vdda_phy);
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+ if (ret) {
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+ dev_err(dev, "cannot enable vdda_phy regulator\n");
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+ goto err_vdda_phy;
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+ }
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+
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+ ret = clk_prepare_enable(res->iface_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable iface clock\n");
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+ goto err_iface;
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+ }
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+
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+ ret = clk_prepare_enable(res->core_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable core clock\n");
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+ goto err_clk_core;
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+ }
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+
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+ ret = clk_prepare_enable(res->phy_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable phy clock\n");
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+ goto err_clk_phy;
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+ }
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+
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+ ret = reset_control_deassert(res->ahb_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert ahb reset\n");
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+ goto err_reset_ahb;
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+ }
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+
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+ return 0;
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+
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+err_reset_ahb:
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+ clk_disable_unprepare(res->phy_clk);
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+err_clk_phy:
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+ clk_disable_unprepare(res->core_clk);
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+err_clk_core:
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+ clk_disable_unprepare(res->iface_clk);
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+err_iface:
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+ regulator_disable(res->vdda_phy);
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+err_vdda_phy:
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+ regulator_disable(res->vdda_refclk);
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+err_refclk:
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+ regulator_disable(res->vdda);
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+ return ret;
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+}
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+
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+static int qcom_pcie_enable_resources_v1(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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+ struct device *dev = pcie->dev;
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+ int ret;
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+
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+ ret = reset_control_deassert(res->core);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert core reset\n");
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+ return ret;
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+ }
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+
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+ ret = clk_prepare_enable(res->aux);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable aux clock\n");
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+ goto err_res;
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+ }
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+
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+ ret = clk_prepare_enable(res->iface);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable iface clock\n");
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+ goto err_aux;
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+ }
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+
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+ ret = clk_prepare_enable(res->master_bus);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable master_bus clock\n");
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+ goto err_iface;
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+ }
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+
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+ ret = clk_prepare_enable(res->slave_bus);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable slave_bus clock\n");
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+ goto err_master;
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+ }
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+
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+ ret = regulator_enable(res->vdda);
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+ if (ret) {
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+ dev_err(dev, "cannot enable vdda regulator\n");
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+ goto err_slave;
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+ }
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+
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+ return 0;
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+
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+err_slave:
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+ clk_disable_unprepare(res->slave_bus);
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+err_master:
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+ clk_disable_unprepare(res->master_bus);
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+err_iface:
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+ clk_disable_unprepare(res->iface);
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+err_aux:
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+ clk_disable_unprepare(res->aux);
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+err_res:
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+ reset_control_assert(res->core);
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+
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+ return ret;
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+}
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+
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+static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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+ struct device *dev = pcie->dev;
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+
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+ res->vdda = devm_regulator_get(dev, "vdda");
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+ if (IS_ERR(res->vdda))
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+ return PTR_ERR(res->vdda);
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+
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+ res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
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+ if (IS_ERR(res->vdda_phy))
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+ return PTR_ERR(res->vdda_phy);
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+
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+ res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
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+ if (IS_ERR(res->vdda_refclk))
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+ return PTR_ERR(res->vdda_refclk);
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+
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+ res->iface_clk = devm_clk_get(dev, "iface");
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+ if (IS_ERR(res->iface_clk))
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+ return PTR_ERR(res->iface_clk);
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+
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+ res->core_clk = devm_clk_get(dev, "core");
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+ if (IS_ERR(res->core_clk))
|
||
|
+ return PTR_ERR(res->core_clk);
|
||
|
+
|
||
|
+ res->phy_clk = devm_clk_get(dev, "phy");
|
||
|
+ if (IS_ERR(res->phy_clk))
|
||
|
+ return PTR_ERR(res->phy_clk);
|
||
|
+
|
||
|
+ res->pci_reset = devm_reset_control_get(dev, "pci");
|
||
|
+ if (IS_ERR(res->pci_reset))
|
||
|
+ return PTR_ERR(res->pci_reset);
|
||
|
+
|
||
|
+ res->axi_reset = devm_reset_control_get(dev, "axi");
|
||
|
+ if (IS_ERR(res->axi_reset))
|
||
|
+ return PTR_ERR(res->axi_reset);
|
||
|
+
|
||
|
+ res->ahb_reset = devm_reset_control_get(dev, "ahb");
|
||
|
+ if (IS_ERR(res->ahb_reset))
|
||
|
+ return PTR_ERR(res->ahb_reset);
|
||
|
+
|
||
|
+ res->por_reset = devm_reset_control_get(dev, "por");
|
||
|
+ if (IS_ERR(res->por_reset))
|
||
|
+ return PTR_ERR(res->por_reset);
|
||
|
+
|
||
|
+ res->phy_reset = devm_reset_control_get(dev, "phy");
|
||
|
+ if (IS_ERR(res->phy_reset))
|
||
|
+ return PTR_ERR(res->phy_reset);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
|
||
|
+{
|
||
|
+ struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
|
||
|
+ struct device *dev = pcie->dev;
|
||
|
+
|
||
|
+ res->vdda = devm_regulator_get(dev, "vdda");
|
||
|
+ if (IS_ERR(res->vdda))
|
||
|
+ return PTR_ERR(res->vdda);
|
||
|
+
|
||
|
+ res->iface = devm_clk_get(dev, "iface");
|
||
|
+ if (IS_ERR(res->iface))
|
||
|
+ return PTR_ERR(res->iface);
|
||
|
+
|
||
|
+ res->aux = devm_clk_get(dev, "aux");
|
||
|
+ if (IS_ERR(res->aux) && PTR_ERR(res->aux) == -EPROBE_DEFER)
|
||
|
+ return -EPROBE_DEFER;
|
||
|
+ else if (IS_ERR(res->aux))
|
||
|
+ res->aux = NULL;
|
||
|
+
|
||
|
+ res->master_bus = devm_clk_get(dev, "master_bus");
|
||
|
+ if (IS_ERR(res->master_bus))
|
||
|
+ return PTR_ERR(res->master_bus);
|
||
|
+
|
||
|
+ res->slave_bus = devm_clk_get(dev, "slave_bus");
|
||
|
+ if (IS_ERR(res->slave_bus))
|
||
|
+ return PTR_ERR(res->slave_bus);
|
||
|
+
|
||
|
+ res->core = devm_reset_control_get(dev, "core");
|
||
|
+ if (IS_ERR(res->core))
|
||
|
+ return PTR_ERR(res->core);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int qcom_pcie_enable_link_training(struct pcie_port *pp)
|
||
|
+{
|
||
|
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
|
||
|
+ struct device *dev = pp->dev;
|
||
|
+ int retries;
|
||
|
+ u32 val;
|
||
|
+
|
||
|
+ /* enable link training */
|
||
|
+ writel_masked(pcie->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0));
|
||
|
+
|
||
|
+ /* wait for up to 100ms for the link to come up */
|
||
|
+ retries = LINKUP_RETRIES_COUNT;
|
||
|
+ do {
|
||
|
+ val = readl(pcie->elbi + PCIE20_ELBI_SYS_STTS);
|
||
|
+ if (val & XMLH_LINK_UP)
|
||
|
+ break;
|
||
|
+ usleep_range(LINKUP_DELAY_MIN_US, LINKUP_DELAY_MAX_US);
|
||
|
+ } while (retries--);
|
||
|
+
|
||
|
+ if (retries < 0 || !dw_pcie_link_up(pp)) {
|
||
|
+ dev_err(dev, "link initialization failed\n");
|
||
|
+ return -ENXIO;
|
||
|
+ }
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static void qcom_pcie_host_init_v1(struct pcie_port *pp)
|
||
|
+{
|
||
|
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ qcom_ep_reset_assert(pcie);
|
||
|
+
|
||
|
+ ret = qcom_pcie_enable_resources_v1(pcie);
|
||
|
+ if (ret)
|
||
|
+ return;
|
||
|
+
|
||
|
+ /* change DBI base address */
|
||
|
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
|
||
|
+
|
||
|
+ if (IS_ENABLED(CONFIG_PCI_MSI))
|
||
|
+ writel_masked(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,
|
||
|
+ 0, BIT(31));
|
||
|
+
|
||
|
+ ret = phy_init(pcie->phy);
|
||
|
+ if (ret)
|
||
|
+ goto err_res;
|
||
|
+
|
||
|
+ ret = phy_power_on(pcie->phy);
|
||
|
+ if (ret)
|
||
|
+ goto err_phy;
|
||
|
+
|
||
|
+ dw_pcie_setup_rc(pp);
|
||
|
+
|
||
|
+ if (IS_ENABLED(CONFIG_PCI_MSI))
|
||
|
+ dw_pcie_msi_init(pp);
|
||
|
+
|
||
|
+ qcom_ep_reset_deassert(pcie);
|
||
|
+
|
||
|
+ ret = qcom_pcie_enable_link_training(pp);
|
||
|
+ if (ret)
|
||
|
+ goto err;
|
||
|
+
|
||
|
+ return;
|
||
|
+
|
||
|
+err:
|
||
|
+ qcom_ep_reset_assert(pcie);
|
||
|
+ phy_power_off(pcie->phy);
|
||
|
+err_phy:
|
||
|
+ phy_exit(pcie->phy);
|
||
|
+err_res:
|
||
|
+ qcom_pcie_disable_resources_v1(pcie);
|
||
|
+}
|
||
|
+
|
||
|
+static void qcom_pcie_host_init_v0(struct pcie_port *pp)
|
||
|
+{
|
||
|
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
|
||
|
+ struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
|
||
|
+ struct device *dev = pcie->dev;
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ qcom_ep_reset_assert(pcie);
|
||
|
+
|
||
|
+ ret = qcom_pcie_enable_resources_v0(pcie);
|
||
|
+ if (ret)
|
||
|
+ return;
|
||
|
+
|
||
|
+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
|
||
|
+
|
||
|
+ /* enable external reference clock */
|
||
|
+ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16));
|
||
|
+
|
||
|
+ ret = reset_control_deassert(res->phy_reset);
|
||
|
+ if (ret) {
|
||
|
+ dev_err(dev, "cannot deassert phy reset\n");
|
||
|
+ return;
|
||
|
+ }
|
||
|
+
|
||
|
+ ret = reset_control_deassert(res->pci_reset);
|
||
|
+ if (ret) {
|
||
|
+ dev_err(dev, "cannot deassert pci reset\n");
|
||
|
+ return;
|
||
|
+ }
|
||
|
+
|
||
|
+ ret = reset_control_deassert(res->por_reset);
|
||
|
+ if (ret) {
|
||
|
+ dev_err(dev, "cannot deassert por reset\n");
|
||
|
+ return;
|
||
|
+ }
|
||
|
+
|
||
|
+ ret = reset_control_deassert(res->axi_reset);
|
||
|
+ if (ret) {
|
||
|
+ dev_err(dev, "cannot deassert axi reset\n");
|
||
|
+ return;
|
||
|
+ }
|
||
|
+
|
||
|
+ /* wait 150ms for clock acquisition */
|
||
|
+ usleep_range(10000, 15000);
|
||
|
+
|
||
|
+ dw_pcie_setup_rc(pp);
|
||
|
+
|
||
|
+ if (IS_ENABLED(CONFIG_PCI_MSI))
|
||
|
+ dw_pcie_msi_init(pp);
|
||
|
+
|
||
|
+ qcom_ep_reset_deassert(pcie);
|
||
|
+
|
||
|
+ ret = qcom_pcie_enable_link_training(pp);
|
||
|
+ if (ret)
|
||
|
+ goto err;
|
||
|
+
|
||
|
+ return;
|
||
|
+err:
|
||
|
+ qcom_ep_reset_assert(pcie);
|
||
|
+ qcom_pcie_disable_resources_v0(pcie);
|
||
|
+}
|
||
|
+
|
||
|
+static void qcom_pcie_host_init(struct pcie_port *pp)
|
||
|
+{
|
||
|
+ struct qcom_pcie *pcie = to_qcom_pcie(pp);
|
||
|
+
|
||
|
+ if (pcie->version == PCIE_V0)
|
||
|
+ return qcom_pcie_host_init_v0(pp);
|
||
|
+ else
|
||
|
+ return qcom_pcie_host_init_v1(pp);
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val)
|
||
|
+{
|
||
|
+ /* the device class is not reported correctly from the register */
|
||
|
+ if (where == PCI_CLASS_REVISION && size == 4) {
|
||
|
+ *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
|
||
|
+ *val &= ~(0xffff << 16);
|
||
|
+ *val |= PCI_CLASS_BRIDGE_PCI << 16;
|
||
|
+ return PCIBIOS_SUCCESSFUL;
|
||
|
+ }
|
||
|
+
|
||
|
+ return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
|
||
|
+ size, val);
|
||
|
+}
|
||
|
+
|
||
|
+static struct pcie_host_ops qcom_pcie_ops = {
|
||
|
+ .link_up = qcom_pcie_link_up,
|
||
|
+ .host_init = qcom_pcie_host_init,
|
||
|
+ .rd_own_conf = qcom_pcie_rd_own_conf,
|
||
|
+};
|
||
|
+
|
||
|
+static const struct of_device_id qcom_pcie_match[] = {
|
||
|
+ { .compatible = "qcom,pcie-v0", .data = (void *)PCIE_V0 },
|
||
|
+ { .compatible = "qcom,pcie-v1", .data = (void *)PCIE_V1 },
|
||
|
+ { }
|
||
|
+};
|
||
|
+
|
||
|
+static int qcom_pcie_probe(struct platform_device *pdev)
|
||
|
+{
|
||
|
+ struct device *dev = &pdev->dev;
|
||
|
+ const struct of_device_id *match;
|
||
|
+ struct resource *res;
|
||
|
+ struct qcom_pcie *pcie;
|
||
|
+ struct pcie_port *pp;
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ match = of_match_node(qcom_pcie_match, dev->of_node);
|
||
|
+ if (!match)
|
||
|
+ return -ENXIO;
|
||
|
+
|
||
|
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||
|
+ if (!pcie)
|
||
|
+ return -ENOMEM;
|
||
|
+
|
||
|
+ pcie->version = (unsigned int)match->data;
|
||
|
+
|
||
|
+ pcie->reset = devm_gpiod_get_optional(dev, "perst");
|
||
|
+ if (IS_ERR(pcie->reset) && PTR_ERR(pcie->reset) == -EPROBE_DEFER)
|
||
|
+ return PTR_ERR(pcie->reset);
|
||
|
+
|
||
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
|
||
|
+ pcie->parf = devm_ioremap_resource(dev, res);
|
||
|
+ if (IS_ERR(pcie->parf))
|
||
|
+ return PTR_ERR(pcie->parf);
|
||
|
+
|
||
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||
|
+ pcie->dbi = devm_ioremap_resource(dev, res);
|
||
|
+ if (IS_ERR(pcie->dbi))
|
||
|
+ return PTR_ERR(pcie->dbi);
|
||
|
+
|
||
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
|
||
|
+ pcie->elbi = devm_ioremap_resource(dev, res);
|
||
|
+ if (IS_ERR(pcie->elbi))
|
||
|
+ return PTR_ERR(pcie->elbi);
|
||
|
+
|
||
|
+ pcie->phy = devm_phy_optional_get(dev, "pciephy");
|
||
|
+ if (IS_ERR(pcie->phy))
|
||
|
+ return PTR_ERR(pcie->phy);
|
||
|
+
|
||
|
+ pcie->dev = dev;
|
||
|
+
|
||
|
+ if (pcie->version == PCIE_V0)
|
||
|
+ ret = qcom_pcie_get_resources_v0(pcie);
|
||
|
+ else
|
||
|
+ ret = qcom_pcie_get_resources_v1(pcie);
|
||
|
+
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
+
|
||
|
+ pp = &pcie->pp;
|
||
|
+ pp->dev = dev;
|
||
|
+ pp->dbi_base = pcie->dbi;
|
||
|
+ pp->root_bus_nr = -1;
|
||
|
+ pp->ops = &qcom_pcie_ops;
|
||
|
+
|
||
|
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||
|
+ pp->msi_irq = platform_get_irq_byname(pdev, "msi");
|
||
|
+ if (pp->msi_irq < 0) {
|
||
|
+ dev_err(dev, "cannot get msi irq\n");
|
||
|
+ return pp->msi_irq;
|
||
|
+ }
|
||
|
+
|
||
|
+ ret = devm_request_irq(dev, pp->msi_irq,
|
||
|
+ qcom_pcie_msi_irq_handler,
|
||
|
+ IRQF_SHARED, "qcom-pcie-msi", pp);
|
||
|
+ if (ret) {
|
||
|
+ dev_err(dev, "cannot request msi irq\n");
|
||
|
+ return ret;
|
||
|
+ }
|
||
|
+ }
|
||
|
+
|
||
|
+ ret = dw_pcie_host_init(pp);
|
||
|
+ if (ret) {
|
||
|
+ dev_err(dev, "cannot initialize host\n");
|
||
|
+ return ret;
|
||
|
+ }
|
||
|
+
|
||
|
+ platform_set_drvdata(pdev, pcie);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int qcom_pcie_remove(struct platform_device *pdev)
|
||
|
+{
|
||
|
+ struct qcom_pcie *pcie = platform_get_drvdata(pdev);
|
||
|
+
|
||
|
+ qcom_ep_reset_assert(pcie);
|
||
|
+ phy_power_off(pcie->phy);
|
||
|
+ phy_exit(pcie->phy);
|
||
|
+ if (pcie->version == PCIE_V0)
|
||
|
+ qcom_pcie_disable_resources_v0(pcie);
|
||
|
+ else
|
||
|
+ qcom_pcie_disable_resources_v1(pcie);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static struct platform_driver qcom_pcie_driver = {
|
||
|
+ .probe = qcom_pcie_probe,
|
||
|
+ .remove = qcom_pcie_remove,
|
||
|
+ .driver = {
|
||
|
+ .name = "qcom-pcie",
|
||
|
+ .of_match_table = qcom_pcie_match,
|
||
|
+ },
|
||
|
+};
|
||
|
+
|
||
|
+module_platform_driver(qcom_pcie_driver);
|
||
|
+
|
||
|
+MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
|
||
|
+MODULE_DESCRIPTION("Qualcomm PCIe root complex driver");
|
||
|
+MODULE_LICENSE("GPL v2");
|
||
|
+MODULE_ALIAS("platform:qcom-pcie");
|
||
|
--- a/drivers/pci/host/Makefile
|
||
|
+++ b/drivers/pci/host/Makefile
|
||
|
@@ -15,3 +15,4 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-laye
|
||
|
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
|
||
|
obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
|
||
|
obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
|
||
|
+obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
|