mirror of https://github.com/hak5/openwrt.git
118 lines
2.8 KiB
Diff
118 lines
2.8 KiB
Diff
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From 7a30e00a278fe94ac8e42d0967ffde99d1ab74ee Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 17:47:07 +0100
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Subject: [PATCH 117/137] DT: MIPS: ralink: clean up RT3050 dtsi and dts file
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* remove nodes for cores whose drivers are not upstream yet
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* add compat string for an additional soc
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* fix a whitespace error
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Grant Likely <grant.likely@secretlab.ca>
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Patchwork: http://patchwork.linux-mips.org/patch/5186/
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---
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arch/mips/ralink/dts/rt3050.dtsi | 52 ++--------------------------------
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arch/mips/ralink/dts/rt3052_eval.dts | 10 ++-----
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2 files changed, 4 insertions(+), 58 deletions(-)
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--- a/arch/mips/ralink/dts/rt3050.dtsi
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+++ b/arch/mips/ralink/dts/rt3050.dtsi
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@@ -1,7 +1,7 @@
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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- compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
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+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
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cpus {
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cpu@0 {
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@@ -9,10 +9,6 @@
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};
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};
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- chosen {
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- bootargs = "console=ttyS0,57600 init=/init";
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- };
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-
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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@@ -23,7 +19,7 @@
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palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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- ranges = <0x0 0x10000000 0x1FFFFF>;
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+ ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -33,11 +29,6 @@
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reg = <0x0 0x100>;
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};
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- timer@100 {
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- compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
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- reg = <0x100 0x100>;
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- };
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-
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intc: intc@200 {
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compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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@@ -54,45 +45,6 @@
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reg = <0x300 0x100>;
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};
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- gpio0: gpio@600 {
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- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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- reg = <0x600 0x34>;
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-
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- gpio-controller;
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- #gpio-cells = <2>;
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-
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- ralink,ngpio = <24>;
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- ralink,regs = [ 00 04 08 0c
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- 20 24 28 2c
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- 30 34 ];
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- };
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-
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- gpio1: gpio@638 {
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- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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- reg = <0x638 0x24>;
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-
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- gpio-controller;
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- #gpio-cells = <2>;
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-
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- ralink,ngpio = <16>;
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- ralink,regs = [ 00 04 08 0c
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- 10 14 18 1c
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- 20 24 ];
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- };
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-
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- gpio2: gpio@660 {
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- compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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- reg = <0x660 0x24>;
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-
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- gpio-controller;
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- #gpio-cells = <2>;
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-
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- ralink,ngpio = <12>;
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- ralink,regs = [ 00 04 08 0c
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- 10 14 18 1c
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- 20 24 ];
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- };
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-
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uartlite@c00 {
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compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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--- a/arch/mips/ralink/dts/rt3052_eval.dts
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+++ b/arch/mips/ralink/dts/rt3052_eval.dts
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@@ -3,8 +3,6 @@
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/include/ "rt3050.dtsi"
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/ {
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- #address-cells = <1>;
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- #size-cells = <1>;
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compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
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model = "Ralink RT3052 evaluation board";
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