mirror of https://github.com/hak5/openwrt.git
92 lines
3.6 KiB
C
92 lines
3.6 KiB
C
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/*
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* BCM4710 address space map and definitions
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* Think twice before adding to this file, this is not the kitchen sink
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* These definitions are not guaranteed for all 47xx chips, only the 4710
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
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*/
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#ifndef _bcm4710_h_
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#define _bcm4710_h_
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/* Address map */
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#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
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#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
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#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
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#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
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#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
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#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
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/* Core register space */
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#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
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#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
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#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
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#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
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#define BCM4710_REG_USB 0x18004000 /* USB core registers */
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#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
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#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
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#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
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#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
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#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
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#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
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#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
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#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
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#define BCM4710_PROG 0x1f800000 /* Programable interface */
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#define BCM4710_FLASH 0x1fc00000 /* Flash */
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#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
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#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
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#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
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#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
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#define SBFLAG_PCI 0
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#define SBFLAG_ENET0 1
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#define SBFLAG_ILINE20 2
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#define SBFLAG_CODEC 3
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#define SBFLAG_USB 4
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#define SBFLAG_EXTIF 5
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#define SBFLAG_ENET1 6
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#ifdef CONFIG_HWSIM
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#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
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#else
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#define BCM4710_TRACE(trval)
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#endif
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/* BCM94702 CPCI -ExtIF used for LocalBus devs */
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#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
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#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
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#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
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#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
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#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
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#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
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#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
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#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
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#define LED_REG(x) \
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(*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
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/*
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* Reset function implemented in PLD. Read or write should trigger hard reset
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*/
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#define SYS_HARD_RESET() \
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{ for (;;) \
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*( (volatile unsigned char *)\
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KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
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}
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#endif /* _bcm4710_h_ */
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