mirror of https://github.com/hak5/openwrt.git
86 lines
2.4 KiB
Diff
86 lines
2.4 KiB
Diff
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From 0916b46962cbcac9465d253d0a398435b3965fd5 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Thu, 31 Jan 2013 12:20:43 +0000
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Subject: [PATCH 13/14] MIPS: add irqdomain support for the CPU IRQ controller
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Add code to load a irq_domain for the MIPS IRQ controller from a devicetree
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file.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: David Daney <david.daney@cavium.com>
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Patchwork: http://patchwork.linux-mips.org/patch/4902/
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---
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arch/mips/include/asm/irq_cpu.h | 6 ++++++
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arch/mips/kernel/irq_cpu.c | 42 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 48 insertions(+)
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--- a/arch/mips/include/asm/irq_cpu.h
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+++ b/arch/mips/include/asm/irq_cpu.h
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@@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
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extern void rm7k_cpu_irq_init(void);
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extern void rm9k_cpu_irq_init(void);
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+#ifdef CONFIG_IRQ_DOMAIN
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+struct device_node;
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+extern int mips_cpu_intc_init(struct device_node *of_node,
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+ struct device_node *parent);
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+#endif
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+
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#endif /* _ASM_IRQ_CPU_H */
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--- a/arch/mips/kernel/irq_cpu.c
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+++ b/arch/mips/kernel/irq_cpu.c
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@@ -31,6 +31,7 @@
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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+#include <linux/irqdomain.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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@@ -113,3 +114,44 @@ void __init mips_cpu_irq_init(void)
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irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
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handle_percpu_irq);
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}
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+
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+#ifdef CONFIG_IRQ_DOMAIN
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+static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+{
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+ static struct irq_chip *chip;
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+
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+ if (hw < 2 && cpu_has_mipsmt) {
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+ /* Software interrupts are used for MT/CMT IPI */
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+ chip = &mips_mt_cpu_irq_controller;
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+ } else {
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+ chip = &mips_cpu_irq_controller;
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+ }
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+
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+ irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
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+ .map = mips_cpu_intc_map,
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+ .xlate = irq_domain_xlate_onecell,
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+};
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+
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+int __init mips_cpu_intc_init(struct device_node *of_node,
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+ struct device_node *parent)
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+{
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+ struct irq_domain *domain;
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+
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+ /* Mask interrupts. */
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+ clear_c0_status(ST0_IM);
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+ clear_c0_cause(CAUSEF_IP);
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+
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+ domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
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+ &mips_cpu_intc_irq_domain_ops, NULL);
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+ if (!domain)
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+ panic("Failed to add irqdomain for MIPS CPU\n");
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+
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+ return 0;
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+}
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+#endif /* CONFIG_IRQ_DOMAIN */
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