mirror of https://github.com/hak5/openwrt.git
68 lines
2.2 KiB
Diff
68 lines
2.2 KiB
Diff
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From eac04ec501cac3069c279ccaa72fce4f530a4071 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 8 Jul 2012 21:07:12 +0200
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Subject: [PATCH 68/72] MIPS: BCM63XX: enable enetsw for BCM6362
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---
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arch/mips/bcm63xx/clk.c | 4 +++-
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arch/mips/bcm63xx/dev-enet.c | 6 ++++--
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 1 +
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3 files changed, 8 insertions(+), 3 deletions(-)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -121,11 +121,13 @@ static void enetsw_set(struct clk *clk,
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{
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u32 mask;
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- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
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+ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
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return;
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if (BCMCPU_IS_6328())
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mask = CKCTL_6328_ROBOSW_EN;
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+ else if (BCMCPU_IS_6362())
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+ mask = CKCTL_6362_ROBOSW_EN;
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else
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mask = CKCTL_6368_ROBOSW_EN | CKCTL_6368_SWPKT_USB_EN |
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CKCTL_6368_SWPKT_SAR_EN;
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--- a/arch/mips/bcm63xx/dev-enet.c
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+++ b/arch/mips/bcm63xx/dev-enet.c
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@@ -141,7 +141,7 @@ static int __init register_shared(void)
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shared_res[0].end = shared_res[0].start;
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shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
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- if (BCMCPU_IS_6328() || BCMCPU_IS_6368())
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+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
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chan_count = 32;
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else
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chan_count = 16;
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@@ -224,7 +224,7 @@ bcm63xx_enetsw_register(const struct bcm
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{
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int ret;
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- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())
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+ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
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return -ENODEV;
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ret = register_shared();
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@@ -243,6 +243,8 @@ bcm63xx_enetsw_register(const struct bcm
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if (BCMCPU_IS_6328())
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enetsw_pd.num_ports = ENETSW_PORTS_6328;
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+ else if (BCMCPU_IS_6362())
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+ enetsw_pd.num_ports = ENETSW_PORTS_6362;
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else if (BCMCPU_IS_6368())
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enetsw_pd.num_ports = ENETSW_PORTS_6368;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
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@@ -44,6 +44,7 @@ struct bcm63xx_enet_platform_data {
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*/
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#define ENETSW_MAX_PORT 6
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#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
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+#define ENETSW_PORTS_6362 6 /* 4 FE PHY + 2 RGMII */
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#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
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#define ENETSW_RGMII_PORT0 4
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