mirror of https://github.com/hak5/openwrt.git
36 lines
1.3 KiB
Diff
36 lines
1.3 KiB
Diff
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From 5209e1b8f78fd1184f25cf19cf0daa58f4ad6599 Mon Sep 17 00:00:00 2001
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From: Boris Brezillon <boris.brezillon@free-electrons.com>
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Date: Thu, 1 Dec 2016 22:00:20 +0100
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Subject: [PATCH] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC
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clock
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The VEC clock requires needs to be set at exactly 108MHz. Allow rate
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change propagation on PLLH_AUX to match this requirement wihtout
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impacting other IPs (PLLH is currently only used by the HDMI encoder,
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which cannot be enabled when the VEC encoder is enabled).
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Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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(cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd)
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---
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drivers/clk/bcm/clk-bcm2835.c | 7 ++++++-
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1 file changed, 6 insertions(+), 1 deletion(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1870,7 +1870,12 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_VECCTL,
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.div_reg = CM_VECDIV,
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.int_bits = 4,
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- .frac_bits = 0),
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+ .frac_bits = 0,
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+ /*
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+ * Allow rate change propagation only on PLLH_AUX which is
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+ * assigned index 7 in the parent array.
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+ */
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+ .set_rate_parent = BIT(7)),
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/* dsi clocks */
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[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
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