mirror of https://github.com/hak5/openwrt.git
85 lines
2.3 KiB
Diff
85 lines
2.3 KiB
Diff
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From 30594cf9bfff176a9e4b14c50dcd8b9d0cc3edec Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Wed, 27 Jul 2016 11:36:51 +0200
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Subject: [PATCH 10/16] Documentation: add BCM6368 pincontroller binding
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documentation
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Add binding documentation for the pincontrol core found in BCM6368 SoCs.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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.../bindings/pinctrl/brcm,bcm6368-pinctrl.txt | 67 ++++++++++++++++++++++
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1 file changed, 67 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.txt
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@@ -0,0 +1,67 @@
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+* Broadcom BCM6368 pin controller
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+
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+Required properties:
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+- compatible: Must be "brcm,bcm6368-pinctrl".
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+- reg: Register specifiers of dirout, dat, mode registers.
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+- reg-names: Must be "dirout", "dat", "mode".
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+- brcm,gpiobasemode: Phandle to the gpio basemode register.
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+- gpio-controller: Identifies this node as a GPIO controller.
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+- #gpio-cells: Must be <2>.
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+
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+Example:
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+
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+pinctrl: pin-controller@10000080 {
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+ compatible = "brcm,bcm6368-pinctrl";
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+ reg = <0x10000080 0x08>,
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+ <0x10000088 0x08>,
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+ <0x10000098 0x04>;
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+ reg-names = "dirout", "dat", "mode";
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+ brcm,gpiobasemode = <&gpiobasemode>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+};
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+
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+gpiobasemode: syscon@100000b8 {
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+ compatible = "brcm,bcm6368-gpiobasemode", "syscon";
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+ reg = <0x100000b8 4>;
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+ native-endian;
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+};
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+
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+Available pins/groups and functions:
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+
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+name pins functions
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+-----------------------------------------------------------
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+gpio0 0 analog_afe0
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+gpio1 1 analog_afe1
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+gpio2 2 sys_irq
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+gpio3 3 serial_led_data
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+gpio4 4 serial_led_clk
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+gpio5 5 inet_led
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+gpio6 6 ephy0_led
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+gpio7 7 ephy1_led
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+gpio8 8 ephy2_led
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+gpio9 9 ephy3_led
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+gpio10 10 robosw_led_data
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+gpio11 11 robosw_led_clk
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+gpio12 12 robosw_led0
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+gpio13 13 robosw_led1
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+gpio14 14 usb_device_led
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+gpio15 15 -
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+gpio16 16 pci_req1
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+gpio17 17 pci_gnt1
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+gpio18 18 pci_intb
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+gpio19 19 pci_req0
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+gpio20 20 pci_gnt0
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+gpio21 21 -
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+gpio22 22 pcmcia_cd1
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+gpio23 23 pcmcia_cd2
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+gpio24 24 pcmcia_vs1
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+gpio25 25 pcmcia_vs2
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+gpio26 26 ebi_cs2
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+gpio27 27 ebi_cs3
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+gpio28 28 spi_cs2
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+gpio29 29 spi_cs3
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+gpio30 30 spi_cs4
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+gpio31 31 spi_cs5
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+uart1_grp 30-33 uart1
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